Lines Matching +full:0 +full:xff9a0000

10 #define ARASAN_NAND_BASEADDR	0xFF100000
12 #define ZYNQMP_TCM_BASE_ADDR	0xFFE00000
13 #define ZYNQMP_TCM_SIZE		0x40000
15 #define ZYNQMP_CRL_APB_BASEADDR	0xFF5E0000
16 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT	0x1000000
17 #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT	0
20 #define PS_MODE0	BIT(0)
31 #define RESET_REASON_EXTERNAL	BIT(0)
35 	u32 cpu_r5_ctrl; /* 0x90 */
37 	u32 timestamp_ref_ctrl; /* 0x128 */
39 	u32 boot_mode; /* 0x200 */
41 	u32 reset_reason; /* 0x220 */
43 	u32 rst_lpd_top; /* 0x23C */
45 	u32 boot_pin_ctrl; /* 0x250 */
51 #define ZYNQMP_IOU_SCNTR_SECURE	0xFF260000
52 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN	0x1
53 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG	0x2
64 #define BOOT_MODES_MASK	0x0000000F
65 #define QSPI_MODE_24BIT	0x00000001
66 #define QSPI_MODE_32BIT	0x00000002
67 #define SD_MODE		0x00000003 /* sd 0 */
68 #define SD_MODE1	0x00000005 /* sd 1 */
69 #define NAND_MODE	0x00000004
70 #define EMMC_MODE	0x00000006
71 #define USB_MODE	0x00000007
72 #define SD1_LSHFT_MODE	0x0000000E /* SD1 Level shifter */
73 #define JTAG_MODE	0x00000000
74 #define BOOT_MODE_USE_ALT	0x100
76 /* SW secondary boot modes 0xa - 0xd */
77 #define SW_USBHOST_MODE	0x0000000A
78 #define SW_SATA_MODE	0x0000000B
80 #define ZYNQMP_IOU_SLCR_BASEADDR	0xFF180000
89 #define ZYNQMP_RPU_BASEADDR	0xFF9A0000
94 	u32 rpu0_cfg; /* 0x100 */
96 	u32 rpu1_cfg; /* 0x200 */
101 #define ZYNQMP_CRF_APB_BASEADDR	0xFD1A0000
105 	u32 rst_fpd_apu; /* 0x104 */
111 #define ZYNQMP_APU_BASEADDR	0xFD5C0000
115 	u32 rvbar_addr0_l; /* 0x40 */
116 	u32 rvbar_addr0_h; /* 0x44 */
123 #define ZYNQMP_CSU_BASEADDR		0xFFCA0000
124 #define ZYNQMP_CSU_VERSION_SILICON	0x0
125 #define ZYNQMP_CSU_VERSION_QEMU		0x3
129 #define ZYNQMP_SILICON_VER_MASK		0xF000
139 #define ZYNQMP_PMU_BASEADDR	0xFFD80000
143 	u32 gen_storage6; /* 0x48 */
148 #define ZYNQMP_CSU_IDCODE_ADDR	0xFFCA0040
149 #define ZYNQMP_CSU_VER_ADDR	0xFFCA0044