Home
last modified time | relevance | path

Searched +full:0 +full:xff000 (Results 1 – 25 of 58) sorted by relevance

123

/openbmc/linux/arch/m68k/sun3/
H A Ddvma.c35 if(ptelist[(vaddr & 0xff000) >> PAGE_SHIFT] != pte) { in dvma_page()
37 ptelist[(vaddr & 0xff000) >> PAGE_SHIFT] = pte; in dvma_page()
61 return 0; in dvma_map_iommu()
67 memset(ptelist, 0, sizeof(ptelist)); in sun3_dvma_init()
/openbmc/linux/arch/s390/kernel/
H A Dmachine_kexec_reloc.c15 *(u16 *)loc &= 0xf000; in arch_kexec_do_relocs()
16 *(u16 *)loc |= val & 0xfff; in arch_kexec_do_relocs()
22 *(u32 *)loc &= 0xf00000ff; in arch_kexec_do_relocs()
23 *(u32 *)loc |= (val & 0xfff) << 16; /* DL */ in arch_kexec_do_relocs()
24 *(u32 *)loc |= (val & 0xff000) >> 4; /* DH */ in arch_kexec_do_relocs()
55 return 0; in arch_kexec_do_relocs()
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dqcom,msm8916-venus.yaml77 reg = <0x01d00000 0xff000>;
H A Dqcom,sc7180-venus.yaml103 reg = <0x0aa00000 0xff000>;
115 iommus = <&apps_smmu 0x0c00 0x60>;
H A Dqcom,sdm845-venus-v2.yaml95 reg = <0x0aa00000 0xff000>;
111 iommus = <&apps_smmu 0x10a0 0x8>,
112 <&apps_smmu 0x10b0 0x0>;
H A Dqcom,sdm845-venus.yaml105 reg = <0x0aa00000 0xff000>;
112 iommus = <&apps_smmu 0x10a0 0x8>,
113 <&apps_smmu 0x10b0 0x0>;
H A Dqcom,msm8996-venus.yaml112 reg = <0x00c00000 0xff000>;
120 iommus = <&venus_smmu 0x00>,
121 <&venus_smmu 0x01>,
122 <&venus_smmu 0x0a>,
123 <&venus_smmu 0x07>,
124 <&venus_smmu 0x0e>,
125 <&venus_smmu 0x0f>,
126 <&venus_smmu 0x08>,
127 <&venus_smmu 0x09>,
128 <&venus_smmu 0x0b>,
[all …]
H A Dqcom,sm8250-venus.yaml113 reg = <0x0aa00000 0xff000>;
129 iommus = <&apps_smmu 0x2100 0x0400>;
H A Dqcom,sdm660-venus.yaml113 reg = <0x0cc00000 0xff000>;
119 interconnects = <&gnoc 0 &mnoc 13>,
123 iommus = <&mmss_smmu 0x400>,
124 <&mmss_smmu 0x401>,
125 <&mmss_smmu 0x40a>,
126 <&mmss_smmu 0x407>,
127 <&mmss_smmu 0x40e>,
128 <&mmss_smmu 0x40f>,
129 <&mmss_smmu 0x408>,
130 <&mmss_smmu 0x409>,
[all …]
/openbmc/u-boot/arch/arm/mach-imx/
H A Dcpu.c49 case 0x00001: in get_reset_cause()
50 case 0x00011: in get_reset_cause()
52 case 0x00004: in get_reset_cause()
54 case 0x00008: in get_reset_cause()
56 case 0x00010: in get_reset_cause()
62 case 0x00020: in get_reset_cause()
64 case 0x00040: in get_reset_cause()
66 case 0x00080: in get_reset_cause()
69 case 0x00100: in get_reset_cause()
71 case 0x00200: in get_reset_cause()
[all …]
/openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dxtensa-modules.c.inc31 { "LBEG", 0, 0 },
32 { "LEND", 1, 0 },
33 { "LCOUNT", 2, 0 },
34 { "BR", 4, 0 },
35 { "PTEVADDR", 83, 0 },
36 { "DDR", 104, 0 },
37 { "CONFIGID0", 176, 0 },
38 { "CONFIGID1", 208, 0 },
39 { "INTERRUPT", 226, 0 },
40 { "INTCLEAR", 227, 0 },
[all …]
/openbmc/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_cpt.c16 #define PCI_DEVID_OTX2_CPT_PF 0xA0FD
17 #define PCI_DEVID_OTX2_CPT10K_PF 0xA0F2
24 u64 free_sts = 0, busy_sts = 0; \
28 for (e = (e_min), i = 0; e < (e_max); e++, i++) { \
30 if (reg & 0x1) \
33 if (reg & 0x2) \
50 dev_err_ratelimited(rvu->dev, "Received CPTAF FLT%d irq : 0x%llx", vec, reg); in cpt_af_flt_intr_handler()
55 case 0: in cpt_af_flt_intr_handler()
65 grp = rvu_read64(rvu, blkaddr, CPT_AF_EXEX_CTL2(eng)) & 0xFF; in cpt_af_flt_intr_handler()
67 rvu_write64(rvu, blkaddr, CPT_AF_EXEX_CTL2(eng), 0x0); in cpt_af_flt_intr_handler()
[all …]
/openbmc/linux/drivers/crypto/bcm/
H A Dspu2.h14 SPU2_CIPHER_TYPE_NONE = 0x0,
15 SPU2_CIPHER_TYPE_AES128 = 0x1,
16 SPU2_CIPHER_TYPE_AES192 = 0x2,
17 SPU2_CIPHER_TYPE_AES256 = 0x3,
18 SPU2_CIPHER_TYPE_DES = 0x4,
19 SPU2_CIPHER_TYPE_3DES = 0x5,
24 SPU2_CIPHER_MODE_ECB = 0x0,
25 SPU2_CIPHER_MODE_CBC = 0x1,
26 SPU2_CIPHER_MODE_CTR = 0x2,
27 SPU2_CIPHER_MODE_CFB = 0x3,
[all …]
/openbmc/u-boot/arch/arm/mach-imx/mx7ulp/
H A Dsoc.c22 /* Temporally hard code the CPU rev to 0x73, rev 1.0. Fix it later */ in get_cpu_rev()
35 u32 bt0_cfg = 0; in get_boot_mode()
37 bt0_cfg = readl(CMC0_RBASE + 0x40); in get_boot_mode()
53 return 0; in arch_cpu_init()
59 return 0; in board_postclk_init()
63 #define UNLOCK_WORD0 0xC520 /* 1st unlock word */
64 #define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
65 #define REFRESH_WORD0 0xA602 /* 1st refresh word */
66 #define REFRESH_WORD1 0xB480 /* 2nd refresh word */
70 writel(UNLOCK_WORD0, (wdog_base + 0x04)); in disable_wdog()
[all …]
/openbmc/u-boot/board/tqc/tqma6/
H A Dtqma6.c56 return 0; in dram_init()
59 static const uint16_t tqma6_emmc_dsr = 0x0100;
91 int ret = 0; in board_mmc_getcd()
105 int ret = 0; in board_mmc_getwp()
109 ret = 0; in board_mmc_getwp()
124 struct mmc *mmc = find_mmc_device(0); in board_mmc_init()
131 return 0; in board_mmc_init()
152 for (i = 0; i < ARRAY_SIZE(tqma6_ecspi1_cs); ++i) in tqma6_iomuxc_spi()
188 * use logical index for bus, e.g. I2C1 -> 0 in tqma6_setup_i2c()
191 ret = setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads); in tqma6_setup_i2c()
[all …]
/openbmc/linux/arch/sparc/include/asm/
H A Dleon_amba.h24 #define LEON_REG_UART_STATUS_DR 0x00000001 /* Data Ready */
25 #define LEON_REG_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */
26 #define LEON_REG_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */
27 #define LEON_REG_UART_STATUS_BR 0x00000008 /* Break Error */
28 #define LEON_REG_UART_STATUS_OE 0x00000010 /* RX Overrun Error */
29 #define LEON_REG_UART_STATUS_PE 0x00000020 /* RX Parity Error */
30 #define LEON_REG_UART_STATUS_FE 0x00000040 /* RX Framing Error */
31 #define LEON_REG_UART_STATUS_ERR 0x00000078 /* Error Mask */
37 #define LEON_REG_UART_CTRL_RE 0x00000001 /* Receiver enable */
38 #define LEON_REG_UART_CTRL_TE 0x00000002 /* Transmitter enable */
[all …]
/openbmc/u-boot/arch/arm/cpu/arm926ejs/mxs/
H A Dmxs.c53 * This function will craft a jumptable at 0x0 which will redirect interrupt
57 * ldr pc, [pc, #0x18] ..... for each vector, thus repeated 8 times
60 * The "ldr pc, [pc, #0x18]" instruction above loads address from memory at
61 * offset 0x18 from current value of PC register. Note that PC is already
63 * actually 0x20, this the associated <destination address>. Loading the PC
68 /* ldr pc, [pc, #0x18] */ in mx28_fixup_vt()
69 const uint32_t ldr_pc = 0xe59ff018; in mx28_fixup_vt()
70 /* Jumptable location is 0x0 */ in mx28_fixup_vt()
71 uint32_t *vt = (uint32_t *)0x0; in mx28_fixup_vt()
74 for (i = 0; i < 8; i++) { in mx28_fixup_vt()
[all …]
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/a38x/
H A Dsys_env_lib.h12 #define COMMON_PHY_BASE_ADDR 0x18300
14 #define DEVICE_CONFIGURATION_REG0 0x18284
15 #define DEVICE_CONFIGURATION_REG1 0x18288
16 #define COMMON_PHY_CONFIGURATION1_REG 0x18300
17 #define COMMON_PHY_CONFIGURATION2_REG 0x18304
18 #define COMMON_PHY_CONFIGURATION4_REG 0x1830c
19 #define COMMON_PHY_STATUS1_REG 0x18318
20 #define COMMON_PHYS_SELECTORS_REG 0x183fc
21 #define SOC_CONTROL_REG1 0x18204
22 #define GENERAL_PURPOSE_RESERVED0_REG 0x182e0
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Ddcore0_tpc0_cfg_masks.h24 #define DCORE0_TPC0_CFG_TPC_COUNT_V_SHIFT 0
25 #define DCORE0_TPC0_CFG_TPC_COUNT_V_MASK 0xFFFFFFFF
28 #define DCORE0_TPC0_CFG_TPC_ID_V_SHIFT 0
29 #define DCORE0_TPC0_CFG_TPC_ID_V_MASK 0xFFFFFFFF
32 #define DCORE0_TPC0_CFG_STALL_ON_ERR_V_SHIFT 0
33 #define DCORE0_TPC0_CFG_STALL_ON_ERR_V_MASK 0x1
36 #define DCORE0_TPC0_CFG_CLK_EN_LBW_CFG_DIS_SHIFT 0
37 #define DCORE0_TPC0_CFG_CLK_EN_LBW_CFG_DIS_MASK 0x1
39 #define DCORE0_TPC0_CFG_CLK_EN_DBG_CFG_DIS_MASK 0x10
42 #define DCORE0_TPC0_CFG_IQ_RL_EN_V_SHIFT 0
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dpcie.c43 .index = 0,
57 struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0]; in mpc83xx_pcie_remap_cfg()
64 * Workaround for the HW bug: for Type 0 configure transactions the in mpc83xx_pcie_remap_cfg()
66 * assumes that the device number bits are 0. in mpc83xx_pcie_remap_cfg()
68 if (devfn & 0xf8) in mpc83xx_pcie_remap_cfg()
72 return 0; in mpc83xx_pcie_remap_cfg()
76 do { *val = op((type)(addr)); } while (0)
78 do { op((type *)(addr), (val)); } while (0)
80 #define cfg_read_err(val) do { *val = -1; } while (0)
81 #define cfg_write_err(val) do { } while (0)
[all …]
/openbmc/linux/arch/riscv/kernel/
H A Dmodule.c38 return 0; in apply_r_riscv_32_rela()
44 return 0; in apply_r_riscv_64_rela()
51 u32 imm12 = (offset & 0x1000) << (31 - 12); in apply_r_riscv_branch_rela()
52 u32 imm11 = (offset & 0x800) >> (11 - 7); in apply_r_riscv_branch_rela()
53 u32 imm10_5 = (offset & 0x7e0) << (30 - 10); in apply_r_riscv_branch_rela()
54 u32 imm4_1 = (offset & 0x1e) << (11 - 4); in apply_r_riscv_branch_rela()
56 *location = (*location & 0x1fff07f) | imm12 | imm11 | imm10_5 | imm4_1; in apply_r_riscv_branch_rela()
57 return 0; in apply_r_riscv_branch_rela()
64 u32 imm20 = (offset & 0x100000) << (31 - 20); in apply_r_riscv_jal_rela()
65 u32 imm19_12 = (offset & 0xff000); in apply_r_riscv_jal_rela()
[all …]
/openbmc/u-boot/arch/arm/mach-imx/imx8/
H A Dcpu.c23 #define BT_PASSOVER_TAG 0x504F
43 if (pass_over && pass_over->g_ap_mu == 0) { in arch_cpu_init()
45 * When ap_mu is 0, means the U-Boot booted in arch_cpu_init()
53 return 0; in arch_cpu_init()
76 return 0; in arch_cpu_init_dm()
120 return 0; in print_bootinfo()
177 devno = 0; in mmc_get_env_dev()
210 debug("0x%llx -- 0x%llx\n", start, end); in get_owned_memreg()
214 return 0; in get_owned_memreg()
228 for (mr = 0; mr < 64; mr++) { in get_effective_memsize()
[all …]
/openbmc/linux/sound/soc/sof/intel/
H A Dbdw.c27 #define BDW_DSP_BAR 0
35 #define IRAM_OFFSET 0xA0000
37 #define DRAM_OFFSET 0x00000
39 #define SHIM_OFFSET 0xFB000
40 #define SHIM_SIZE 0x100
41 #define MBOX_OFFSET 0x9E000
42 #define MBOX_SIZE 0x1000
43 #define MBOX_DUMP_SIZE 0x30
44 #define EXCEPT_OFFSET 0x800
45 #define EXCEPT_MAX_HDR_SIZE 0x400
[all …]
/openbmc/linux/drivers/pinctrl/samsung/
H A Dpinctrl-s3c64xx.c33 #define SVC_GROUP_MASK 0xf
34 #define SVC_NUM_MASK 0xf
38 #define EINT12CON_REG 0x200
39 #define EINT12MASK_REG 0x240
40 #define EINT12PEND_REG 0x260
50 #define SERVICE_REG 0x284
51 #define SERVICEPEND_REG 0x288
53 #define EINT0CON0_REG 0x900
54 #define EINT0MASK_REG 0x920
55 #define EINT0PEND_REG 0x924
[all …]
/openbmc/linux/arch/powerpc/kvm/
H A Dbook3s_64_mmu.c24 #define dprintk(X...) do { } while(0)
35 for (i = 0; i < vcpu->arch.slb_nr; i++) { in kvmppc_mmu_book3s_64_find_slbe()
48 dprintk("KVM: No SLB entry found for 0x%lx [%llx | %llx]\n", in kvmppc_mmu_book3s_64_find_slbe()
50 for (i = 0; i < vcpu->arch.slb_nr; i++) { in kvmppc_mmu_book3s_64_find_slbe()
88 return 0; in kvmppc_mmu_book3s_64_ea_to_vp()
126 htabsize = ((1 << ((vcpu_book3s->sdr1 & 0x1f) + 11)) - 1); in kvmppc_mmu_book3s_64_get_pteg()
137 pteg = vcpu_book3s->sdr1 & 0xfffffffffffc0000ULL; in kvmppc_mmu_book3s_64_get_pteg()
140 dprintk("MMU: page=0x%x sdr1=0x%llx pteg=0x%llx vsid=0x%llx\n", in kvmppc_mmu_book3s_64_get_pteg()
180 if ((r & 0xf000) == 0x1000) in decode_pagesize()
184 if ((r & 0xff000) == 0) in decode_pagesize()
[all …]

123