23 #define BT_PASSOVER_TAG	0x504F
43 		if (pass_over && pass_over->g_ap_mu == 0) {  in arch_cpu_init()
45 			 * When ap_mu is 0, means the U-Boot booted  in arch_cpu_init()
53 	return 0;  in arch_cpu_init()
76 	return 0;  in arch_cpu_init_dm()
120 	return 0;  in print_bootinfo()
177 		devno = 0;  in mmc_get_env_dev()
210 		debug("0x%llx -- 0x%llx\n", start, end);  in get_owned_memreg()
214 		return 0;  in get_owned_memreg()
228 	for (mr = 0; mr < 64; mr++) {  in get_effective_memsize()
260 	for (mr = 0; mr < 64; mr++) {  in dram_init()
287 	return 0;  in dram_init()
295 	while (current_bank > 0) {  in dram_bank_sort()
317 	int i = 0;  in dram_init_banksize()
323 	for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) {  in dram_init_banksize()
358 		gd->bd->bi_dram[0].start = PHYS_SDRAM_1;  in dram_init_banksize()
359 		gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;  in dram_init_banksize()
364 	return 0;  in dram_init_banksize()
411 	/* Create map for registers access from 0x1c000000 to 0x80000000*/  in enable_caches()
412 	imx8_mem_map[0].virt = 0x1c000000UL;  in enable_caches()
413 	imx8_mem_map[0].phys = 0x1c000000UL;  in enable_caches()
414 	imx8_mem_map[0].size = 0x64000000UL;  in enable_caches()
415 	imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |  in enable_caches()
419 	for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) {  in enable_caches()
431 		imx8_mem_map[i].size = 0;  in enable_caches()
432 		imx8_mem_map[i].attrs = 0;  in enable_caches()
439 	for (i = 0; i < MAX_MEM_MAP_REGIONS; i++) {  in enable_caches()
440 		debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n",  in enable_caches()
453 	u64 size = 0;  in get_page_table_size()
487 	if (dev_id == 0) {  in imx_get_mac_from_fuse()
488 		word[0] = FUSE_MAC0_WORD0;  in imx_get_mac_from_fuse()
491 		word[0] = FUSE_MAC1_WORD0;  in imx_get_mac_from_fuse()
495 	for (i = 0; i < 2; i++) {  in imx_get_mac_from_fuse()
497 		if (ret < 0)  in imx_get_mac_from_fuse()
501 	mac[0] = val[0];  in imx_get_mac_from_fuse()
502 	mac[1] = val[0] >> 8;  in imx_get_mac_from_fuse()
503 	mac[2] = val[0] >> 16;  in imx_get_mac_from_fuse()
504 	mac[3] = val[0] >> 24;  in imx_get_mac_from_fuse()
509 	      __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);  in imx_get_mac_from_fuse()
517 	u32 id = 0, rev = 0;  in get_cpu_rev()
522 		return 0;  in get_cpu_rev()
524 	rev = (id >> 5)  & 0xf;  in get_cpu_rev()
525 	id = (id & 0x1f) + MXC_SOC_IMX8;  /* Dummy ID for chip */  in get_cpu_rev()
584 	return 0;  in cpu_imx_get_desc()
593 	return 0;  in cpu_imx_get_info()
604 	return 0;  in cpu_imx_get_vendor()
628 		return 0;  in imx8_get_cpu_rate()
642 	plat->rev = get_imx8_rev(cpurev & 0xFFF);  in imx8_cpu_probe()
643 	plat->type = get_imx8_type((cpurev & 0xFF000) >> 12);  in imx8_cpu_probe()
645 	return 0;  in imx8_cpu_probe()