Lines Matching +full:0 +full:xff000
12 #define COMMON_PHY_BASE_ADDR 0x18300
14 #define DEVICE_CONFIGURATION_REG0 0x18284
15 #define DEVICE_CONFIGURATION_REG1 0x18288
16 #define COMMON_PHY_CONFIGURATION1_REG 0x18300
17 #define COMMON_PHY_CONFIGURATION2_REG 0x18304
18 #define COMMON_PHY_CONFIGURATION4_REG 0x1830c
19 #define COMMON_PHY_STATUS1_REG 0x18318
20 #define COMMON_PHYS_SELECTORS_REG 0x183fc
21 #define SOC_CONTROL_REG1 0x18204
22 #define GENERAL_PURPOSE_RESERVED0_REG 0x182e0
23 #define GBE_CONFIGURATION_REG 0x18460
24 #define DEVICE_SAMPLE_AT_RESET1_REG 0x18600
25 #define DEVICE_SAMPLE_AT_RESET2_REG 0x18604
26 #define DEV_ID_REG 0x18238
28 #define CORE_PLL_PARAMETERS_REG 0xe42e0
29 #define CORE_PLL_CONFIG_REG 0xe42e4
31 #define QSGMII_CONTROL_REG1 0x18494
34 #define DEV_ID_REG_DEVICE_ID_MASK 0xffff0000
37 #define SAR_DEV_ID_MASK 0x7
39 #define POWER_AND_PLL_CTRL_REG 0xa0004
40 #define CALIBRATION_CTRL_REG 0xa0008
41 #define DFE_REG0 0xa001c
42 #define DFE_REG3 0xa0028
43 #define RESET_DFE_REG 0xa0148
44 #define LOOPBACK_REG 0xa008c
45 #define SYNC_PATTERN_REG 0xa0090
46 #define INTERFACE_REG 0xa0094
47 #define ISOLATE_REG 0xa0098
48 #define MISC_REG 0xa013c
49 #define GLUE_REG 0xa0140
50 #define GENERATION_DIVIDER_FORCE_REG 0xa0144
51 #define PCIE_REG0 0xa0120
52 #define LANE_ALIGN_REG0 0xa0124
53 #define SQUELCH_FFE_SETTING_REG 0xa0018
54 #define G1_SETTINGS_0_REG 0xa0034
55 #define G1_SETTINGS_1_REG 0xa0038
56 #define G1_SETTINGS_3_REG 0xa0440
57 #define G1_SETTINGS_4_REG 0xa0444
58 #define G2_SETTINGS_0_REG 0xa003c
59 #define G2_SETTINGS_1_REG 0xa0040
60 #define G2_SETTINGS_2_REG 0xa00f8
61 #define G2_SETTINGS_3_REG 0xa0448
62 #define G2_SETTINGS_4_REG 0xa044c
63 #define G3_SETTINGS_0_REG 0xa0044
64 #define G3_SETTINGS_1_REG 0xa0048
65 #define G3_SETTINGS_3_REG 0xa0450
66 #define G3_SETTINGS_4_REG 0xa0454
67 #define VTHIMPCAL_CTRL_REG 0xa0104
68 #define REF_REG0 0xa0134
69 #define CAL_REG6 0xa0168
70 #define RX_REG2 0xa0184
71 #define RX_REG3 0xa0188
72 #define PCIE_REG1 0xa0288
73 #define PCIE_REG3 0xa0290
74 #define LANE_CFG0_REG 0xa0600
75 #define LANE_CFG1_REG 0xa0604
76 #define LANE_CFG4_REG 0xa0620
77 #define LANE_CFG5_REG 0xa0624
78 #define GLOBAL_CLK_CTRL 0xa0704
79 #define GLOBAL_MISC_CTRL 0xa0718
80 #define GLOBAL_CLK_SRC_HI 0xa0710
82 #define GLOBAL_CLK_CTRL 0xa0704
83 #define GLOBAL_MISC_CTRL 0xa0718
84 #define GLOBAL_PM_CTRL 0xa0740
87 #define SATA_CTRL_REG_IND_ADDR 0xa80a0
88 #define SATA_CTRL_REG_IND_DATA 0xa80a4
90 #define SATA_VENDOR_PORT_0_REG_ADDR 0xa8178
91 #define SATA_VENDOR_PORT_1_REG_ADDR 0xa81f8
92 #define SATA_VENDOR_PORT_0_REG_DATA 0xa817c
93 #define SATA_VENDOR_PORT_1_REG_DATA 0xa81fc
96 #define POWER_AND_PLL_CTRL_REG_100MHZ_VAL 0x0
97 #define POWER_AND_PLL_CTRL_REG_25MHZ_VAL_1 0x1
98 #define POWER_AND_PLL_CTRL_REG_25MHZ_VAL_2 0x2
99 #define POWER_AND_PLL_CTRL_REG_40MHZ_VAL 0x3
100 #define GLOBAL_PM_CTRL_REG_25MHZ_VAL 0x7
101 #define GLOBAL_PM_CTRL_REG_40MHZ_VAL 0xc
102 #define LANE_CFG4_REG_25MHZ_VAL 0x200
103 #define LANE_CFG4_REG_40MHZ_VAL 0x300
105 #define POWER_AND_PLL_CTRL_REG_MASK (~(0x1f))
106 #define GLOBAL_PM_CTRL_REG_MASK (~(0xff))
107 #define LANE_CFG4_REG_MASK (~(0x1f00))
109 #define REF_CLK_SELECTOR_VAL_PEX0(reg_val) (reg_val >> 2) & 0x1
110 #define REF_CLK_SELECTOR_VAL_PEX1(reg_val) (reg_val >> 3) & 0x1
111 #define REF_CLK_SELECTOR_VAL_PEX2(reg_val) (reg_val >> 30) & 0x1
112 #define REF_CLK_SELECTOR_VAL_PEX3(reg_val) (reg_val >> 31) & 0x1
113 #define REF_CLK_SELECTOR_VAL(reg_val) (reg_val & 0x1)
118 /* starting from A38x A0, i2c address of EEPROM is 0x57 */
120 #define EEPROM_I2C_ADDR 0x50
123 MV_88F68XX_Z1_ID ? 0x50 : 0x57)
125 #define RD_GET_MODE_ADDR 0x4c
126 #define DB_GET_MODE_SLM1363_ADDR 0x25
127 #define DB_GET_MODE_SLM1364_ADDR 0x24
128 #define DB381_GET_MODE_SLM1426_1427_ADDR 0x56
132 #define SATR_DB_LANE1_CFG_MASK 0x7
133 #define SATR_DB_LANE1_CFG_OFFSET 0
135 #define SATR_DB_LANE2_CFG_MASK 0x38
139 #define SATR_GP_LANE1_CFG_MASK 0x4
141 #define SATR_GP_LANE2_CFG_MASK 0x8
144 /* For setting MPP2 and MPP3 to be TWSI mode and MPP 0,1 to UART mode */
145 #define MPP_CTRL_REG 0x18000
146 #define MPP_SET_MASK (~(0xffff))
147 #define MPP_SET_DATA (0x1111)
148 #define MPP_UART1_SET_MASK (~(0xff000))
149 #define MPP_UART1_SET_DATA (0x66000)
151 #define AVS_DEBUG_CNTR_REG 0xe4124
152 #define AVS_DEBUG_CNTR_DEFAULT_VALUE 0x08008073
154 #define AVS_ENABLED_CONTROL 0xe4130
156 #define AVS_LOW_VDD_LIMIT_MASK (0xff << AVS_LOW_VDD_LIMIT_OFFS)
157 #define AVS_LOW_VDD_LIMIT_VAL (0x27 << AVS_LOW_VDD_LIMIT_OFFS)
160 #define AVS_HIGH_VDD_LIMIT_MASK (0xff << AVS_HIGH_VDD_LIMIT_OFFS)
161 #define AVS_HIGH_VDD_LIMIT_VAL (0x27 << AVS_HIGH_VDD_LIMIT_OFFS)
164 #define MARVELL_BOARD_ID_MASK 0x10
166 #define A38X_CUSTOMER_BOARD_ID_BASE 0x0
167 #define A38X_CUSTOMER_BOARD_ID0 (A38X_CUSTOMER_BOARD_ID_BASE + 0)
174 #define A38X_MARVELL_BOARD_ID_BASE 0x10
175 #define RD_NAS_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 0)
187 #define A39X_CUSTOMER_BOARD_ID_BASE 0x20
188 #define A39X_CUSTOMER_BOARD_ID0 (A39X_CUSTOMER_BOARD_ID_BASE + 0)
195 #define A39X_MARVELL_BOARD_ID_BASE 0x30
196 #define A39X_DB_69XX_ID (A39X_MARVELL_BOARD_ID_BASE + 0)
226 #define MV_INVALID_BOARD_ID 0xffffffff
229 #define DEV_VERSION_ID_REG 0x1823c
231 #define REVISON_ID_MASK 0xf00
234 #define MV_88F68XX_Z1_ID 0x0
235 #define MV_88F68XX_A0_ID 0x4
236 #define MV_88F68XX_B0_ID 0xa
238 #define MV_88F69XX_Z1_ID 0x2
240 #define MPP_CONTROL_REG(id) (0x18000 + (id * 4))
241 #define GPP_DATA_OUT_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x00)
242 #define GPP_DATA_OUT_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x04)
243 #define GPP_DATA_IN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x10)
244 #define MV_GPP_REGS_BASE(unit) (0x18100 + ((unit) * 0x40))
247 #define MPP_MASK(GPIO_NUM) (0xf << 4 * (GPIO_NUM - \
254 #define MV_6810_DEV_ID 0x6810
255 #define MV_6811_DEV_ID 0x6811
256 #define MV_6820_DEV_ID 0x6820
257 #define MV_6828_DEV_ID 0x6828
259 #define MV_6920_DEV_ID 0x6920
260 #define MV_6928_DEV_ID 0x6928
273 #define MV_6820_INDEX 0
278 #define MV_6920_INDEX 0
287 #define MV_6820_INDEX 0
291 #define MV_6920_INDEX 0