22 	/* Temporally hard code the CPU rev to 0x73, rev 1.0. Fix it later */  in get_cpu_rev()
35 	u32 bt0_cfg = 0;  in get_boot_mode()
37 	bt0_cfg = readl(CMC0_RBASE + 0x40);  in get_boot_mode()
53 	return 0;  in arch_cpu_init()
59 	return 0;  in board_postclk_init()
63 #define UNLOCK_WORD0 0xC520 /* 1st unlock word */
64 #define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
65 #define REFRESH_WORD0 0xA602 /* 1st refresh word */
66 #define REFRESH_WORD1 0xB480 /* 2nd refresh word */
70 	writel(UNLOCK_WORD0, (wdog_base + 0x04));  in disable_wdog()
71 	writel(UNLOCK_WORD1, (wdog_base + 0x04));  in disable_wdog()
72 	writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */  in disable_wdog()
73 	writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */  in disable_wdog()
74 	writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */  in disable_wdog()
76 	writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */  in disable_wdog()
77 	writel(REFRESH_WORD1, (wdog_base + 0x04));  in disable_wdog()
134 	       get_imx_type((cpurev & 0xFF000) >> 12),  in print_cpuinfo()
135 	       (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0,  in print_cpuinfo()
154 	return 0;  in print_cpuinfo()
171 #define CMC_SRS_WUP                       (1 << 0)
177 	u32 cause1, cause = 0, srs = 0;  in get_reset_cause()
178 	u32 *reg_ssrs = (u32 *)(SRC_BASE_ADDR + 0x28);  in get_reset_cause()
179 	u32 *reg_srs = (u32 *)(SRC_BASE_ADDR + 0x20);  in get_reset_cause()
234 	int devno = 0;  in mmc_get_env_dev()
235 	u32 bt1_cfg = 0;  in mmc_get_env_dev()
241 	bt1_cfg = readl(CMC1_RBASE + 0x40);  in mmc_get_env_dev()
242 	devno = (bt1_cfg >> 9) & 0x7;  in mmc_get_env_dev()