Searched +full:0 +full:xe6020000 (Results 1 – 25 of 41) sorted by relevance
12
14 #define RWDT_BASE 0xE602000015 #define SWDT_BASE 0xE603000016 #define LBSC_BASE 0xEE22020017 #define TMU_BASE 0xE61E000018 #define GPIO5_BASE 0xE605500021 #define SCIF0_BASE 0xE6E6000022 #define SCIF1_BASE 0xE6E6800023 #define SCIF2_BASE 0xE6E8800024 #define SCIF3_BASE 0xE6C5000025 #define SCIF4_BASE 0xE6C40000[all …]
13 #define MERAM_BASE 0xE558000014 #define DDRP_BASE 0xC12A000015 #define HPB_BASE 0xE600000016 #define RWDT0_BASE 0xE602000017 #define RWDT1_BASE 0xE603000018 #define GPIO_BASE 0xE605000019 #define CMT1_BASE 0xE613800020 #define CPG_BASE 0xE615000021 #define SYSC_BASE 0xE618000022 #define SDHI0_BASE 0xE6850000[all …]
5 #define GLOBAL_TIMER_BASE_ADDR (0xF0000200)6 #define MERAM_BASE (0xE5580000)9 #define GIC_BASE (0xF0000100)13 #define LIFEC_SEC_SRC (0xE6110008)16 #define RWDT_BASE (0xE6020000)19 #define HPB_BASE (0xE6001010)22 #define HPBSCR_BASE (0xE6001600)25 #define SBSC1_BASE (0xFE400000)26 #define SDMRA1A (SBSC1_BASE + 0x100000)27 #define SDMRA2A (SBSC1_BASE + 0x1C0000)[all …]
14 #define RWDT_BASE 0xE602000015 #define SWDT_BASE 0xE603000016 #define LBSC_BASE 0xFEC0020017 #define DBSC3_0_BASE 0xE679000018 #define DBSC3_1_BASE 0xE67A000019 #define TMU_BASE 0xE61E000020 #define GPIO5_BASE 0xE605500021 #define SH_QSPI_BASE 0xE6B1000024 #define SCIF0_BASE 0xE6E6000025 #define SCIF1_BASE 0xE6E68000[all …]
181 reg = <0xe6020000 0x0c>;
19 #size-cells = <0>;21 a53_0: cpu@0 {23 reg = <0>;39 L2_CA53: cache-controller-0 {49 #clock-cells = <0>;51 clock-frequency = <0>;76 reg = <0 0xe6020000 0 0x0c>;86 reg = <0 0xe6050000 0 0x50>;90 gpio-ranges = <&pfc 0 0 18>;101 reg = <0 0xe6051000 0 0x50>;[all …]
39 #clock-cells = <0>;41 clock-frequency = <0>;46 #size-cells = <0>;49 cpu0: cpu@0 {52 reg = <0>;69 L2_CA15: cache-controller-0 {80 #clock-cells = <0>;82 clock-frequency = <0>;95 #clock-cells = <0>;97 clock-frequency = <0>;[all …]
29 #size-cells = <0>;31 a53_0: cpu@0 {34 reg = <0>;61 #clock-cells = <0>;63 clock-frequency = <0>;68 #clock-cells = <0>;70 clock-frequency = <0>;88 #clock-cells = <0>;89 clock-frequency = <0>;95 #clock-cells = <0>;[all …]
21 #clock-cells = <0>;22 clock-frequency = <0>;27 #size-cells = <0>;29 a53_0: cpu@0 {31 reg = <0x0>;48 #clock-cells = <0>;50 clock-frequency = <0>;65 #clock-cells = <0>;66 clock-frequency = <0>;79 reg = <0 0xe6020000 0 0x0c>;[all …]
34 * The external audio clocks are configured as 0 Hz fixed frequency40 #clock-cells = <0>;41 clock-frequency = <0>;45 #clock-cells = <0>;46 clock-frequency = <0>;50 #clock-cells = <0>;51 clock-frequency = <0>;57 #clock-cells = <0>;59 clock-frequency = <0>;64 #size-cells = <0>;[all …]
32 * The external audio clocks are configured as 0 Hz fixed frequency38 #clock-cells = <0>;39 clock-frequency = <0>;43 #clock-cells = <0>;44 clock-frequency = <0>;48 #clock-cells = <0>;49 clock-frequency = <0>;55 #clock-cells = <0>;57 clock-frequency = <0>;62 #size-cells = <0>;[all …]
40 * The external audio clocks are configured as 0 Hz fixed frequency46 #clock-cells = <0>;47 clock-frequency = <0>;51 #clock-cells = <0>;52 clock-frequency = <0>;56 #clock-cells = <0>;57 clock-frequency = <0>;63 #clock-cells = <0>;65 clock-frequency = <0>;70 #size-cells = <0>;[all …]
34 * The external audio clocks are configured as 0 Hz fixed frequency40 #clock-cells = <0>;41 clock-frequency = <0>;46 #clock-cells = <0>;47 clock-frequency = <0>;52 #clock-cells = <0>;53 clock-frequency = <0>;59 #clock-cells = <0>;60 clock-frequency = <0>;65 #size-cells = <0>;[all …]
40 #clock-cells = <0>;42 clock-frequency = <0>;47 #size-cells = <0>;49 cpu0: cpu@0 {52 reg = <0>;71 L2_CA15: cache-controller-0 {82 #clock-cells = <0>;84 clock-frequency = <0>;97 #clock-cells = <0>;99 clock-frequency = <0>;[all …]
27 #size-cells = <0>;29 cpu0: cpu@0 {32 reg = <0>;51 L2_CA7: cache-controller-0 {62 #clock-cells = <0>;64 clock-frequency = <0>;77 #clock-cells = <0>;79 clock-frequency = <0>;93 reg = <0 0xe6020000 0 0x0c>;104 reg = <0 0xe6050000 0 0x50>;[all …]
36 * The external audio clocks are configured as 0 Hz fixed42 #clock-cells = <0>;43 clock-frequency = <0>;47 #clock-cells = <0>;48 clock-frequency = <0>;52 #clock-cells = <0>;53 clock-frequency = <0>;59 #clock-cells = <0>;61 clock-frequency = <0>;66 #size-cells = <0>;[all …]
19 * The external audio clocks are configured as 0 Hz fixed frequency25 #clock-cells = <0>;26 clock-frequency = <0>;30 #clock-cells = <0>;31 clock-frequency = <0>;35 #clock-cells = <0>;36 clock-frequency = <0>;42 #clock-cells = <0>;44 clock-frequency = <0>;49 #size-cells = <0>;[all …]
19 * The external audio clocks are configured as 0 Hz fixed frequency25 #clock-cells = <0>;26 clock-frequency = <0>;31 #clock-cells = <0>;32 clock-frequency = <0>;37 #clock-cells = <0>;38 clock-frequency = <0>;44 #clock-cells = <0>;46 clock-frequency = <0>;51 #size-cells = <0>;[all …]
22 #clock-cells = <0>;23 clock-frequency = <0>;28 #size-cells = <0>;30 a53_0: cpu@0 {33 reg = <0>;60 #clock-cells = <0>;62 clock-frequency = <0>;67 #clock-cells = <0>;69 clock-frequency = <0>;87 #clock-cells = <0>;[all …]
17 cluster01_opp: opp-table-0 {73 #size-cells = <0>;113 a55_0: cpu@0 {115 reg = <0>;127 reg = <0x100>;139 reg = <0x10000>;151 reg = <0x10100>;163 reg = <0x20000>;175 reg = <0x20100>;187 reg = <0x30000>;[all …]
22 #clock-cells = <0>;23 clock-frequency = <0>;28 #size-cells = <0>;30 a53_0: cpu@0 {33 reg = <0>;80 #clock-cells = <0>;82 clock-frequency = <0>;87 #clock-cells = <0>;89 clock-frequency = <0>;95 #clock-cells = <0>;[all …]
19 * The external audio clocks are configured as 0 Hz fixed frequency25 #clock-cells = <0>;26 clock-frequency = <0>;31 #clock-cells = <0>;32 clock-frequency = <0>;38 #clock-cells = <0>;39 clock-frequency = <0>;44 #size-cells = <0>;46 a53_0: cpu@0 {48 reg = <0x0>;[all …]