Lines Matching +full:0 +full:xe6020000
29 #size-cells = <0>;
31 a53_0: cpu@0 {
34 reg = <0>;
61 #clock-cells = <0>;
63 clock-frequency = <0>;
68 #clock-cells = <0>;
70 clock-frequency = <0>;
88 #clock-cells = <0>;
89 clock-frequency = <0>;
95 #clock-cells = <0>;
96 clock-frequency = <0>;
110 reg = <0 0xe6020000 0 0x0c>;
120 reg = <0 0xe6050000 0 0x50>;
124 gpio-ranges = <&pfc 0 0 22>;
135 reg = <0 0xe6051000 0 0x50>;
139 gpio-ranges = <&pfc 0 32 28>;
150 reg = <0 0xe6052000 0 0x50>;
154 gpio-ranges = <&pfc 0 64 17>;
165 reg = <0 0xe6053000 0 0x50>;
169 gpio-ranges = <&pfc 0 96 17>;
180 reg = <0 0xe6054000 0 0x50>;
184 gpio-ranges = <&pfc 0 128 6>;
195 reg = <0 0xe6055000 0 0x50>;
199 gpio-ranges = <&pfc 0 160 15>;
209 reg = <0 0xe6060000 0 0x504>;
214 reg = <0 0xe6150000 0 0x1000>;
218 #power-domain-cells = <0>;
224 reg = <0 0xe6160000 0 0x200>;
229 reg = <0 0xe6180000 0 0x440>;
237 reg = <0 0xe61c0000 0 0x200>;
238 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
252 reg = <0 0xe6500000 0 0x40>;
257 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
258 <&dmac2 0x91>, <&dmac2 0x90>;
262 #size-cells = <0>;
269 reg = <0 0xe6508000 0 0x40>;
274 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
275 <&dmac2 0x93>, <&dmac2 0x92>;
279 #size-cells = <0>;
286 reg = <0 0xe6510000 0 0x40>;
291 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
292 <&dmac2 0x95>, <&dmac2 0x94>;
296 #size-cells = <0>;
303 reg = <0 0xe66d0000 0 0x40>;
308 dmas = <&dmac1 0x97>, <&dmac1 0x96>,
309 <&dmac2 0x97>, <&dmac2 0x96>;
313 #size-cells = <0>;
320 reg = <0 0xe66d8000 0 0x40>;
325 dmas = <&dmac1 0x99>, <&dmac1 0x98>,
326 <&dmac2 0x99>, <&dmac2 0x98>;
330 #size-cells = <0>;
338 reg = <0 0xe6540000 0 96>;
344 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
345 <&dmac2 0x31>, <&dmac2 0x30>;
356 reg = <0 0xe6550000 0 96>;
362 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
363 <&dmac2 0x33>, <&dmac2 0x32>;
374 reg = <0 0xe6560000 0 96>;
380 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
381 <&dmac2 0x35>, <&dmac2 0x34>;
391 reg = <0 0xe66a0000 0 96>;
397 dmas = <&dmac1 0x37>, <&dmac1 0x36>,
398 <&dmac2 0x37>, <&dmac2 0x36>;
408 reg = <0 0xe66c0000 0 0x8000>;
433 reg = <0 0xe6800000 0 0x800>;
472 #size-cells = <0>;
480 reg = <0 0xe6e60000 0 64>;
486 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
487 <&dmac2 0x51>, <&dmac2 0x50>;
498 reg = <0 0xe6e68000 0 64>;
504 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
505 <&dmac2 0x53>, <&dmac2 0x52>;
516 reg = <0 0xe6c50000 0 64>;
522 dmas = <&dmac1 0x57>, <&dmac1 0x56>,
523 <&dmac2 0x57>, <&dmac2 0x56>;
533 reg = <0 0xe6c40000 0 64>;
539 dmas = <&dmac1 0x59>, <&dmac1 0x58>,
540 <&dmac2 0x59>, <&dmac2 0x58>;
550 reg = <0 0xe6ef0000 0 0x1000>;
555 renesas,id = <0>;
560 #size-cells = <0>;
564 #size-cells = <0>;
578 reg = <0 0xe6ef1000 0 0x1000>;
588 #size-cells = <0>;
592 #size-cells = <0>;
606 reg = <0 0xe6ef2000 0 0x1000>;
616 #size-cells = <0>;
620 #size-cells = <0>;
634 reg = <0 0xe6ef3000 0 0x1000>;
644 #size-cells = <0>;
648 #size-cells = <0>;
663 reg = <0 0xe7300000 0 0x10000>;
682 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
691 reg = <0 0xe7310000 0 0x10000>;
718 reg = <0 0xe7740000 0 0x1000>;
719 renesas,ipmmu-main = <&ipmmu_mm 0>;
726 reg = <0 0xff8b0000 0 0x1000>;
734 reg = <0 0xe67b0000 0 0x1000>;
743 reg = <0 0xffc80000 0 0x1000>;
751 reg = <0 0xfebd0000 0 0x1000>;
760 #address-cells = <0>;
762 reg = <0 0xf1010000 0 0x1000>,
763 <0 0xf1020000 0 0x20000>,
764 <0 0xf1040000 0 0x20000>,
765 <0 0xf1060000 0 0x20000>;
776 reg = <0 0xfea20000 0 0x5000>;
786 reg = <0 0xfea27000 0 0x200>;
794 reg = <0 0xfeaa0000 0 0x10000>;
803 #size-cells = <0>;
807 #size-cells = <0>;
811 csi40vin0: endpoint@0 {
812 reg = <0>;
833 reg = <0 0xfeb00000 0 0x80000>;
836 clock-names = "du.0";
844 #size-cells = <0>;
846 port@0 {
847 reg = <0>;
863 reg = <0 0xfeb90000 0 0x14>;
871 #size-cells = <0>;
873 port@0 {
874 reg = <0>;
890 reg = <0 0xfff00044 0 4>;