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/openbmc/openbmc/meta-phosphor/recipes-phosphor/ipmi/phosphor-ipmi-sensor-inventory/
H A Dconfig.yaml1 0x03:
2 entityID: 0x22
4 sensorType: 0x0F
6 sensorReadingType: 0x6F
15 0x13:
18 0x00:
21 0x01:
24 0x03:
27 0x07:
30 0x14:
[all …]
/openbmc/u-boot/include/mtd/
H A Dcfi_flash.h10 #define FLASH_CMD_CFI 0x98
11 #define FLASH_CMD_READ_ID 0x90
12 #define FLASH_CMD_RESET 0xff
13 #define FLASH_CMD_BLOCK_ERASE 0x20
14 #define FLASH_CMD_ERASE_CONFIRM 0xD0
15 #define FLASH_CMD_WRITE 0x40
16 #define FLASH_CMD_PROTECT 0x60
17 #define FLASH_CMD_SETUP 0x60
18 #define FLASH_CMD_SET_CR_CONFIRM 0x03
19 #define FLASH_CMD_PROTECT_SET 0x01
[all …]
/openbmc/u-boot/drivers/pci/
H A Daspeed_pcie_phy.c14 #define ASPEED_PCIE_CLASS_CODE 0x04
15 #define ASPEED_PCIE_GLOBAL 0x30
16 #define ASPEED_PCIE_CFG_DIN 0x50
17 #define ASPEED_PCIE_CFG3 0x58
18 #define ASPEED_PCIE_LOCK 0x7C
19 #define ASPEED_PCIE_LINK 0xC0
20 #define ASPEED_PCIE_INT 0xC4
21 #define ASPEED_PCIE_LINK_STS 0xD0
23 /* AST_PCIE_CFG2 0x04 */
27 /* AST_PCIE_GLOBAL 0x30 */
[all …]
H A Dpcie_aspeed.h7 /* reg 0x24 */
11 #define PCIE_RC_TX_COMPLETE 0
15 #define PCIE_TRIGGER_TX BIT(0)
17 #define PCIE_RC_L 0x80
18 #define PCIE_RC_H 0xC0
19 /* reg 0x80, 0xC0 */
29 #define PCIE_RC_ENABLE BIT(0)
31 /* reg 0x88, 0xC8 : RC ISR */
39 #define PCIE_RC_INTA_ISR BIT(0)
45 u32 h2x_rdata; //0x0c
[all …]
/openbmc/qemu/ebpf/
H A Drss.bpf.skeleton.h146 s->maps[0].name = "tap_rss_map_configurations"; in rss_bpf__create_skeleton()
147 s->maps[0].map = &obj->maps.tap_rss_map_configurations; in rss_bpf__create_skeleton()
164 s->progs[0].name = "tun_rss_steering_prog"; in rss_bpf__create_skeleton()
165 s->progs[0].prog = &obj->progs.tun_rss_steering_prog; in rss_bpf__create_skeleton()
166 s->progs[0].link = &obj->links.tun_rss_steering_prog; in rss_bpf__create_skeleton()
171 return 0; in rss_bpf__create_skeleton()
180 \x7f\x45\x4c\x46\x02\x01\x01\0\0\0\0\0\0\0\0\0\x01\0\xf7\0\x01\0\0\0\0\0\0\0\0\ in rss_bpf__elf_bytes()
181 \0\0\0\0\0\0\0\0\0\0\0\xb0\x4b\0\0\0\0\0\0\0\0\0\0\x40\0\0\0\0\0\x40\0\x0d\0\ in rss_bpf__elf_bytes()
182 \x01\0\x7b\x1a\x48\xff\0\0\0\0\xb7\x09\0\0\0\0\0\0\x63\x9a\x54\xff\0\0\0\0\xbf\ in rss_bpf__elf_bytes()
183 \xa7\0\0\0\0\0\0\x07\x07\0\0\x54\xff\xff\xff\x18\x01\0\0\0\0\0\0\0\0\0\0\0\0\0\ in rss_bpf__elf_bytes()
[all …]
/openbmc/openbmc/meta-phosphor/recipes-phosphor/ipmi/phosphor-ipmi-inventory-sel-mrw/
H A Dconfig.yaml2 0x01:
3 SensorType: 0x12
4 Offset: 0x02
6 0x03:
7 SensorType: 0x07
8 Offset: 0x08
10 0x07:
11 SensorType: 0xC7
12 Offset: 0x00
14 0x20:
[all …]
/openbmc/u-boot/lib/tizen/
H A Dtizen_logo_16bpp_gzip.h12 0x1f,0x8b,0x08,0x08,0xd9,0x76,0x29,0x53,0x00,0x03,0x74,0x69,0x7a,0x65,0x6e,0x5f,
13 0x6c,0x6f,0x67,0x6f,0x2e,0x62,0x6d,0x70,0x00,0xed,0x9d,0x6f,0x6c,0x1b,0x67,0x7e,
14 0xe7,0xa9,0x4d,0x80,0x65,0xbb,0x2e,0x56,0xb1,0xd8,0x25,0xcf,0x0a,0x70,0x52,0xa4,
15 0x2d,0xc2,0x5a,0x39,0x58,0x35,0xf7,0x42,0x35,0x7a,0x63,0xd5,0x6a,0x1b,0x9d,0x5c,
16 0xd4,0x0a,0x85,0xca,0xde,0x35,0x70,0x1b,0xc7,0x29,0xbc,0xaa,0xbb,0x50,0x14,0x0a,
17 0xd6,0x79,0xdf,0x9c,0x2b,0x07,0x88,0xa1,0xb8,0x88,0x4a,0x11,0x2b,0x83,0x7a,0x71,
18 0xc9,0xd2,0x6e,0x1d,0x4c,0x76,0xa1,0x60,0x28,0x44,0xc5,0xe8,0x8d,0x6b,0xba,0xbd,
19 0x14,0xca,0x56,0xba,0x0e,0x51,0x05,0x70,0x0b,0x24,0xa8,0x83,0x7a,0xef,0x5c,0x54,
20 0x77,0x61,0x6a,0xbf,0xb9,0x79,0xe6,0x99,0xe7,0x79,0x7e,0xf3,0x87,0x9c,0x67,0x86,
21 0xc3,0x7f,0xca,0xf3,0x7d,0x30,0x1a,0x92,0xe2,0x9f,0x21,0x39,0x1f,0x7e,0x7f,0xcf,
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp-zcu102-rev1.0.dts3 * dts file for Xilinx ZynqMP ZCU102 Rev1.0
13 model = "ZynqMP ZCU102 Rev1.0";
14 compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
21 board_sn: board-sn@0 {
22 reg = <0x0 0x14>;
26 reg = <0x20 0x6>;
30 reg = <0xd0 0x6>;
34 reg = <0xe0 0x3>;
/openbmc/qemu/tests/unit/
H A Dtest-crypto-akcipher.c29 0x30, 0x82, 0x02, 0x5c, 0x02, 0x01, 0x00, 0x02,
30 0x81, 0x81, 0x00, 0xe6, 0x4d, 0x76, 0x4f, 0xb2,
31 0x97, 0x09, 0xad, 0x9d, 0x17, 0x33, 0xf2, 0x30,
32 0x42, 0x83, 0xa9, 0xcb, 0x49, 0xa4, 0x2e, 0x59,
33 0x5e, 0x75, 0x51, 0xd1, 0xac, 0xc8, 0x86, 0x3e,
34 0xdb, 0x72, 0x2e, 0xb2, 0xf7, 0xc3, 0x5b, 0xc7,
35 0xea, 0xed, 0x30, 0xd1, 0xf7, 0x37, 0xee, 0x9d,
36 0x36, 0x59, 0x6f, 0xf8, 0xce, 0xc0, 0x5c, 0x82,
37 0x80, 0x37, 0x83, 0xd7, 0x45, 0x6a, 0xe9, 0xea,
38 0xc5, 0x3a, 0x59, 0x6b, 0x34, 0x31, 0x44, 0x00,
[all …]
H A Dtest-crypto-der.c27 "\x30\x82\x01\x39" /* SEQUENCE, offset: 0, length: 313 */
32 "\xc8\x34\x0c\x12\x4f\x11\x90\xc6\xc2\xa5\xd0\xcd\xfb\xfc\x2c\x95"
43 "\x8d\x05\x48\xdd\xff\x5c\x30\xbc\x6b\xc4\x18\x9d\xfc\xa2\xd0\x9b"
60 "\x30\x82\x04\xa6" /* SEQUENCE, offset: 0, length 1190 */
103 "\x77\x73\x08\x0f\x32\xbd\xe6\x95\xdc\xd0\x14\x7d\x44\xdc\x3e\xd9"
142 "\x09\x7e\x82\xca\x91\xbe\xd0\xdd\x9c\x8c\xb0\x77\x64\x30\x1b\x7e"
145 "\x02\xb9\xf0\xd0\xbb\xf7\xb7\x78\xf9\x3d\x76\x60\xd6\x6b\x5f\x35"
151 "\x30\x53" /* SEQUENCE, offset 0, length 83 */
164 "\x30\x77" /* SEQUENCE, offset 0, length 119 */
169 "\xa0\x0a" /* CONTEXT SPECIFIC 0, offset 39, length 10 */
[all …]
/openbmc/bmcweb/redfish-core/include/utils/
H A Dsystemd_utils.hpp27 sd_id128_t appId{{0Xe0, 0Xe1, 0X73, 0X76, 0X64, 0X61, 0X47, 0Xda, 0Xa5, in getUuid()
28 0X0c, 0Xd0, 0Xcc, 0X64, 0X12, 0X45, 0X78}}; in getUuid()
31 if (sd_id128_get_machine_app_specific(appId, &machineId) == 0) in getUuid()
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2_devcpu_gcb_miim_regs.h9 #define MIIM_MII_STATUS(gi) (0xc8 + (gi * 36))
10 #define MIIM_MII_CMD(gi) (0xd0 + (gi * 36))
11 #define MIIM_MII_DATA(gi) (0xd4 + (gi * 36))
13 #define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) ((x) ? BIT(3) : 0)
15 #define MSCC_F_MII_CMD_MIIM_CMD_VLD(x) ((x) ? BIT(31) : 0)
20 #define MSCC_F_MII_CMD_MIIM_CMD_SCAN(x) ((x) ? BIT(0) : 0)
23 #define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) (((x) >> 0) & GENMASK(15, 0))
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt_devcpu_gcb_miim_regs.h9 #define MIIM_MII_STATUS(gi) (0xc4 + (gi * 36))
10 #define MIIM_MII_CMD(gi) (0xcc + (gi * 36))
11 #define MIIM_MII_DATA(gi) (0xd0 + (gi * 36))
13 #define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) ((x) ? BIT(3) : 0)
15 #define MSCC_F_MII_CMD_MIIM_CMD_VLD(x) ((x) ? BIT(31) : 0)
20 #define MSCC_F_MII_CMD_MIIM_CMD_SCAN(x) ((x) ? BIT(0) : 0)
23 #define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) (((x) >> 0) & GENMASK(15, 0))
/openbmc/qemu/tests/bench/
H A Dtest_akcipher_keys.c.inc12 0x30, 0x82, 0x02, 0x5c, 0x02, 0x01, 0x00, 0x02,
13 0x81, 0x81, 0x00, 0xe6, 0x4d, 0x76, 0x4f, 0xb2,
14 0x97, 0x09, 0xad, 0x9d, 0x17, 0x33, 0xf2, 0x30,
15 0x42, 0x83, 0xa9, 0xcb, 0x49, 0xa4, 0x2e, 0x59,
16 0x5e, 0x75, 0x51, 0xd1, 0xac, 0xc8, 0x86, 0x3e,
17 0xdb, 0x72, 0x2e, 0xb2, 0xf7, 0xc3, 0x5b, 0xc7,
18 0xea, 0xed, 0x30, 0xd1, 0xf7, 0x37, 0xee, 0x9d,
19 0x36, 0x59, 0x6f, 0xf8, 0xce, 0xc0, 0x5c, 0x82,
20 0x80, 0x37, 0x83, 0xd7, 0x45, 0x6a, 0xe9, 0xea,
21 0xc5, 0x3a, 0x59, 0x6b, 0x34, 0x31, 0x44, 0x00,
[all …]
/openbmc/qemu/include/hw/adc/
H A Daspeed_adc.h28 #define ASPEED_ADC_NR_REGS (0xD0 >> 2)
/openbmc/pldm/fw-update/test/
H A Ddevice_updater_test.cpp23 {0x00}, in DeviceUpdaterTest()
26 std::vector<uint8_t>{0x16, 0x20, 0x23, 0xC9, 0x3E, 0xC5, 0x41, in DeviceUpdaterTest()
27 0x15, 0x95, 0xF4, 0x48, 0x70, 0x1D, 0x49, in DeviceUpdaterTest()
28 0xD6, 0x75}}}, in DeviceUpdaterTest()
31 {10, 100, 0xFFFFFFFF, 0, 0, 139, 1024, "VersionString3"}}; in DeviceUpdaterTest()
48 package.seekg(0); in TEST_F()
55 package.seekg(0); in TEST_F()
63 EXPECT_EQ(fwDeviceIDRecords[0], fwDeviceIDRecord); in TEST_F()
69 DeviceUpdater deviceUpdater(0, package, fwDeviceIDRecord, compImageInfos, in TEST_F()
74 reqFwDataReq{0x8A, 0x05, 0x15, 0x00, 0x00, 0x00, in TEST_F()
[all …]
/openbmc/u-boot/arch/x86/include/asm/
H A Dpch_common.h10 #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */
11 #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */
12 #define SATA_SP 0xd0 /* Scratchpad */
14 #define INTR_LN 0x3c
15 #define IDE_TIM_PRI 0x40 /* IDE timings, primary */
18 #define IDE_ISP_5_CLOCKS (0 << 12)
21 #define IDE_RCT_4_CLOCKS (0 << 8)
32 #define IDE_TIME0 (1 << 0)
33 #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
35 #define SERIRQ_CNTL 0x64
/openbmc/qemu/scripts/
H A Dextract-vsssdk-headers25 MAGIC=$'\xd0\xcf\x11\xe0\xa1\xb1\x1a\xe1'
35 exit 0
/openbmc/u-boot/arch/arm/include/asm/arch-tegra20/
H A Dgp_padctrl.h14 u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
15 u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
16 u32 reserved0[22]; /* 0x08 - 0x5C: */
17 u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
18 u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
19 u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
20 u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
21 u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
22 u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
23 u32 cdevcfg1; /* 0x78: APB_MISC_GP_CDEV1CFGPADCTRL */
[all …]
/openbmc/u-boot/arch/arm/mach-davinci/include/mach/
H A Dddr2_defs.h14 unsigned char rsvd0[4]; /* 0x00 */
15 unsigned int sdrstat; /* 0x04 */
16 unsigned int sdbcr; /* 0x08 */
17 unsigned int sdrcr; /* 0x0C */
18 unsigned int sdtimr; /* 0x10 */
19 unsigned int sdtimr2; /* 0x14 */
20 unsigned char rsvd1[4]; /* 0x18 */
21 unsigned int sdbcr2; /* 0x1C */
22 unsigned int pbbpr; /* 0x20 */
23 unsigned char rsvd2[156]; /* 0x24 */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-meson/
H A Dclock-axg.h18 #define HHI_GP0_PLL_CNTL 0x40
19 #define HHI_GP0_PLL_CNTL2 0x44
20 #define HHI_GP0_PLL_CNTL3 0x48
21 #define HHI_GP0_PLL_CNTL4 0x4c
22 #define HHI_GP0_PLL_CNTL5 0x50
23 #define HHI_GP0_PLL_STS 0x54
24 #define HHI_GP0_PLL_CNTL1 0x58
25 #define HHI_HIFI_PLL_CNTL 0x80
26 #define HHI_HIFI_PLL_CNTL2 0x84
27 #define HHI_HIFI_PLL_CNTL3 0x88
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra30/
H A Dgp_padctrl.h13 u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
14 u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
15 u32 reserved0[22]; /* 0x08 - 0x5C: */
16 u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
17 u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
18 u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
19 u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
20 u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
21 u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
22 u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
[all …]
/openbmc/ipmitool/include/ipmitool/
H A Dipmi_cc.h49 #define IPMI_CC_OK 0x00
50 #define IPMI_CC_NODE_BUSY 0xc0
51 #define IPMI_CC_INV_CMD 0xc1
52 #define IPMI_CC_INV_CMD_FOR_LUN 0xc2
53 #define IPMI_CC_TIMEOUT 0xc3
54 #define IPMI_CC_OUT_OF_SPACE 0xc4
55 #define IPMI_CC_RES_CANCELED 0xc5
56 #define IPMI_CC_REQ_DATA_TRUNC 0xc6
57 #define IPMI_CC_REQ_DATA_INV_LENGTH 0xc7
58 #define IPMI_CC_REQ_DATA_FIELD_EXCEED 0xc8
[all …]
/openbmc/u-boot/include/faraday/
H A Dftpmu010.h15 unsigned int IDNMBR0; /* 0x00 */
16 unsigned int reserved0; /* 0x04 */
17 unsigned int OSCC; /* 0x08 */
18 unsigned int PMODE; /* 0x0C */
19 unsigned int PMCR; /* 0x10 */
20 unsigned int PED; /* 0x14 */
21 unsigned int PEDSR; /* 0x18 */
22 unsigned int reserved1; /* 0x1C */
23 unsigned int PMSR; /* 0x20 */
24 unsigned int PGSR; /* 0x24 */
[all …]
/openbmc/qemu/hw/audio/
H A Dpl041.hx14 REGISTER( rxcr1, 0x00 )
15 REGISTER( txcr1, 0x04 )
16 REGISTER( sr1, 0x08 )
17 REGISTER( isr1, 0x0C )
18 REGISTER( ie1, 0x10 )
19 REGISTER( rxcr2, 0x14 )
20 REGISTER( txcr2, 0x18 )
21 REGISTER( sr2, 0x1C )
22 REGISTER( isr2, 0x20 )
23 REGISTER( ie2, 0x24 )
[all …]

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