1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 200a2749dSAllen Martin /* 300a2749dSAllen Martin * (C) Copyright 2010,2011 400a2749dSAllen Martin * NVIDIA Corporation <www.nvidia.com> 500a2749dSAllen Martin */ 600a2749dSAllen Martin 7dc89ad14STom Warren #ifndef _TEGRA20_GP_PADCTRL_H_ 8dc89ad14STom Warren #define _TEGRA20_GP_PADCTRL_H_ 9dc89ad14STom Warren 10dc89ad14STom Warren #include <asm/arch-tegra/gp_padctrl.h> 1100a2749dSAllen Martin 1200a2749dSAllen Martin /* APB_MISC_GP and padctrl registers */ 1300a2749dSAllen Martin struct apb_misc_gp_ctlr { 1400a2749dSAllen Martin u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ 1500a2749dSAllen Martin u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ 1600a2749dSAllen Martin u32 reserved0[22]; /* 0x08 - 0x5C: */ 1700a2749dSAllen Martin u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ 1800a2749dSAllen Martin u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ 1900a2749dSAllen Martin u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ 2000a2749dSAllen Martin u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */ 2100a2749dSAllen Martin u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ 2200a2749dSAllen Martin u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ 2300a2749dSAllen Martin u32 cdevcfg1; /* 0x78: APB_MISC_GP_CDEV1CFGPADCTRL */ 2400a2749dSAllen Martin u32 cdevcfg2; /* 0x7C: APB_MISC_GP_CDEV2CFGPADCTRL */ 2500a2749dSAllen Martin u32 csuscfg; /* 0x80: APB_MISC_GP_CSUSCFGPADCTRL */ 2600a2749dSAllen Martin u32 dap1cfg; /* 0x84: APB_MISC_GP_DAP1CFGPADCTRL */ 2700a2749dSAllen Martin u32 dap2cfg; /* 0x88: APB_MISC_GP_DAP2CFGPADCTRL */ 2800a2749dSAllen Martin u32 dap3cfg; /* 0x8C: APB_MISC_GP_DAP3CFGPADCTRL */ 2900a2749dSAllen Martin u32 dap4cfg; /* 0x90: APB_MISC_GP_DAP4CFGPADCTRL */ 3000a2749dSAllen Martin u32 dbgcfg; /* 0x94: APB_MISC_GP_DBGCFGPADCTRL */ 3100a2749dSAllen Martin u32 lcdcfg1; /* 0x98: APB_MISC_GP_LCDCFG1PADCTRL */ 3200a2749dSAllen Martin u32 lcdcfg2; /* 0x9C: APB_MISC_GP_LCDCFG2PADCTRL */ 3300a2749dSAllen Martin u32 sdmmc2_cfg; /* 0xA0: APB_MISC_GP_SDMMC2CFGPADCTRL */ 3400a2749dSAllen Martin u32 sdmmc3_cfg; /* 0xA4: APB_MISC_GP_SDMMC3CFGPADCTRL */ 3500a2749dSAllen Martin u32 spicfg; /* 0xA8: APB_MISC_GP_SPICFGPADCTRL */ 3600a2749dSAllen Martin u32 uaacfg; /* 0xAC: APB_MISC_GP_UAACFGPADCTRL */ 3700a2749dSAllen Martin u32 uabcfg; /* 0xB0: APB_MISC_GP_UABCFGPADCTRL */ 3800a2749dSAllen Martin u32 uart2cfg; /* 0xB4: APB_MISC_GP_UART2CFGPADCTRL */ 3900a2749dSAllen Martin u32 uart3cfg; /* 0xB8: APB_MISC_GP_UART3CFGPADCTRL */ 4000a2749dSAllen Martin u32 vicfg1; /* 0xBC: APB_MISC_GP_VICFG1PADCTRL */ 4100a2749dSAllen Martin u32 vicfg2; /* 0xC0: APB_MISC_GP_VICFG2PADCTRL */ 4200a2749dSAllen Martin u32 xm2cfga; /* 0xC4: APB_MISC_GP_XM2CFGAPADCTRL */ 4300a2749dSAllen Martin u32 xm2cfgc; /* 0xC8: APB_MISC_GP_XM2CFGCPADCTRL */ 4400a2749dSAllen Martin u32 xm2cfgd; /* 0xCC: APB_MISC_GP_XM2CFGDPADCTRL */ 4500a2749dSAllen Martin u32 xm2clkcfg; /* 0xD0: APB_MISC_GP_XM2CLKCFGPADCTRL */ 4600a2749dSAllen Martin u32 memcomp; /* 0xD4: APB_MISC_GP_MEMCOMPPADCTRL */ 4700a2749dSAllen Martin }; 4800a2749dSAllen Martin 49dc89ad14STom Warren #endif /* _TEGRA20_GP_PADCTRL_H_ */ 50