1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2fa36ae79SStefan Roese /* 3fa36ae79SStefan Roese * (C) Copyright 2009 4fa36ae79SStefan Roese * Stefan Roese, DENX Software Engineering, sr@denx.de. 5fa36ae79SStefan Roese */ 6fa36ae79SStefan Roese 7fa36ae79SStefan Roese #ifndef __CFI_FLASH_H__ 8fa36ae79SStefan Roese #define __CFI_FLASH_H__ 9fa36ae79SStefan Roese 10fa36ae79SStefan Roese #define FLASH_CMD_CFI 0x98 11fa36ae79SStefan Roese #define FLASH_CMD_READ_ID 0x90 12fa36ae79SStefan Roese #define FLASH_CMD_RESET 0xff 13fa36ae79SStefan Roese #define FLASH_CMD_BLOCK_ERASE 0x20 14fa36ae79SStefan Roese #define FLASH_CMD_ERASE_CONFIRM 0xD0 15fa36ae79SStefan Roese #define FLASH_CMD_WRITE 0x40 16fa36ae79SStefan Roese #define FLASH_CMD_PROTECT 0x60 176f726f95SStefan Roese #define FLASH_CMD_SETUP 0x60 186f726f95SStefan Roese #define FLASH_CMD_SET_CR_CONFIRM 0x03 19fa36ae79SStefan Roese #define FLASH_CMD_PROTECT_SET 0x01 20fa36ae79SStefan Roese #define FLASH_CMD_PROTECT_CLEAR 0xD0 21fa36ae79SStefan Roese #define FLASH_CMD_CLEAR_STATUS 0x50 22fa36ae79SStefan Roese #define FLASH_CMD_READ_STATUS 0x70 23fa36ae79SStefan Roese #define FLASH_CMD_WRITE_TO_BUFFER 0xE8 24fa36ae79SStefan Roese #define FLASH_CMD_WRITE_BUFFER_PROG 0xE9 25fa36ae79SStefan Roese #define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 26fa36ae79SStefan Roese 27fa36ae79SStefan Roese #define FLASH_STATUS_DONE 0x80 28fa36ae79SStefan Roese #define FLASH_STATUS_ESS 0x40 29fa36ae79SStefan Roese #define FLASH_STATUS_ECLBS 0x20 30fa36ae79SStefan Roese #define FLASH_STATUS_PSLBS 0x10 31fa36ae79SStefan Roese #define FLASH_STATUS_VPENS 0x08 32fa36ae79SStefan Roese #define FLASH_STATUS_PSS 0x04 33fa36ae79SStefan Roese #define FLASH_STATUS_DPS 0x02 34fa36ae79SStefan Roese #define FLASH_STATUS_R 0x01 35fa36ae79SStefan Roese #define FLASH_STATUS_PROTECT 0x01 36fa36ae79SStefan Roese 37fa36ae79SStefan Roese #define AMD_CMD_RESET 0xF0 38fa36ae79SStefan Roese #define AMD_CMD_WRITE 0xA0 39fa36ae79SStefan Roese #define AMD_CMD_ERASE_START 0x80 40fa36ae79SStefan Roese #define AMD_CMD_ERASE_SECTOR 0x30 41fa36ae79SStefan Roese #define AMD_CMD_UNLOCK_START 0xAA 42fa36ae79SStefan Roese #define AMD_CMD_UNLOCK_ACK 0x55 43fa36ae79SStefan Roese #define AMD_CMD_WRITE_TO_BUFFER 0x25 44fa36ae79SStefan Roese #define AMD_CMD_WRITE_BUFFER_CONFIRM 0x29 4566863b05SAnatolij Gustschin #define AMD_CMD_SET_PPB_ENTRY 0xC0 4666863b05SAnatolij Gustschin #define AMD_CMD_SET_PPB_EXIT_BC1 0x90 4766863b05SAnatolij Gustschin #define AMD_CMD_SET_PPB_EXIT_BC2 0x00 4866863b05SAnatolij Gustschin #define AMD_CMD_PPB_UNLOCK_BC1 0x80 4966863b05SAnatolij Gustschin #define AMD_CMD_PPB_UNLOCK_BC2 0x30 5066863b05SAnatolij Gustschin #define AMD_CMD_PPB_LOCK_BC1 0xA0 5166863b05SAnatolij Gustschin #define AMD_CMD_PPB_LOCK_BC2 0x00 52fa36ae79SStefan Roese 53fa36ae79SStefan Roese #define AMD_STATUS_TOGGLE 0x40 54fa36ae79SStefan Roese #define AMD_STATUS_ERROR 0x20 55fa36ae79SStefan Roese 56fa36ae79SStefan Roese #define ATM_CMD_UNLOCK_SECT 0x70 57fa36ae79SStefan Roese #define ATM_CMD_SOFTLOCK_START 0x80 58fa36ae79SStefan Roese #define ATM_CMD_LOCK_SECT 0x40 59fa36ae79SStefan Roese 60fa36ae79SStefan Roese #define FLASH_CONTINUATION_CODE 0x7F 61fa36ae79SStefan Roese 62fa36ae79SStefan Roese #define FLASH_OFFSET_MANUFACTURER_ID 0x00 63e303be2dSStefan Roese #define FLASH_OFFSET_DEVICE_ID 0x01 6472443c7fSMarek Vasut #define FLASH_OFFSET_LOWER_SW_BITS 0x0C 65e303be2dSStefan Roese #define FLASH_OFFSET_DEVICE_ID2 0x0E 66e303be2dSStefan Roese #define FLASH_OFFSET_DEVICE_ID3 0x0F 67e303be2dSStefan Roese #define FLASH_OFFSET_CFI 0x55 68fa36ae79SStefan Roese #define FLASH_OFFSET_CFI_ALT 0x555 69e303be2dSStefan Roese #define FLASH_OFFSET_CFI_RESP 0x10 70e303be2dSStefan Roese #define FLASH_OFFSET_PRIMARY_VENDOR 0x13 71fa36ae79SStefan Roese /* extended query table primary address */ 72e303be2dSStefan Roese #define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15 73fa36ae79SStefan Roese #define FLASH_OFFSET_WTOUT 0x1F 74e303be2dSStefan Roese #define FLASH_OFFSET_WBTOUT 0x20 75e303be2dSStefan Roese #define FLASH_OFFSET_ETOUT 0x21 76e303be2dSStefan Roese #define FLASH_OFFSET_CETOUT 0x22 77e303be2dSStefan Roese #define FLASH_OFFSET_WMAX_TOUT 0x23 78e303be2dSStefan Roese #define FLASH_OFFSET_WBMAX_TOUT 0x24 79e303be2dSStefan Roese #define FLASH_OFFSET_EMAX_TOUT 0x25 80e303be2dSStefan Roese #define FLASH_OFFSET_CEMAX_TOUT 0x26 81e303be2dSStefan Roese #define FLASH_OFFSET_SIZE 0x27 82e303be2dSStefan Roese #define FLASH_OFFSET_INTERFACE 0x28 83e303be2dSStefan Roese #define FLASH_OFFSET_BUFFER_SIZE 0x2A 84e303be2dSStefan Roese #define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C 85e303be2dSStefan Roese #define FLASH_OFFSET_ERASE_REGIONS 0x2D 86e303be2dSStefan Roese #define FLASH_OFFSET_PROTECT 0x02 87fa36ae79SStefan Roese #define FLASH_OFFSET_USER_PROTECTION 0x85 88fa36ae79SStefan Roese #define FLASH_OFFSET_INTEL_PROTECTION 0x81 89fa36ae79SStefan Roese 90fa36ae79SStefan Roese #define CFI_CMDSET_NONE 0 91fa36ae79SStefan Roese #define CFI_CMDSET_INTEL_EXTENDED 1 92fa36ae79SStefan Roese #define CFI_CMDSET_AMD_STANDARD 2 93fa36ae79SStefan Roese #define CFI_CMDSET_INTEL_STANDARD 3 94fa36ae79SStefan Roese #define CFI_CMDSET_AMD_EXTENDED 4 95fa36ae79SStefan Roese #define CFI_CMDSET_MITSU_STANDARD 256 96fa36ae79SStefan Roese #define CFI_CMDSET_MITSU_EXTENDED 257 97fa36ae79SStefan Roese #define CFI_CMDSET_SST 258 98fa36ae79SStefan Roese #define CFI_CMDSET_INTEL_PROG_REGIONS 512 99fa36ae79SStefan Roese 100fa36ae79SStefan Roese #ifdef CONFIG_SYS_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */ 101fa36ae79SStefan Roese # undef FLASH_CMD_RESET 102fa36ae79SStefan Roese # define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */ 103fa36ae79SStefan Roese #endif 104fa36ae79SStefan Roese 105fa36ae79SStefan Roese #define NUM_ERASE_REGIONS 4 /* max. number of erase regions */ 106fa36ae79SStefan Roese 107fa36ae79SStefan Roese typedef union { 108622b9527SRyan Harkin u8 w8; 109622b9527SRyan Harkin u16 w16; 110622b9527SRyan Harkin u32 w32; 111622b9527SRyan Harkin u64 w64; 112fa36ae79SStefan Roese } cfiword_t; 113fa36ae79SStefan Roese 114fa36ae79SStefan Roese /* CFI standard query structure */ 115aedadf10SAndrew Gabbasov /* The offsets and sizes of this packed structure members correspond 116aedadf10SAndrew Gabbasov * to the actual layout in CFI Flash chips. Some 16- and 32-bit members 117aedadf10SAndrew Gabbasov * are unaligned and must be accessed with explicit unaligned access macros. 118aedadf10SAndrew Gabbasov */ 119fa36ae79SStefan Roese struct cfi_qry { 120fa36ae79SStefan Roese u8 qry[3]; 121aedadf10SAndrew Gabbasov u16 p_id; /* unaligned */ 122aedadf10SAndrew Gabbasov u16 p_adr; /* unaligned */ 123aedadf10SAndrew Gabbasov u16 a_id; /* unaligned */ 124aedadf10SAndrew Gabbasov u16 a_adr; /* unaligned */ 125fa36ae79SStefan Roese u8 vcc_min; 126fa36ae79SStefan Roese u8 vcc_max; 127fa36ae79SStefan Roese u8 vpp_min; 128fa36ae79SStefan Roese u8 vpp_max; 129fa36ae79SStefan Roese u8 word_write_timeout_typ; 130fa36ae79SStefan Roese u8 buf_write_timeout_typ; 131fa36ae79SStefan Roese u8 block_erase_timeout_typ; 132fa36ae79SStefan Roese u8 chip_erase_timeout_typ; 133fa36ae79SStefan Roese u8 word_write_timeout_max; 134fa36ae79SStefan Roese u8 buf_write_timeout_max; 135fa36ae79SStefan Roese u8 block_erase_timeout_max; 136fa36ae79SStefan Roese u8 chip_erase_timeout_max; 137fa36ae79SStefan Roese u8 dev_size; 138aedadf10SAndrew Gabbasov u16 interface_desc; /* aligned */ 139aedadf10SAndrew Gabbasov u16 max_buf_write_size; /* aligned */ 140fa36ae79SStefan Roese u8 num_erase_regions; 141aedadf10SAndrew Gabbasov u32 erase_region_info[NUM_ERASE_REGIONS]; /* unaligned */ 142fa36ae79SStefan Roese } __attribute__((packed)); 143fa36ae79SStefan Roese 144fa36ae79SStefan Roese struct cfi_pri_hdr { 145fa36ae79SStefan Roese u8 pri[3]; 146fa36ae79SStefan Roese u8 major_version; 147fa36ae79SStefan Roese u8 minor_version; 148fa36ae79SStefan Roese } __attribute__((packed)); 149fa36ae79SStefan Roese 150ca5def3fSStefan Roese #ifndef CONFIG_SYS_FLASH_BANKS_LIST 151ca5def3fSStefan Roese #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 152ca5def3fSStefan Roese #endif 153ca5def3fSStefan Roese 154ca5def3fSStefan Roese /* 155ca5def3fSStefan Roese * CFI_MAX_FLASH_BANKS only used for flash_info struct declaration. 156ca5def3fSStefan Roese * 157ca5def3fSStefan Roese * Use CONFIG_SYS_MAX_FLASH_BANKS_DETECT if defined 158ca5def3fSStefan Roese */ 159ca5def3fSStefan Roese #if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT) 160ca5def3fSStefan Roese #define CONFIG_SYS_MAX_FLASH_BANKS (cfi_flash_num_flash_banks) 161ca5def3fSStefan Roese #define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS_DETECT 162ca5def3fSStefan Roese /* board code can update this variable before CFI detection */ 163ca5def3fSStefan Roese extern int cfi_flash_num_flash_banks; 164ca5def3fSStefan Roese #else 165ca5def3fSStefan Roese #define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS 166ca5def3fSStefan Roese #endif 167ca5def3fSStefan Roese 1686a19cc9dSMasahiro Yamada phys_addr_t cfi_flash_bank_addr(int i); 1696a19cc9dSMasahiro Yamada unsigned long cfi_flash_bank_size(int i); 1706a19cc9dSMasahiro Yamada void flash_cmd_reset(flash_info_t *info); 1716a19cc9dSMasahiro Yamada 1726a19cc9dSMasahiro Yamada #ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 1736a19cc9dSMasahiro Yamada void flash_write8(u8 value, void *addr); 1746a19cc9dSMasahiro Yamada void flash_write16(u16 value, void *addr); 1756a19cc9dSMasahiro Yamada void flash_write32(u32 value, void *addr); 1766a19cc9dSMasahiro Yamada void flash_write64(u64 value, void *addr); 1776a19cc9dSMasahiro Yamada u8 flash_read8(void *addr); 1786a19cc9dSMasahiro Yamada u16 flash_read16(void *addr); 1796a19cc9dSMasahiro Yamada u32 flash_read32(void *addr); 1806a19cc9dSMasahiro Yamada u64 flash_read64(void *addr); 1816a19cc9dSMasahiro Yamada #endif 182fa36ae79SStefan Roese 183fa36ae79SStefan Roese #endif /* __CFI_FLASH_H__ */ 184