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/openbmc/linux/arch/arm/mach-omap2/
H A Domap54xx.h17 #define L4_54XX_BASE 0x4a000000
18 #define L4_WK_54XX_BASE 0x4ae00000
19 #define L4_PER_54XX_BASE 0x48000000
20 #define L3_54XX_BASE 0x44000000
21 #define OMAP54XX_32KSYNCT_BASE 0x4ae04000
22 #define OMAP54XX_CM_CORE_AON_BASE 0x4a004000
23 #define OMAP54XX_CM_CORE_BASE 0x4a008000
24 #define OMAP54XX_PRM_BASE 0x4ae06000
25 #define OMAP54XX_PRCM_MPU_BASE 0x48243000
26 #define OMAP54XX_SCM_BASE 0x4a002000
[all …]
H A Diomap.h33 #define OMAP2_L3_IO_OFFSET 0x90000000
36 #define OMAP2_L4_IO_OFFSET 0xb2000000
39 #define OMAP4_L3_IO_OFFSET 0xb4000000
42 #define AM33XX_L4_WK_IO_OFFSET 0xb5000000
45 #define OMAP4_L3_PER_IO_OFFSET 0xb1100000
48 #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
58 #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
61 #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
65 #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
70 /* 0x6e000000 --> 0xfe000000 */
[all …]
H A Domap44xx.h17 #define L4_44XX_BASE 0x4a000000
18 #define L4_WK_44XX_BASE 0x4a300000
19 #define L4_PER_44XX_BASE 0x48000000
20 #define L4_EMU_44XX_BASE 0x54000000
21 #define L3_44XX_BASE 0x44000000
22 #define OMAP44XX_EMIF1_BASE 0x4c000000
23 #define OMAP44XX_EMIF2_BASE 0x4d000000
24 #define OMAP44XX_DMM_BASE 0x4e000000
25 #define OMAP4430_32KSYNCT_BASE 0x4a304000
26 #define OMAP4430_CM1_BASE 0x4a004000
[all …]
/openbmc/u-boot/include/configs/
H A Dqemu-arm.h13 #define CONFIG_SYS_SDRAM_BASE 0x40000000
24 #define CONFIG_ENV_ADDR 0x4000000
28 func(USB, usb, 0) \
29 func(SCSI, scsi, 0) \
30 func(VIRTIO, virtio, 0) \
37 "fdt_high=0xffffffff\0" \
38 "initrd_high=0xffffffff\0" \
39 "fdt_addr=0x40000000\0" \
40 "scriptaddr=0x40200000\0" \
41 "pxefile_addr_r=0x40300000\0" \
[all …]
H A Dspear3xx_evb.h33 #define CONFIG_MACB0_PHY 0x01
34 #define CONFIG_MACB1_PHY 0x03
35 #define CONFIG_MACB2_PHY 0x05
36 #define CONFIG_MACB3_PHY 0x07
40 #define CONFIG_MACB0_PHY 0x01
45 #define CONFIG_SYS_SERIAL0 0xD0000000
57 #define CONFIG_SYS_SERIAL1 0xB2000000
58 #define CONFIG_SYS_SERIAL2 0xB2080000
59 #define CONFIG_SYS_SERIAL3 0xB2100000
60 #define CONFIG_SYS_SERIAL4 0xB2180000
[all …]
H A Dsunxi-common.h24 # define CONFIG_MACH_TYPE_COMPAT_REV 0
62 #define SDRAM_OFFSET(x) 0x2##x
63 #define CONFIG_SYS_SDRAM_BASE 0x20000000
64 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* default load address */
68 #define CONFIG_SPL_STACK_R_ADDR 0x2fe00000
69 #define CONFIG_SPL_BSS_START_ADDR 0x2ff80000
71 #define SDRAM_OFFSET(x) 0x4##x
72 #define CONFIG_SYS_SDRAM_BASE 0x40000000
73 #define CONFIG_SYS_LOAD_ADDR 0x42000000 /* default load address */
74 /* V3s do not have enough memory to place code at 0x4a000000 */
[all …]
H A Dvexpress_common.h20 #define V2M_PA_CS0 0x40000000
21 #define V2M_PA_CS1 0x44000000
22 #define V2M_PA_CS2 0x48000000
23 #define V2M_PA_CS3 0x4c000000
24 #define V2M_PA_CS7 0x10000000
27 #define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(0))
31 #define V2M_BASE 0x60000000
34 #define V2M_PA_CS0 0x08000000
35 #define V2M_PA_CS1 0x0c000000
36 #define V2M_PA_CS2 0x14000000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/
H A Dmarvell,pxa2xx-lcdc.txt26 reg = <0x44000000 0x10000>;
/openbmc/u-boot/arch/arm/include/asm/arch-spear/
H A Dhardware.h10 #define CONFIG_SYS_USBD_BASE 0xE1100000
11 #define CONFIG_SYS_PLUG_BASE 0xE1200000
12 #define CONFIG_SYS_FIFO_BASE 0xE1000800
13 #define CONFIG_SYS_UHC0_EHCI_BASE 0xE1800000
14 #define CONFIG_SYS_UHC1_EHCI_BASE 0xE2000000
15 #define CONFIG_SYS_SMI_BASE 0xFC000000
16 #define CONFIG_SPEAR_SYSCNTLBASE 0xFCA00000
17 #define CONFIG_SPEAR_TIMERBASE 0xFC800000
18 #define CONFIG_SPEAR_MISCBASE 0xFCA80000
19 #define CONFIG_SPEAR_ETHBASE 0xE0800000
[all …]
/openbmc/linux/arch/arm/mach-pxa/
H A Dpxa-regs.h14 #define UNCACHED_PHYS_0 0xfe000000
15 #define UNCACHED_PHYS_0_SIZE 0x00100000
20 * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
21 * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
22 * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
23 * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
24 * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
25 * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
26 * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
31 #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/ls102xa/
H A Dfsl_epu.c13 {EPGCR, 0},
15 {EPECR0 + EPECR_STRIDE * 0, 0},
16 {EPECR0 + EPECR_STRIDE * 1, 0},
17 {EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
18 {EPECR0 + EPECR_STRIDE * 3, 0x80000084},
19 {EPECR0 + EPECR_STRIDE * 4, 0x20000084},
20 {EPECR0 + EPECR_STRIDE * 5, 0x08000004},
21 {EPECR0 + EPECR_STRIDE * 6, 0x80000084},
22 {EPECR0 + EPECR_STRIDE * 7, 0x80000084},
23 {EPECR0 + EPECR_STRIDE * 8, 0x60000084},
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-pxa/
H A Dhardware.h42 #define PCMCIA_IO_0_BASE 0xf6000000
43 #define PCMCIA_IO_1_BASE 0xf7000000
49 #define PCIO_BASE 0
55 #define UNCACHED_PHYS_0 0xff000000
61 * 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff
62 * 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff
63 * 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff
/openbmc/linux/arch/arm/boot/dts/st/
H A Dspear310.dtsi15 ranges = <0x40000000 0x40000000 0x10000000
16 0xb0000000 0xb0000000 0x10000000
17 0xd0000000 0xd0000000 0x30000000>;
21 reg = <0xb4000000 0x1000>;
29 reg = <0x44000000 0x1000 /* FSMC Register */
30 0x40000000 0x0010 /* NAND Base DATA */
31 0x40020000 0x0010 /* NAND Base ADDR */
32 0x40010000 0x0010>; /* NAND Base CMD */
39 reg = <0xb4000000 0x1000>;
49 ranges = <0xb0000000 0xb0000000 0x10000000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dsocionext,uniphier-system-bus.yaml45 implementation defined. Some SoCs can use 0x00000000-0x0fffffff and
46 0x40000000-0x4fffffff, while other SoCs only 0x40000000-0x4fffffff.
53 bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff
55 bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff
61 "^.*@[1-5],[1-9a-f][0-9a-f]+$":
77 // - the Ethernet device is connected at the offset 0x01f00000 of CS1 and
78 // mapped to 0x43f00000 of the parent bus.
79 // - the UART device is connected at the offset 0x00200000 of CS5 and
80 // mapped to 0x46200000 of the parent bus.
84 reg = <0x58c00000 0x400>;
[all …]
/openbmc/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa2xx.dtsi64 reg = <0x40d00000 0xd0>;
69 #address-cells = <0x1>;
70 #size-cells = <0x1>;
71 reg = <0x40e00000 0x10000>;
73 #gpio-cells = <0x2>;
77 #interrupt-cells = <0x2>;
81 reg = <0x40e00000 0x4>;
85 reg = <0x40e00004 0x4>;
89 reg = <0x40e00008 0x4>;
92 reg = <0x40e0000c 0x4>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dfsl,edma.yaml162 reg = <0x40018000 0x2000>,
163 <0x40024000 0x1000>,
164 <0x40025000 0x1000>;
165 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
166 <0 9 IRQ_TYPE_LEVEL_HIGH>;
180 reg = <0x40080000 0x2000>,
181 <0x40210000 0x1000>;
183 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
211 reg = <0x44000000 0x200000>;
/openbmc/qemu/hw/arm/
H A Dvexpress.c50 #define VEXPRESS_BOARD_ID 0x8e0
54 /* Number of virtio transports to create (0..8; limited by
98 [VE_NORFLASHALIAS] = 0,
99 /* CS7: 0x10000000 .. 0x10020000 */
100 [VE_SYSREGS] = 0x10000000,
101 [VE_SP810] = 0x10001000,
102 [VE_SERIALPCI] = 0x10002000,
103 [VE_PL041] = 0x10004000,
104 [VE_MMCI] = 0x10005000,
105 [VE_KMI0] = 0x10006000,
[all …]
H A Dversatilepb.c31 #define VERSATILE_FLASH_ADDR 0x34000000
68 qemu_set_irq(s->parent[s->irq], flags != 0); in vpb_sic_update()
80 qemu_set_irq(s->parent[i], (s->level & mask) != 0); in vpb_sic_update_pic()
102 case 0: /* STATUS */ in vpb_sic_read()
113 printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset); in vpb_sic_read()
114 return 0; in vpb_sic_read()
139 s->pic_enable |= (value & 0x7fe00000); in vpb_sic_write()
147 printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset); in vpb_sic_write()
167 for (i = 0; i < 32; i++) { in vpb_sic_init()
172 "vpb-sic", 0x1000); in vpb_sic_init()
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/pxaregs/pxaregs-1.14/
H A Dpxaregs.c44 { "IBMR", 0x40301680, 0, 0xffffffff, 'x', "I2C Bus Monitor Register" },
45 { "IBMR_SDAS", 0x40301680, 0, 0x00000001, 'x', "SDA Status" },
46 { "IBMR_SCLS", 0x40301680, 1, 0x00000001, 'x', "SDA Status" },
48 { "IDBR", 0x40301688, 0, 0xffffffff, 'x', "I2C Data Buffer Register" },
49 { "IDBR_IDB", 0x40301688, 0, 0x000000ff, 'x', "I2C Data Buffer" },
51 { "ICR", 0x40301690, 0, 0xffffffff, 'x', "I2C Control Register" },
52 { "ICR_START", 0x40301690, 0, 1, 'x', " start bit " },
53 { "ICR_STOP", 0x40301690, 1, 1, 'x', " stop bit " },
54 { "ICR_ACKNAK",0x40301690, 2, 1, 'x', " send ACK(0) or NAK(1)" },
55 { "ICR_TB", 0x40301690, 3, 1, 'x', " transfer byte bit " },
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dimu_v11_0_3.c31 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_IO_RD_COMBINE_FLUSH, 0x00055555, 0xe0000000),
32 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_IO_WR_COMBINE_FLUSH, 0x00055555, 0xe0000000),
33 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_DRAM_COMBINE_FLUSH, 0x00555555, 0xe0000000),
34 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_MISC2, 0x00001ffe, 0xe0000000),
35 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_CREDITS, 0x003f3fff, 0xe0000000),
36 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_TAG_RESERVE1, 0x00000000, 0xe0000000),
37 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCC_RESERVE0, 0x00041000, 0xe0000000),
38 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCC_RESERVE1, 0x00000000, 0xe0000000),
39 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCD_RESERVE0, 0x00040000, 0xe0000000),
40 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCD_RESERVE1, 0x00000000, 0xe0000000),
[all …]
/openbmc/linux/drivers/gpu/drm/ast/
H A Dast_dp501.c34 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff); in send_ack()
35 sendack |= 0x80; in send_ack()
36 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack); in send_ack()
42 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff); in send_nack()
43 sendack &= ~0x80; in send_nack()
44 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack); in send_nack()
50 u32 retry = 0; in wait_ack()
52 waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff); in wait_ack()
53 waitack &= 0x80; in wait_ack()
66 u32 retry = 0; in wait_nack()
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Darm-realview-eb.dtsi43 /* 128 MiB memory @ 0x0 */
44 reg = <0x00000000 0x08000000>;
48 vmmc: fixedregulator@0 {
57 #clock-cells = <0>;
63 #clock-cells = <0>;
71 #clock-cells = <0>;
79 #clock-cells = <0>;
87 #clock-cells = <0>;
95 #clock-cells = <0>;
103 #clock-cells = <0>;
[all …]
H A Dvexpress-v2m.dtsi27 ranges = <0x40000000 0x40000000 0x10000000>,
28 <0x10000000 0x10000000 0x00020000>;
31 interrupt-map-mask = <0 63>;
32 interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
33 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
34 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
35 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
36 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
37 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
38 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/openbmc/u-boot/arch/arm/mach-davinci/include/mach/
H A Dhardware.h35 #define DAVINCI_DMA_3PCC_BASE (0x01c00000)
36 #define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
37 #define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
38 #define DAVINCI_UART0_BASE (0x01c20000)
39 #define DAVINCI_UART1_BASE (0x01c20400)
40 #define DAVINCI_TIMER3_BASE (0x01c20800)
41 #define DAVINCI_I2C_BASE (0x01c21000)
42 #define DAVINCI_TIMER0_BASE (0x01c21400)
43 #define DAVINCI_TIMER1_BASE (0x01c21800)
44 #define DAVINCI_WDOG_BASE (0x01c21c00)
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Ddm816x.dtsi29 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
63 reg = <0x44000000 0x10000>;
71 reg = <0x48180000 0x4000>;
75 #size-cells = <0>;
84 reg = <0x48140000 0x21000>;
88 ranges = <0 0x48140000 0x21000>;
92 reg = <0x800 0x50a>;
95 pinctrl-single,function-mask = <0xf>;
[all …]

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