1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2c49f34bcSTony Lindgren /*: 3c49f34bcSTony Lindgren * Address mappings and base address for OMAP5 interconnects 4c49f34bcSTony Lindgren * and peripherals. 5c49f34bcSTony Lindgren * 6c49f34bcSTony Lindgren * Copyright (C) 2012 Texas Instruments 7c49f34bcSTony Lindgren * Santosh Shilimkar <santosh.shilimkar@ti.com> 8c49f34bcSTony Lindgren * Sricharan <r.sricharan@ti.com> 9c49f34bcSTony Lindgren */ 10c49f34bcSTony Lindgren #ifndef __ASM_SOC_OMAP54XX_H 11c49f34bcSTony Lindgren #define __ASM_SOC_OMAP54XX_H 12c49f34bcSTony Lindgren 13c49f34bcSTony Lindgren /* 14c49f34bcSTony Lindgren * Please place only base defines here and put the rest in device 15c49f34bcSTony Lindgren * specific headers. 16c49f34bcSTony Lindgren */ 17c49f34bcSTony Lindgren #define L4_54XX_BASE 0x4a000000 18c49f34bcSTony Lindgren #define L4_WK_54XX_BASE 0x4ae00000 19c49f34bcSTony Lindgren #define L4_PER_54XX_BASE 0x48000000 20c49f34bcSTony Lindgren #define L3_54XX_BASE 0x44000000 21c49f34bcSTony Lindgren #define OMAP54XX_32KSYNCT_BASE 0x4ae04000 22c49f34bcSTony Lindgren #define OMAP54XX_CM_CORE_AON_BASE 0x4a004000 23c49f34bcSTony Lindgren #define OMAP54XX_CM_CORE_BASE 0x4a008000 24c49f34bcSTony Lindgren #define OMAP54XX_PRM_BASE 0x4ae06000 25c49f34bcSTony Lindgren #define OMAP54XX_PRCM_MPU_BASE 0x48243000 26c49f34bcSTony Lindgren #define OMAP54XX_SCM_BASE 0x4a002000 27c49f34bcSTony Lindgren #define OMAP54XX_CTRL_BASE 0x4a002800 28da0e02a1SSantosh Shilimkar #define OMAP54XX_SAR_RAM_BASE 0x4ae26000 29c49f34bcSTony Lindgren 30ea827ad5SNishanth Menon /* DRA7 specific base addresses */ 31ea827ad5SNishanth Menon #define L3_MAIN_SN_DRA7XX_BASE 0x44000000 32ea827ad5SNishanth Menon #define L4_PER1_DRA7XX_BASE 0x48000000 33ea827ad5SNishanth Menon #define L4_CFG_MPU_DRA7XX_BASE 0x48210000 34ea827ad5SNishanth Menon #define L4_PER2_DRA7XX_BASE 0x48400000 35ea827ad5SNishanth Menon #define L4_PER3_DRA7XX_BASE 0x48800000 36ea827ad5SNishanth Menon #define L4_CFG_DRA7XX_BASE 0x4A000000 37ea827ad5SNishanth Menon #define L4_WKUP_DRA7XX_BASE 0x4ae00000 38a3a9384aSR Sricharan #define DRA7XX_CM_CORE_AON_BASE 0x4a005000 39a3a9384aSR Sricharan #define DRA7XX_CTRL_BASE 0x4a003400 40a3a9384aSR Sricharan #define DRA7XX_TAP_BASE 0x4ae0c000 41a3a9384aSR Sricharan 42c49f34bcSTony Lindgren #endif /* __ASM_SOC_OMAP555554XX_H */ 43