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/openbmc/linux/Documentation/devicetree/bindings/mailbox/
H A Dqcom-ipcc.yaml20 protocol (protocol-id is 0). Refer include/dt-bindings/mailbox/qcom-ipcc.h
75 reg = <0x408000 0x1000>;
/openbmc/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Ddma_qm_1_regs.h22 #define mmDMA_QM_1_GLBL_CFG0 0x408000
24 #define mmDMA_QM_1_GLBL_CFG1 0x408004
26 #define mmDMA_QM_1_GLBL_PROT 0x408008
28 #define mmDMA_QM_1_GLBL_ERR_CFG 0x40800C
30 #define mmDMA_QM_1_GLBL_ERR_ADDR_LO 0x408010
32 #define mmDMA_QM_1_GLBL_ERR_ADDR_HI 0x408014
34 #define mmDMA_QM_1_GLBL_ERR_WDATA 0x408018
36 #define mmDMA_QM_1_GLBL_SECURE_PROPS 0x40801C
38 #define mmDMA_QM_1_GLBL_NON_SECURE_PROPS 0x408020
40 #define mmDMA_QM_1_GLBL_STS0 0x408024
[all …]
/openbmc/linux/arch/mips/boot/dts/brcm/
H A Dbcm7362.dtsi9 #size-cells = <0>;
13 cpu@0 {
16 reg = <0>;
31 #address-cells = <0>;
41 #clock-cells = <0>;
47 #clock-cells = <0>;
57 ranges = <0 0x10000000 0x01000000>;
61 reg = <0x411400 0x30>, <0x411600 0x30>;
72 reg = <0x403000 0x30>;
81 reg = <0x400000 0xdc>;
[all …]
H A Dbcm7360.dtsi9 #size-cells = <0>;
13 cpu@0 {
16 reg = <0>;
25 #address-cells = <0>;
35 #clock-cells = <0>;
41 #clock-cells = <0>;
51 ranges = <0 0x10000000 0x01000000>;
55 reg = <0x411400 0x30>;
66 reg = <0x403000 0x30>;
75 reg = <0x400000 0xdc>;
[all …]
H A Dbcm7346.dtsi9 #size-cells = <0>;
13 cpu@0 {
16 reg = <0>;
31 #address-cells = <0>;
41 #clock-cells = <0>;
47 #clock-cells = <0>;
57 ranges = <0 0x10000000 0x01000000>;
61 reg = <0x411400 0x30>, <0x411600 0x30>;
72 reg = <0x403000 0x30>;
81 reg = <0x400000 0xdc>;
[all …]
H A Dbcm7435.dtsi9 #size-cells = <0>;
13 cpu@0 {
16 reg = <0>;
43 #address-cells = <0>;
53 #clock-cells = <0>;
59 #clock-cells = <0>;
69 ranges = <0 0x10000000 0x01000000>;
73 reg = <0x41b500 0x40>, <0x41b600 0x40>,
74 <0x41b700 0x40>, <0x41b800 0x40>;
85 reg = <0x403000 0x30>;
[all …]
H A Dbcm7425.dtsi9 #size-cells = <0>;
13 cpu@0 {
16 reg = <0>;
31 #address-cells = <0>;
41 #clock-cells = <0>;
47 #clock-cells = <0>;
57 ranges = <0 0x10000000 0x01000000>;
61 reg = <0x41a400 0x30>, <0x41a600 0x30>;
72 reg = <0x403000 0x30>;
81 reg = <0x400000 0xdc>;
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dctxnv40.c31 * - On context save, NVIDIA set 0x400314 bit 0 to 1 if the "3D state"
35 * opcode 0x60000d is called before resuming normal operation.
37 * checks: ((nsource & 0x0857) || (0x400718 & 0x0100) || (intr & 0x0001))
38 * and calls 0x60000d before resuming normal operation.
40 * and if true 0x800001 is called with count=0, pos=0, the flag is cleared
44 * flag 10. If it's set, they only transfer the small 0x300 byte block
50 * - There's a number of places where context offset 0 (where we place
51 * the PRAMIN offset of the context) is loaded into either 0x408000,
52 * 0x408004 or 0x408008. Not sure what's up there either.
53 * - The ctxprogs for some cards save 0x400a00 again during the cleanup
[all …]
H A Dctxgk104.c35 { 0x001000, 1, 0x01, 0x00000004 },
36 { 0x000039, 3, 0x01, 0x00000000 },
37 { 0x0000a9, 1, 0x01, 0x0000ffff },
38 { 0x000038, 1, 0x01, 0x0fac6881 },
39 { 0x00003d, 1, 0x01, 0x00000001 },
40 { 0x0000e8, 8, 0x01, 0x00000400 },
41 { 0x000078, 8, 0x01, 0x00000300 },
42 { 0x000050, 1, 0x01, 0x00000011 },
43 { 0x000058, 8, 0x01, 0x00000008 },
44 { 0x000208, 8, 0x01, 0x00000001 },
[all …]
H A Dctxgf100.c37 { 0x001000, 1, 0x01, 0x00000004 },
38 { 0x0000a9, 1, 0x01, 0x0000ffff },
39 { 0x000038, 1, 0x01, 0x0fac6881 },
40 { 0x00003d, 1, 0x01, 0x00000001 },
41 { 0x0000e8, 8, 0x01, 0x00000400 },
42 { 0x000078, 8, 0x01, 0x00000300 },
43 { 0x000050, 1, 0x01, 0x00000011 },
44 { 0x000058, 8, 0x01, 0x00000008 },
45 { 0x000208, 8, 0x01, 0x00000001 },
46 { 0x000081, 1, 0x01, 0x00000001 },
[all …]
H A Dctxnv50.c23 #define CP_FLAG_CLEAR 0
25 #define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0)
26 #define CP_FLAG_SWAP_DIRECTION_LOAD 0
28 #define CP_FLAG_UNK01 ((0 * 32) + 1)
29 #define CP_FLAG_UNK01_CLEAR 0
31 #define CP_FLAG_UNK03 ((0 * 32) + 3)
32 #define CP_FLAG_UNK03_CLEAR 0
34 #define CP_FLAG_USER_SAVE ((0 * 32) + 5)
35 #define CP_FLAG_USER_SAVE_NOT_PENDING 0
37 #define CP_FLAG_USER_LOAD ((0 * 32) + 6)
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7915/
H A Dmmio.c21 [INT_SOURCE_CSR] = 0xd7010,
22 [INT_MASK_CSR] = 0xd7014,
23 [INT1_SOURCE_CSR] = 0xd7088,
24 [INT1_MASK_CSR] = 0xd708c,
25 [INT_MCU_CMD_SOURCE] = 0xd51f0,
26 [INT_MCU_CMD_EVENT] = 0x3108,
27 [WFDMA0_ADDR] = 0xd4000,
28 [WFDMA0_PCIE1_ADDR] = 0xd8000,
29 [WFDMA_EXT_CSR_ADDR] = 0xd7000,
30 [CBTOP1_PHY_END] = 0x77ffffff,
[all …]
/openbmc/linux/drivers/phy/microchip/
H A Dsparx5_serdes.c31 #define SPX5_SERDES_QUIET_MODE_VAL 0x01ef4e0c
34 SPX5_SD10G28_CMU_MAIN = 0,
353 .cfg_en_adv = 0,
355 .cfg_en_dly = 0,
356 .cfg_tap_adv_3_0 = 0,
358 .cfg_tap_dly_4_0 = 0,
359 .cfg_eq_c_force_3_0 = 0xf,
368 .cfg_tap_adv_3_0 = 0,
370 .cfg_tap_dly_4_0 = 0x10,
371 .cfg_eq_c_force_3_0 = 0xf,
[all …]
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dxtensa-modules.c.inc32 { "MMID", 89, 0 },
33 { "DDR", 104, 0 },
34 { "CONFIGID0", 176, 0 },
35 { "CONFIGID1", 208, 0 },
36 { "INTERRUPT", 226, 0 },
37 { "INTCLEAR", 227, 0 },
38 { "CCOUNT", 234, 0 },
39 { "PRID", 235, 0 },
40 { "ICOUNT", 236, 0 },
41 { "CCOMPARE0", 240, 0 },
[all …]
/openbmc/qemu/target/xtensa/core-dc233c/
H A Dxtensa-modules.c.inc3 Customer ID=4869; Build=0x2cfec; Copyright (c) 2003-2010 Tensilica Inc.
32 { "LBEG", 0, 0 },
33 { "LEND", 1, 0 },
34 { "LCOUNT", 2, 0 },
35 { "ACCLO", 16, 0 },
36 { "ACCHI", 17, 0 },
37 { "M0", 32, 0 },
38 { "M1", 33, 0 },
39 { "M2", 34, 0 },
40 { "M3", 35, 0 },
[all …]
/openbmc/qemu/target/xtensa/core-de212/
H A Dxtensa-modules.c.inc32 { "LBEG", 0, 0 },
33 { "LEND", 1, 0 },
34 { "LCOUNT", 2, 0 },
35 { "ACCLO", 16, 0 },
36 { "ACCHI", 17, 0 },
37 { "M0", 32, 0 },
38 { "M1", 33, 0 },
39 { "M2", 34, 0 },
40 { "M3", 35, 0 },
41 { "MMID", 89, 0 },
[all …]
/openbmc/qemu/target/xtensa/core-dc232b/
H A Dxtensa-modules.c.inc29 { "LBEG", 0, 0 },
30 { "LEND", 1, 0 },
31 { "LCOUNT", 2, 0 },
32 { "ACCLO", 16, 0 },
33 { "ACCHI", 17, 0 },
34 { "M0", 32, 0 },
35 { "M1", 33, 0 },
36 { "M2", 34, 0 },
37 { "M3", 35, 0 },
38 { "PTEVADDR", 83, 0 },
[all …]
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dxtensa-modules.c.inc31 { "LBEG", 0, 0 },
32 { "LEND", 1, 0 },
33 { "LCOUNT", 2, 0 },
34 { "BR", 4, 0 },
35 { "ACCLO", 16, 0 },
36 { "ACCHI", 17, 0 },
37 { "M0", 32, 0 },
38 { "M1", 33, 0 },
39 { "M2", 34, 0 },
40 { "M3", 35, 0 },
[all …]
/openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dxtensa-modules.c.inc31 { "LBEG", 0, 0 },
32 { "LEND", 1, 0 },
33 { "LCOUNT", 2, 0 },
34 { "BR", 4, 0 },
35 { "PTEVADDR", 83, 0 },
36 { "DDR", 104, 0 },
37 { "CONFIGID0", 176, 0 },
38 { "CONFIGID1", 208, 0 },
39 { "INTERRUPT", 226, 0 },
40 { "INTCLEAR", 227, 0 },
[all …]
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dxtensa-modules.c.inc31 { "LBEG", 0, 0 },
32 { "LEND", 1, 0 },
33 { "LCOUNT", 2, 0 },
34 { "BR", 4, 0 },
35 { "MMID", 89, 0 },
36 { "DDR", 104, 0 },
37 { "176", 176, 0 },
38 { "208", 208, 0 },
39 { "INTERRUPT", 226, 0 },
40 { "INTCLEAR", 227, 0 },
[all …]