1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2018 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_DMA_QM_1_REGS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_DMA_QM_1_REGS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * DMA_QM_1 (Prototype: QMAN) 19*e65e175bSOded Gabbay ***************************************** 20*e65e175bSOded Gabbay */ 21*e65e175bSOded Gabbay 22*e65e175bSOded Gabbay #define mmDMA_QM_1_GLBL_CFG0 0x408000 23*e65e175bSOded Gabbay 24*e65e175bSOded Gabbay #define mmDMA_QM_1_GLBL_CFG1 0x408004 25*e65e175bSOded Gabbay 26*e65e175bSOded Gabbay #define mmDMA_QM_1_GLBL_PROT 0x408008 27*e65e175bSOded Gabbay 28*e65e175bSOded Gabbay #define mmDMA_QM_1_GLBL_ERR_CFG 0x40800C 29*e65e175bSOded Gabbay 30*e65e175bSOded Gabbay #define mmDMA_QM_1_GLBL_ERR_ADDR_LO 0x408010 31*e65e175bSOded Gabbay 32*e65e175bSOded Gabbay #define mmDMA_QM_1_GLBL_ERR_ADDR_HI 0x408014 33*e65e175bSOded Gabbay 34*e65e175bSOded Gabbay #define mmDMA_QM_1_GLBL_ERR_WDATA 0x408018 35*e65e175bSOded Gabbay 36*e65e175bSOded Gabbay #define mmDMA_QM_1_GLBL_SECURE_PROPS 0x40801C 37*e65e175bSOded Gabbay 38*e65e175bSOded Gabbay #define mmDMA_QM_1_GLBL_NON_SECURE_PROPS 0x408020 39*e65e175bSOded Gabbay 40*e65e175bSOded Gabbay #define mmDMA_QM_1_GLBL_STS0 0x408024 41*e65e175bSOded Gabbay 42*e65e175bSOded Gabbay #define mmDMA_QM_1_GLBL_STS1 0x408028 43*e65e175bSOded Gabbay 44*e65e175bSOded Gabbay #define mmDMA_QM_1_PQ_BASE_LO 0x408060 45*e65e175bSOded Gabbay 46*e65e175bSOded Gabbay #define mmDMA_QM_1_PQ_BASE_HI 0x408064 47*e65e175bSOded Gabbay 48*e65e175bSOded Gabbay #define mmDMA_QM_1_PQ_SIZE 0x408068 49*e65e175bSOded Gabbay 50*e65e175bSOded Gabbay #define mmDMA_QM_1_PQ_PI 0x40806C 51*e65e175bSOded Gabbay 52*e65e175bSOded Gabbay #define mmDMA_QM_1_PQ_CI 0x408070 53*e65e175bSOded Gabbay 54*e65e175bSOded Gabbay #define mmDMA_QM_1_PQ_CFG0 0x408074 55*e65e175bSOded Gabbay 56*e65e175bSOded Gabbay #define mmDMA_QM_1_PQ_CFG1 0x408078 57*e65e175bSOded Gabbay 58*e65e175bSOded Gabbay #define mmDMA_QM_1_PQ_ARUSER 0x40807C 59*e65e175bSOded Gabbay 60*e65e175bSOded Gabbay #define mmDMA_QM_1_PQ_PUSH0 0x408080 61*e65e175bSOded Gabbay 62*e65e175bSOded Gabbay #define mmDMA_QM_1_PQ_PUSH1 0x408084 63*e65e175bSOded Gabbay 64*e65e175bSOded Gabbay #define mmDMA_QM_1_PQ_PUSH2 0x408088 65*e65e175bSOded Gabbay 66*e65e175bSOded Gabbay #define mmDMA_QM_1_PQ_PUSH3 0x40808C 67*e65e175bSOded Gabbay 68*e65e175bSOded Gabbay #define mmDMA_QM_1_PQ_STS0 0x408090 69*e65e175bSOded Gabbay 70*e65e175bSOded Gabbay #define mmDMA_QM_1_PQ_STS1 0x408094 71*e65e175bSOded Gabbay 72*e65e175bSOded Gabbay #define mmDMA_QM_1_PQ_RD_RATE_LIM_EN 0x4080A0 73*e65e175bSOded Gabbay 74*e65e175bSOded Gabbay #define mmDMA_QM_1_PQ_RD_RATE_LIM_RST_TOKEN 0x4080A4 75*e65e175bSOded Gabbay 76*e65e175bSOded Gabbay #define mmDMA_QM_1_PQ_RD_RATE_LIM_SAT 0x4080A8 77*e65e175bSOded Gabbay 78*e65e175bSOded Gabbay #define mmDMA_QM_1_PQ_RD_RATE_LIM_TOUT 0x4080AC 79*e65e175bSOded Gabbay 80*e65e175bSOded Gabbay #define mmDMA_QM_1_CQ_CFG0 0x4080B0 81*e65e175bSOded Gabbay 82*e65e175bSOded Gabbay #define mmDMA_QM_1_CQ_CFG1 0x4080B4 83*e65e175bSOded Gabbay 84*e65e175bSOded Gabbay #define mmDMA_QM_1_CQ_ARUSER 0x4080B8 85*e65e175bSOded Gabbay 86*e65e175bSOded Gabbay #define mmDMA_QM_1_CQ_PTR_LO 0x4080C0 87*e65e175bSOded Gabbay 88*e65e175bSOded Gabbay #define mmDMA_QM_1_CQ_PTR_HI 0x4080C4 89*e65e175bSOded Gabbay 90*e65e175bSOded Gabbay #define mmDMA_QM_1_CQ_TSIZE 0x4080C8 91*e65e175bSOded Gabbay 92*e65e175bSOded Gabbay #define mmDMA_QM_1_CQ_CTL 0x4080CC 93*e65e175bSOded Gabbay 94*e65e175bSOded Gabbay #define mmDMA_QM_1_CQ_PTR_LO_STS 0x4080D4 95*e65e175bSOded Gabbay 96*e65e175bSOded Gabbay #define mmDMA_QM_1_CQ_PTR_HI_STS 0x4080D8 97*e65e175bSOded Gabbay 98*e65e175bSOded Gabbay #define mmDMA_QM_1_CQ_TSIZE_STS 0x4080DC 99*e65e175bSOded Gabbay 100*e65e175bSOded Gabbay #define mmDMA_QM_1_CQ_CTL_STS 0x4080E0 101*e65e175bSOded Gabbay 102*e65e175bSOded Gabbay #define mmDMA_QM_1_CQ_STS0 0x4080E4 103*e65e175bSOded Gabbay 104*e65e175bSOded Gabbay #define mmDMA_QM_1_CQ_STS1 0x4080E8 105*e65e175bSOded Gabbay 106*e65e175bSOded Gabbay #define mmDMA_QM_1_CQ_RD_RATE_LIM_EN 0x4080F0 107*e65e175bSOded Gabbay 108*e65e175bSOded Gabbay #define mmDMA_QM_1_CQ_RD_RATE_LIM_RST_TOKEN 0x4080F4 109*e65e175bSOded Gabbay 110*e65e175bSOded Gabbay #define mmDMA_QM_1_CQ_RD_RATE_LIM_SAT 0x4080F8 111*e65e175bSOded Gabbay 112*e65e175bSOded Gabbay #define mmDMA_QM_1_CQ_RD_RATE_LIM_TOUT 0x4080FC 113*e65e175bSOded Gabbay 114*e65e175bSOded Gabbay #define mmDMA_QM_1_CQ_IFIFO_CNT 0x408108 115*e65e175bSOded Gabbay 116*e65e175bSOded Gabbay #define mmDMA_QM_1_CP_MSG_BASE0_ADDR_LO 0x408120 117*e65e175bSOded Gabbay 118*e65e175bSOded Gabbay #define mmDMA_QM_1_CP_MSG_BASE0_ADDR_HI 0x408124 119*e65e175bSOded Gabbay 120*e65e175bSOded Gabbay #define mmDMA_QM_1_CP_MSG_BASE1_ADDR_LO 0x408128 121*e65e175bSOded Gabbay 122*e65e175bSOded Gabbay #define mmDMA_QM_1_CP_MSG_BASE1_ADDR_HI 0x40812C 123*e65e175bSOded Gabbay 124*e65e175bSOded Gabbay #define mmDMA_QM_1_CP_MSG_BASE2_ADDR_LO 0x408130 125*e65e175bSOded Gabbay 126*e65e175bSOded Gabbay #define mmDMA_QM_1_CP_MSG_BASE2_ADDR_HI 0x408134 127*e65e175bSOded Gabbay 128*e65e175bSOded Gabbay #define mmDMA_QM_1_CP_MSG_BASE3_ADDR_LO 0x408138 129*e65e175bSOded Gabbay 130*e65e175bSOded Gabbay #define mmDMA_QM_1_CP_MSG_BASE3_ADDR_HI 0x40813C 131*e65e175bSOded Gabbay 132*e65e175bSOded Gabbay #define mmDMA_QM_1_CP_LDMA_TSIZE_OFFSET 0x408140 133*e65e175bSOded Gabbay 134*e65e175bSOded Gabbay #define mmDMA_QM_1_CP_LDMA_SRC_BASE_LO_OFFSET 0x408144 135*e65e175bSOded Gabbay 136*e65e175bSOded Gabbay #define mmDMA_QM_1_CP_LDMA_SRC_BASE_HI_OFFSET 0x408148 137*e65e175bSOded Gabbay 138*e65e175bSOded Gabbay #define mmDMA_QM_1_CP_LDMA_DST_BASE_LO_OFFSET 0x40814C 139*e65e175bSOded Gabbay 140*e65e175bSOded Gabbay #define mmDMA_QM_1_CP_LDMA_DST_BASE_HI_OFFSET 0x408150 141*e65e175bSOded Gabbay 142*e65e175bSOded Gabbay #define mmDMA_QM_1_CP_LDMA_COMMIT_OFFSET 0x408154 143*e65e175bSOded Gabbay 144*e65e175bSOded Gabbay #define mmDMA_QM_1_CP_FENCE0_RDATA 0x408158 145*e65e175bSOded Gabbay 146*e65e175bSOded Gabbay #define mmDMA_QM_1_CP_FENCE1_RDATA 0x40815C 147*e65e175bSOded Gabbay 148*e65e175bSOded Gabbay #define mmDMA_QM_1_CP_FENCE2_RDATA 0x408160 149*e65e175bSOded Gabbay 150*e65e175bSOded Gabbay #define mmDMA_QM_1_CP_FENCE3_RDATA 0x408164 151*e65e175bSOded Gabbay 152*e65e175bSOded Gabbay #define mmDMA_QM_1_CP_FENCE0_CNT 0x408168 153*e65e175bSOded Gabbay 154*e65e175bSOded Gabbay #define mmDMA_QM_1_CP_FENCE1_CNT 0x40816C 155*e65e175bSOded Gabbay 156*e65e175bSOded Gabbay #define mmDMA_QM_1_CP_FENCE2_CNT 0x408170 157*e65e175bSOded Gabbay 158*e65e175bSOded Gabbay #define mmDMA_QM_1_CP_FENCE3_CNT 0x408174 159*e65e175bSOded Gabbay 160*e65e175bSOded Gabbay #define mmDMA_QM_1_CP_STS 0x408178 161*e65e175bSOded Gabbay 162*e65e175bSOded Gabbay #define mmDMA_QM_1_CP_CURRENT_INST_LO 0x40817C 163*e65e175bSOded Gabbay 164*e65e175bSOded Gabbay #define mmDMA_QM_1_CP_CURRENT_INST_HI 0x408180 165*e65e175bSOded Gabbay 166*e65e175bSOded Gabbay #define mmDMA_QM_1_CP_BARRIER_CFG 0x408184 167*e65e175bSOded Gabbay 168*e65e175bSOded Gabbay #define mmDMA_QM_1_CP_DBG_0 0x408188 169*e65e175bSOded Gabbay 170*e65e175bSOded Gabbay #define mmDMA_QM_1_PQ_BUF_ADDR 0x408300 171*e65e175bSOded Gabbay 172*e65e175bSOded Gabbay #define mmDMA_QM_1_PQ_BUF_RDATA 0x408304 173*e65e175bSOded Gabbay 174*e65e175bSOded Gabbay #define mmDMA_QM_1_CQ_BUF_ADDR 0x408308 175*e65e175bSOded Gabbay 176*e65e175bSOded Gabbay #define mmDMA_QM_1_CQ_BUF_RDATA 0x40830C 177*e65e175bSOded Gabbay 178*e65e175bSOded Gabbay #endif /* ASIC_REG_DMA_QM_1_REGS_H_ */ 179