Lines Matching +full:0 +full:x408000
32 { "MMID", 89, 0 },
33 { "DDR", 104, 0 },
34 { "CONFIGID0", 176, 0 },
35 { "CONFIGID1", 208, 0 },
36 { "INTERRUPT", 226, 0 },
37 { "INTCLEAR", 227, 0 },
38 { "CCOUNT", 234, 0 },
39 { "PRID", 235, 0 },
40 { "ICOUNT", 236, 0 },
41 { "CCOMPARE0", 240, 0 },
42 { "CCOMPARE1", 241, 0 },
43 { "CCOMPARE2", 242, 0 },
44 { "VECBASE", 231, 0 },
45 { "EPC1", 177, 0 },
46 { "EPC2", 178, 0 },
47 { "EPC3", 179, 0 },
48 { "EPC4", 180, 0 },
49 { "EPC5", 181, 0 },
50 { "EPC6", 182, 0 },
51 { "EPC7", 183, 0 },
52 { "EXCSAVE1", 209, 0 },
53 { "EXCSAVE2", 210, 0 },
54 { "EXCSAVE3", 211, 0 },
55 { "EXCSAVE4", 212, 0 },
56 { "EXCSAVE5", 213, 0 },
57 { "EXCSAVE6", 214, 0 },
58 { "EXCSAVE7", 215, 0 },
59 { "EPS2", 194, 0 },
60 { "EPS3", 195, 0 },
61 { "EPS4", 196, 0 },
62 { "EPS5", 197, 0 },
63 { "EPS6", 198, 0 },
64 { "EPS7", 199, 0 },
65 { "EXCCAUSE", 232, 0 },
66 { "DEPC", 192, 0 },
67 { "EXCVADDR", 238, 0 },
68 { "WINDOWBASE", 72, 0 },
69 { "WINDOWSTART", 73, 0 },
70 { "SAR", 3, 0 },
71 { "PS", 230, 0 },
72 { "MISC0", 244, 0 },
73 { "MISC1", 245, 0 },
74 { "INTENABLE", 228, 0 },
75 { "DBREAKA0", 144, 0 },
76 { "DBREAKC0", 160, 0 },
77 { "DBREAKA1", 145, 0 },
78 { "DBREAKC1", 161, 0 },
79 { "IBREAKA0", 128, 0 },
80 { "IBREAKA1", 129, 0 },
81 { "IBREAKENABLE", 96, 0 },
82 { "ICOUNTLEVEL", 237, 0 },
83 { "DEBUGCAUSE", 233, 0 },
84 { "SCOMPARE1", 12, 0 },
85 { "ATOMCTL", 99, 0 },
97 { "PC", 32, 0 },
98 { "ICOUNT", 32, 0 },
99 { "DDR", 32, 0 },
100 { "INTERRUPT", 22, 0 },
101 { "CCOUNT", 32, 0 },
102 { "XTSYNC", 1, 0 },
103 { "VECBASE", 22, 0 },
104 { "EPC1", 32, 0 },
105 { "EPC2", 32, 0 },
106 { "EPC3", 32, 0 },
107 { "EPC4", 32, 0 },
108 { "EPC5", 32, 0 },
109 { "EPC6", 32, 0 },
110 { "EPC7", 32, 0 },
111 { "EXCSAVE1", 32, 0 },
112 { "EXCSAVE2", 32, 0 },
113 { "EXCSAVE3", 32, 0 },
114 { "EXCSAVE4", 32, 0 },
115 { "EXCSAVE5", 32, 0 },
116 { "EXCSAVE6", 32, 0 },
117 { "EXCSAVE7", 32, 0 },
118 { "EPS2", 13, 0 },
119 { "EPS3", 13, 0 },
120 { "EPS4", 13, 0 },
121 { "EPS5", 13, 0 },
122 { "EPS6", 13, 0 },
123 { "EPS7", 13, 0 },
124 { "EXCCAUSE", 6, 0 },
125 { "PSINTLEVEL", 4, 0 },
126 { "PSUM", 1, 0 },
127 { "PSWOE", 1, 0 },
128 { "PSEXCM", 1, 0 },
129 { "DEPC", 32, 0 },
130 { "EXCVADDR", 32, 0 },
131 { "WindowBase", 3, 0 },
132 { "WindowStart", 8, 0 },
133 { "PSCALLINC", 2, 0 },
134 { "PSOWB", 4, 0 },
135 { "SAR", 6, 0 },
136 { "MISC0", 32, 0 },
137 { "MISC1", 32, 0 },
138 { "InOCDMode", 1, 0 },
139 { "INTENABLE", 22, 0 },
140 { "DBREAKA0", 32, 0 },
141 { "DBREAKC0", 8, 0 },
142 { "DBREAKA1", 32, 0 },
143 { "DBREAKC1", 8, 0 },
144 { "IBREAKA0", 32, 0 },
145 { "IBREAKA1", 32, 0 },
146 { "IBREAKENABLE", 2, 0 },
147 { "ICOUNTLEVEL", 4, 0 },
148 { "DEBUGCAUSE", 6, 0 },
149 { "DBNUM", 4, 0 },
150 { "CCOMPARE0", 32, 0 },
151 { "CCOMPARE1", 32, 0 },
152 { "CCOMPARE2", 32, 0 },
153 { "SCOMPARE1", 32, 0 },
154 { "ATOMCTL", 6, 0 },
228 unsigned tie_t = 0;
229 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
238 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
244 unsigned tie_t = 0;
245 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
254 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
260 unsigned tie_t = 0;
261 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
270 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
276 unsigned tie_t = 0;
277 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
286 insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
292 unsigned tie_t = 0;
293 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
302 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
308 unsigned tie_t = 0;
309 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
318 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
324 unsigned tie_t = 0;
325 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
334 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
340 unsigned tie_t = 0;
341 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
350 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
356 unsigned tie_t = 0;
357 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
358 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
367 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
369 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
375 unsigned tie_t = 0;
376 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
385 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
391 unsigned tie_t = 0;
392 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
393 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
402 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
404 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
410 unsigned tie_t = 0;
411 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
420 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
426 unsigned tie_t = 0;
427 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
436 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
442 unsigned tie_t = 0;
443 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
452 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
458 unsigned tie_t = 0;
459 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
468 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
474 unsigned tie_t = 0;
475 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
484 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
490 unsigned tie_t = 0;
491 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
500 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
506 unsigned tie_t = 0;
507 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
516 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
522 unsigned tie_t = 0;
523 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
532 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
538 unsigned tie_t = 0;
539 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
548 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
554 unsigned tie_t = 0;
555 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
564 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
570 unsigned tie_t = 0;
571 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
572 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
581 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
583 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
589 unsigned tie_t = 0;
590 tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
599 insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
605 unsigned tie_t = 0;
606 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
615 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
621 unsigned tie_t = 0;
622 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
631 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
637 unsigned tie_t = 0;
638 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
639 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
648 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
650 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
656 unsigned tie_t = 0;
657 tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
666 insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
672 unsigned tie_t = 0;
673 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
682 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
688 unsigned tie_t = 0;
689 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
698 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
704 unsigned tie_t = 0;
705 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
714 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
720 unsigned tie_t = 0;
721 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
730 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
736 unsigned tie_t = 0;
737 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
738 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
747 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
749 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
755 unsigned tie_t = 0;
756 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
757 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
766 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
768 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
774 unsigned tie_t = 0;
775 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
776 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
785 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
787 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
793 unsigned tie_t = 0;
794 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
803 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
809 unsigned tie_t = 0;
810 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
811 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
820 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
822 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
828 unsigned tie_t = 0;
829 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
830 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
839 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
841 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
847 unsigned tie_t = 0;
848 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
849 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
858 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
860 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
866 unsigned tie_t = 0;
867 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
868 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
877 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
879 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
885 unsigned tie_t = 0;
886 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
887 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
896 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
898 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
904 unsigned tie_t = 0;
905 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
914 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
920 unsigned tie_t = 0;
921 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
930 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
936 unsigned tie_t = 0;
937 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
946 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
952 unsigned tie_t = 0;
953 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
954 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
963 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
965 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
971 unsigned tie_t = 0;
972 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
981 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
987 unsigned tie_t = 0;
988 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
997 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1003 unsigned tie_t = 0;
1004 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1013 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1019 unsigned tie_t = 0;
1020 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1029 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1035 unsigned tie_t = 0;
1036 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1045 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1051 unsigned tie_t = 0;
1052 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1061 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1067 unsigned tie_t = 0;
1068 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1077 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1083 unsigned tie_t = 0;
1084 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1093 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1099 unsigned tie_t = 0;
1100 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1109 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1115 unsigned tie_t = 0;
1116 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1125 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1131 unsigned tie_t = 0;
1132 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1133 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1142 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1144 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1150 unsigned tie_t = 0;
1151 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1152 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1161 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1163 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1169 unsigned tie_t = 0;
1170 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1171 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1180 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1182 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1188 unsigned tie_t = 0;
1189 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1190 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1199 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1201 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1207 unsigned tie_t = 0;
1208 tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
1217 insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
1223 unsigned tie_t = 0;
1224 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
1233 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
1239 unsigned tie_t = 0;
1240 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1241 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1250 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1252 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1258 unsigned tie_t = 0;
1259 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1260 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1269 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1271 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1277 unsigned tie_t = 0;
1278 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1279 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1288 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1290 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1296 unsigned tie_t = 0;
1297 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
1306 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1312 unsigned tie_t = 0;
1313 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
1322 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1335 return 0;
1405 #define funcUnits 0
1422 { "IMPWIRE", 32, 0, 0, 'i' }
1434 0xffffffff,
1435 0x1,
1436 0x2,
1437 0x3,
1438 0x4,
1439 0x5,
1440 0x6,
1441 0x7,
1442 0x8,
1443 0x9,
1444 0xa,
1445 0xb,
1446 0xc,
1447 0xd,
1448 0xe,
1449 0xf,
1450 0
1455 0xffffffff,
1456 0x1,
1457 0x2,
1458 0x3,
1459 0x4,
1460 0x5,
1461 0x6,
1462 0x7,
1463 0x8,
1464 0xa,
1465 0xc,
1466 0x10,
1467 0x20,
1468 0x40,
1469 0x80,
1470 0x100,
1471 0
1476 0x8000,
1477 0x10000,
1478 0x2,
1479 0x3,
1480 0x4,
1481 0x5,
1482 0x6,
1483 0x7,
1484 0x8,
1485 0xa,
1486 0xc,
1487 0x10,
1488 0x20,
1489 0x40,
1490 0x80,
1491 0x100,
1492 0
1503 soffsetx4_in_0 = *valp & 0x3ffff;
1504 soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2);
1506 return 0;
1515 soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff;
1517 return 0;
1525 uimm12x8_in_0 = *valp & 0xfff;
1528 return 0;
1537 uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff);
1539 return 0;
1547 simm4_in_0 = *valp & 0xf;
1550 return 0;
1559 simm4_in_0 = (simm4_out_0 & 0xf);
1561 return 0;
1567 return 0;
1579 return 0;
1591 return 0;
1603 return 0;
1615 return 0;
1627 return 0;
1641 immrx4_in_0 = *valp & 0xf;
1642 immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2;
1644 return 0;
1653 immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf);
1655 return 0;
1663 lsi4x4_in_0 = *valp & 0xf;
1666 return 0;
1675 lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf);
1677 return 0;
1685 simm7_in_0 = *valp & 0x7f;
1686 …simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | …
1688 return 0;
1697 simm7_in_0 = (simm7_out_0 & 0x7f);
1699 return 0;
1707 uimm6_in_0 = *valp & 0x3f;
1708 uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0);
1710 return 0;
1719 uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f;
1721 return 0;
1729 ai4const_in_0 = *valp & 0xf;
1730 ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf];
1732 return 0;
1743 case 0xffffffff: ai4const_in_0 = 0; break;
1744 case 0x1: ai4const_in_0 = 0x1; break;
1745 case 0x2: ai4const_in_0 = 0x2; break;
1746 case 0x3: ai4const_in_0 = 0x3; break;
1747 case 0x4: ai4const_in_0 = 0x4; break;
1748 case 0x5: ai4const_in_0 = 0x5; break;
1749 case 0x6: ai4const_in_0 = 0x6; break;
1750 case 0x7: ai4const_in_0 = 0x7; break;
1751 case 0x8: ai4const_in_0 = 0x8; break;
1752 case 0x9: ai4const_in_0 = 0x9; break;
1753 case 0xa: ai4const_in_0 = 0xa; break;
1754 case 0xb: ai4const_in_0 = 0xb; break;
1755 case 0xc: ai4const_in_0 = 0xc; break;
1756 case 0xd: ai4const_in_0 = 0xd; break;
1757 case 0xe: ai4const_in_0 = 0xe; break;
1758 default: ai4const_in_0 = 0xf; break;
1761 return 0;
1769 b4const_in_0 = *valp & 0xf;
1770 b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf];
1772 return 0;
1783 case 0xffffffff: b4const_in_0 = 0; break;
1784 case 0x1: b4const_in_0 = 0x1; break;
1785 case 0x2: b4const_in_0 = 0x2; break;
1786 case 0x3: b4const_in_0 = 0x3; break;
1787 case 0x4: b4const_in_0 = 0x4; break;
1788 case 0x5: b4const_in_0 = 0x5; break;
1789 case 0x6: b4const_in_0 = 0x6; break;
1790 case 0x7: b4const_in_0 = 0x7; break;
1791 case 0x8: b4const_in_0 = 0x8; break;
1792 case 0xa: b4const_in_0 = 0x9; break;
1793 case 0xc: b4const_in_0 = 0xa; break;
1794 case 0x10: b4const_in_0 = 0xb; break;
1795 case 0x20: b4const_in_0 = 0xc; break;
1796 case 0x40: b4const_in_0 = 0xd; break;
1797 case 0x80: b4const_in_0 = 0xe; break;
1798 default: b4const_in_0 = 0xf; break;
1801 return 0;
1809 b4constu_in_0 = *valp & 0xf;
1810 b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf];
1812 return 0;
1823 case 0x8000: b4constu_in_0 = 0; break;
1824 case 0x10000: b4constu_in_0 = 0x1; break;
1825 case 0x2: b4constu_in_0 = 0x2; break;
1826 case 0x3: b4constu_in_0 = 0x3; break;
1827 case 0x4: b4constu_in_0 = 0x4; break;
1828 case 0x5: b4constu_in_0 = 0x5; break;
1829 case 0x6: b4constu_in_0 = 0x6; break;
1830 case 0x7: b4constu_in_0 = 0x7; break;
1831 case 0x8: b4constu_in_0 = 0x8; break;
1832 case 0xa: b4constu_in_0 = 0x9; break;
1833 case 0xc: b4constu_in_0 = 0xa; break;
1834 case 0x10: b4constu_in_0 = 0xb; break;
1835 case 0x20: b4constu_in_0 = 0xc; break;
1836 case 0x40: b4constu_in_0 = 0xd; break;
1837 case 0x80: b4constu_in_0 = 0xe; break;
1838 default: b4constu_in_0 = 0xf; break;
1841 return 0;
1849 uimm8_in_0 = *valp & 0xff;
1852 return 0;
1861 uimm8_in_0 = (uimm8_out_0 & 0xff);
1863 return 0;
1871 uimm8x2_in_0 = *valp & 0xff;
1874 return 0;
1883 uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff);
1885 return 0;
1893 uimm8x4_in_0 = *valp & 0xff;
1896 return 0;
1905 uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff);
1907 return 0;
1915 uimm4x16_in_0 = *valp & 0xf;
1918 return 0;
1927 uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf);
1929 return 0;
1937 uimmrx4_in_0 = *valp & 0xf;
1940 return 0;
1949 uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf);
1951 return 0;
1959 simm8_in_0 = *valp & 0xff;
1962 return 0;
1971 simm8_in_0 = (simm8_out_0 & 0xff);
1973 return 0;
1981 simm8x256_in_0 = *valp & 0xff;
1984 return 0;
1993 simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff);
1995 return 0;
2003 simm12b_in_0 = *valp & 0xfff;
2006 return 0;
2015 simm12b_in_0 = (simm12b_out_0 & 0xfff);
2017 return 0;
2025 msalp32_in_0 = *valp & 0x1f;
2026 msalp32_out_0 = 0x20 - msalp32_in_0;
2028 return 0;
2037 msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f;
2039 return 0;
2047 op2p1_in_0 = *valp & 0xf;
2048 op2p1_out_0 = op2p1_in_0 + 0x1;
2050 return 0;
2059 op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf;
2061 return 0;
2069 label8_in_0 = *valp & 0xff;
2070 label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24);
2072 return 0;
2081 label8_in_0 = (label8_out_0 - 0x4) & 0xff;
2083 return 0;
2091 label12_in_0 = *valp & 0xfff;
2092 label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20);
2094 return 0;
2103 label12_in_0 = (label12_out_0 - 0x4) & 0xfff;
2105 return 0;
2113 soffset_in_0 = *valp & 0x3ffff;
2114 soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14);
2116 return 0;
2125 soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff;
2127 return 0;
2135 uimm16x4_in_0 = *valp & 0xffff;
2136 uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2;
2138 return 0;
2147 uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff;
2149 return 0;
2157 bbi_in_0 = *valp & 0x1f;
2158 bbi_out_0 = (0 << 5) | bbi_in_0;
2160 return 0;
2169 bbi_in_0 = (bbi_out_0 & 0x1f);
2171 return 0;
2179 s_in_0 = *valp & 0xf;
2180 s_out_0 = (0 << 4) | s_in_0;
2182 return 0;
2191 s_in_0 = (s_out_0 & 0xf);
2193 return 0;
2201 immt_in_0 = *valp & 0xf;
2204 return 0;
2213 immt_in_0 = immt_out_0 & 0xf;
2215 return 0;
2223 tp7_in_0 = *valp & 0xf;
2224 tp7_out_0 = tp7_in_0 + 0x7;
2226 return 0;
2235 tp7_in_0 = (tp7_out_0 - 0x7) & 0xf;
2237 return 0;
2245 xt_wbr15_label_in_0 = *valp & 0x7fff;
2246 xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17);
2248 return 0;
2257 xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff;
2259 return 0;
2267 xt_wbr18_label_in_0 = *valp & 0x3ffff;
2268 xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14);
2270 return 0;
2279 xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff;
2281 return 0;
2289 bitindex_in_0 = *valp & 0x1f;
2290 bitindex_out_0 = (0 << 5) | bitindex_in_0;
2292 return 0;
2301 bitindex_in_0 = (bitindex_out_0 & 0x1f);
2303 return 0;
2309 *valp -= (pc & ~0x3);
2310 return 0;
2316 *valp += (pc & ~0x3);
2317 return 0;
2324 return 0;
2331 return 0;
2338 return 0;
2345 return 0;
2352 return 0;
2359 return 0;
2366 return 0;
2373 return 0;
2379 *valp -= ((pc + 3) & ~0x3);
2380 return 0;
2386 *valp += ((pc + 3) & ~0x3);
2387 return 0;
2394 return 0;
2401 return 0;
2408 return 0;
2415 return 0;
2419 { "soffsetx4", FIELD_offset, -1, 0,
2423 { "uimm12x8", FIELD_imm12, -1, 0,
2424 0,
2426 0, 0 },
2427 { "simm4", FIELD_mn, -1, 0,
2428 0,
2430 0, 0 },
2434 0, 0 },
2438 0, 0 },
2442 0, 0 },
2446 0, 0 },
2450 0, 0 },
2454 0, 0 },
2458 0, 0 },
2462 0, 0 },
2466 0, 0 },
2467 { "immrx4", FIELD_r, -1, 0,
2468 0,
2470 0, 0 },
2471 { "lsi4x4", FIELD_r, -1, 0,
2472 0,
2474 0, 0 },
2475 { "simm7", FIELD_imm7, -1, 0,
2476 0,
2478 0, 0 },
2479 { "uimm6", FIELD_imm6, -1, 0,
2483 { "ai4const", FIELD_t, -1, 0,
2484 0,
2486 0, 0 },
2487 { "b4const", FIELD_r, -1, 0,
2488 0,
2490 0, 0 },
2491 { "b4constu", FIELD_r, -1, 0,
2492 0,
2494 0, 0 },
2495 { "uimm8", FIELD_imm8, -1, 0,
2496 0,
2498 0, 0 },
2499 { "uimm8x2", FIELD_imm8, -1, 0,
2500 0,
2502 0, 0 },
2503 { "uimm8x4", FIELD_imm8, -1, 0,
2504 0,
2506 0, 0 },
2507 { "uimm4x16", FIELD_op2, -1, 0,
2508 0,
2510 0, 0 },
2511 { "uimmrx4", FIELD_r, -1, 0,
2512 0,
2514 0, 0 },
2515 { "simm8", FIELD_imm8, -1, 0,
2516 0,
2518 0, 0 },
2519 { "simm8x256", FIELD_imm8, -1, 0,
2520 0,
2522 0, 0 },
2523 { "simm12b", FIELD_imm12b, -1, 0,
2524 0,
2526 0, 0 },
2527 { "msalp32", FIELD_sal, -1, 0,
2528 0,
2530 0, 0 },
2531 { "op2p1", FIELD_op2, -1, 0,
2532 0,
2534 0, 0 },
2535 { "label8", FIELD_imm8, -1, 0,
2539 { "label12", FIELD_imm12, -1, 0,
2543 { "soffset", FIELD_offset, -1, 0,
2547 { "uimm16x4", FIELD_imm16, -1, 0,
2551 { "bbi", FIELD_bbi, -1, 0,
2552 0,
2554 0, 0 },
2555 { "sae", FIELD_sae, -1, 0,
2556 0,
2558 0, 0 },
2559 { "sas", FIELD_sas, -1, 0,
2560 0,
2562 0, 0 },
2563 { "sargt", FIELD_sargt, -1, 0,
2564 0,
2566 0, 0 },
2567 { "s", FIELD_s, -1, 0,
2568 0,
2570 0, 0 },
2571 { "immt", FIELD_t, -1, 0,
2572 0,
2574 0, 0 },
2575 { "imms", FIELD_s, -1, 0,
2576 0,
2578 0, 0 },
2579 { "tp7", FIELD_t, -1, 0,
2580 0,
2582 0, 0 },
2583 { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
2587 { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
2591 { "bitindex", FIELD_bitindex, -1, 0,
2592 0,
2594 0, 0 },
2595 { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
2596 { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
2597 { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
2598 { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
2599 { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
2600 { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
2601 { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
2602 { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
2603 { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
2604 { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
2605 { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
2606 { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
2607 { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
2608 { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
2609 { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
2610 { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
2611 { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
2612 { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
2613 { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
2614 { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
2615 { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
2616 { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
2617 { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
2618 { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
2619 { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
2620 { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
2621 { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
2622 { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
2623 { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
2624 { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
2625 { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
2626 { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
2627 { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 }
4648 { 0, 0 /* xt_iclass_excw */,
4649 0, 0, 0, 0 },
4650 { 0, 0 /* xt_iclass_rfe */,
4651 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
4652 { 0, 0 /* xt_iclass_rfde */,
4653 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
4654 { 0, 0 /* xt_iclass_syscall */,
4655 0, 0, 0, 0 },
4657 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
4659 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
4661 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
4663 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
4665 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
4667 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
4669 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
4671 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
4673 1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
4675 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
4676 { 0, 0 /* xt_iclass_rfwou */,
4677 5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
4679 0, 0, 0, 0 },
4681 0, 0, 0, 0 },
4683 1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
4685 1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
4687 1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
4689 1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
4691 1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
4693 1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
4695 0, 0, 0, 0 },
4697 0, 0, 0, 0 },
4699 0, 0, 0, 0 },
4700 { 0, 0 /* xt_iclass_ill_n */,
4701 0, 0, 0, 0 },
4703 0, 0, 0, 0 },
4705 0, 0, 0, 0 },
4707 0, 0, 0, 0 },
4708 { 0, 0 /* xt_iclass_nopn */,
4709 0, 0, 0, 0 },
4711 0, 0, 0, 0 },
4713 0, 0, 0, 0 },
4715 0, 0, 0, 0 },
4717 0, 0, 0, 0 },
4719 0, 0, 0, 0 },
4721 0, 0, 0, 0 },
4723 0, 0, 0, 0 },
4725 0, 0, 0, 0 },
4727 0, 0, 0, 0 },
4729 0, 0, 0, 0 },
4731 0, 0, 0, 0 },
4733 0, 0, 0, 0 },
4735 0, 0, 0, 0 },
4737 0, 0, 0, 0 },
4738 { 0, 0 /* xt_iclass_ill */,
4739 0, 0, 0, 0 },
4741 0, 0, 0, 0 },
4743 0, 0, 0, 0 },
4745 0, 0, 0, 0 },
4747 0, 0, 0, 0 },
4749 0, 0, 0, 0 },
4751 0, 0, 0, 0 },
4753 0, 0, 0, 0 },
4755 0, 0, 0, 0 },
4757 0, 0, 0, 0 },
4759 0, 0, 0, 0 },
4760 { 0, 0 /* xt_iclass_nop */,
4761 0, 0, 0, 0 },
4763 0, 0, 0, 0 },
4764 { 0, 0 /* xt_iclass_simcall */,
4765 0, 0, 0, 0 },
4767 0, 0, 0, 0 },
4769 0, 0, 0, 0 },
4771 0, 0, 0, 0 },
4773 0, 0, 0, 0 },
4775 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
4777 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
4779 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
4781 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
4783 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
4785 0, 0, 0, 0 },
4787 0, 0, 0, 0 },
4789 0, 0, 0, 0 },
4790 { 0, 0 /* xt_iclass_memw */,
4791 0, 0, 0, 0 },
4792 { 0, 0 /* xt_iclass_extw */,
4793 0, 0, 0, 0 },
4794 { 0, 0 /* xt_iclass_isync */,
4795 0, 0, 0, 0 },
4796 { 0, 0 /* xt_iclass_sync */,
4797 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
4799 6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
4801 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
4803 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
4805 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
4807 0, 0, 0, 0 },
4809 0, 0, 0, 0 },
4811 0, 0, 0, 0 },
4813 0, 0, 0, 0 },
4815 0, 0, 0, 0 },
4817 0, 0, 0, 0 },
4819 0, 0, 0, 0 },
4821 0, 0, 0, 0 },
4823 0, 0, 0, 0 },
4825 6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
4827 6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
4829 6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
4831 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
4833 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
4835 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
4837 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
4839 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
4841 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
4843 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
4845 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
4847 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
4849 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
4851 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
4853 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
4855 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
4857 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
4859 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
4861 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
4863 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
4865 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
4867 1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
4869 1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
4871 1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
4873 1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
4875 1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
4877 1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
4879 1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
4881 1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
4883 1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
4885 1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
4887 1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
4889 1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
4891 1, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
4893 1, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
4895 1, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
4897 1, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
4899 1, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
4901 1, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
4903 1, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
4905 1, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
4907 1, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
4909 1, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
4911 1, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
4913 1, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
4915 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
4917 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
4919 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
4921 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
4923 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
4925 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
4927 1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
4929 1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
4931 1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
4933 1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
4935 1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
4937 1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
4939 1, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
4941 1, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
4943 1, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
4945 1, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
4947 1, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
4949 1, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
4951 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
4953 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
4955 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
4957 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
4959 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
4961 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
4963 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
4965 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
4967 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
4969 1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
4971 1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
4973 1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
4975 1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
4977 1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
4979 1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
4981 0, 0, 0, 0 },
4983 1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
4985 1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
4987 1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
4989 0, 0, 0, 0 },
4991 0, 0, 0, 0 },
4993 0, 0, 0, 0 },
4995 20, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
4997 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
4999 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
5001 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
5003 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
5005 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
5007 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
5009 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
5011 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
5013 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
5015 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
5017 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
5019 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
5021 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
5023 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
5025 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
5027 1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
5029 2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
5031 2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
5033 1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
5035 2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
5037 2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
5039 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
5041 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
5043 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
5045 1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
5047 1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
5049 1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
5051 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
5053 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
5055 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
5057 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
5059 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
5061 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
5063 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
5065 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
5067 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
5069 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
5071 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
5073 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
5075 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
5077 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
5079 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
5081 3, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 },
5083 2, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 },
5085 9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
5086 { 0, 0 /* xt_iclass_rfdd */,
5087 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
5089 1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
5091 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
5093 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
5095 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
5097 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
5099 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
5101 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
5103 1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
5105 2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
5107 2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
5109 1, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
5111 2, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
5113 2, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
5115 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
5117 0, 0, 0, 0 },
5119 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
5121 0, 0, 0, 0 },
5123 0, 0, 0, 0 },
5125 0, 0, 0, 0 },
5127 0, 0, 0, 0 },
5129 0, 0, 0, 0 },
5131 0, 0, 0, 0 },
5133 0, 0, 0, 0 },
5135 0, 0, 0, 0 },
5137 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
5139 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
5141 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
5143 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
5145 1, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 },
5147 2, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 },
5149 2, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 },
5151 0, 0, 0, 0 },
5153 0, 0, 0, 0 },
5155 0, 0, 0, 0 },
5157 0, 0, 0, 0 },
5159 0, 0, 0, 0 },
5161 0, 0, 0, 0 },
5163 1, Iclass_rur_expstate_stateArgs, 0, 0 },
5165 1, Iclass_wur_expstate_stateArgs, 0, 0 },
5167 0, 0, 1, Iclass_iclass_READ_IMPWIRE_intfArgs },
5169 1, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 },
5171 1, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 },
5173 1, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }
5448 slotbuf[0] = 0x2080;
5454 slotbuf[0] = 0x3000;
5460 slotbuf[0] = 0x3200;
5466 slotbuf[0] = 0x5000;
5472 slotbuf[0] = 0x35;
5478 slotbuf[0] = 0x25;
5484 slotbuf[0] = 0x15;
5490 slotbuf[0] = 0xf0;
5496 slotbuf[0] = 0xe0;
5502 slotbuf[0] = 0xd0;
5508 slotbuf[0] = 0x36;
5514 slotbuf[0] = 0x1000;
5520 slotbuf[0] = 0x408000;
5526 slotbuf[0] = 0x90;
5532 slotbuf[0] = 0xf01d;
5538 slotbuf[0] = 0x3400;
5544 slotbuf[0] = 0x3500;
5550 slotbuf[0] = 0x90000;
5556 slotbuf[0] = 0x490000;
5562 slotbuf[0] = 0x34800;
5568 slotbuf[0] = 0x134800;
5574 slotbuf[0] = 0x614800;
5580 slotbuf[0] = 0x34900;
5586 slotbuf[0] = 0x134900;
5592 slotbuf[0] = 0x614900;
5598 slotbuf[0] = 0xa;
5604 slotbuf[0] = 0xb;
5610 slotbuf[0] = 0x8c;
5616 slotbuf[0] = 0xcc;
5622 slotbuf[0] = 0xf06d;
5628 slotbuf[0] = 0x8;
5634 slotbuf[0] = 0xd;
5640 slotbuf[0] = 0xc;
5646 slotbuf[0] = 0xf03d;
5652 slotbuf[0] = 0xf00d;
5658 slotbuf[0] = 0x9;
5664 slotbuf[0] = 0xc002;
5670 slotbuf[0] = 0xd002;
5676 slotbuf[0] = 0x800000;
5682 slotbuf[0] = 0xc00000;
5688 slotbuf[0] = 0x900000;
5694 slotbuf[0] = 0xa00000;
5700 slotbuf[0] = 0xb00000;
5706 slotbuf[0] = 0xd00000;
5712 slotbuf[0] = 0xe00000;
5718 slotbuf[0] = 0xf00000;
5724 slotbuf[0] = 0x100000;
5730 slotbuf[0] = 0x200000;
5736 slotbuf[0] = 0x300000;
5742 slotbuf[0] = 0x26;
5748 slotbuf[0] = 0x66;
5754 slotbuf[0] = 0xe6;
5760 slotbuf[0] = 0xa6;
5766 slotbuf[0] = 0x6007;
5772 slotbuf[0] = 0xe007;
5778 slotbuf[0] = 0xf6;
5784 slotbuf[0] = 0xb6;
5790 slotbuf[0] = 0x1007;
5796 slotbuf[0] = 0x9007;
5802 slotbuf[0] = 0xa007;
5808 slotbuf[0] = 0x2007;
5814 slotbuf[0] = 0xb007;
5820 slotbuf[0] = 0x3007;
5826 slotbuf[0] = 0x8007;
5832 slotbuf[0] = 0x7;
5838 slotbuf[0] = 0x4007;
5844 slotbuf[0] = 0xc007;
5850 slotbuf[0] = 0x5007;
5856 slotbuf[0] = 0xd007;
5862 slotbuf[0] = 0x16;
5868 slotbuf[0] = 0x56;
5874 slotbuf[0] = 0xd6;
5880 slotbuf[0] = 0x96;
5886 slotbuf[0] = 0x5;
5892 slotbuf[0] = 0xc0;
5898 slotbuf[0] = 0x40000;
5904 slotbuf[0] = 0;
5910 slotbuf[0] = 0x6;
5916 slotbuf[0] = 0xa0;
5922 slotbuf[0] = 0x1002;
5928 slotbuf[0] = 0x9002;
5934 slotbuf[0] = 0x2002;
5940 slotbuf[0] = 0x1;
5946 slotbuf[0] = 0x2;
5952 slotbuf[0] = 0xa002;
5958 slotbuf[0] = 0x830000;
5964 slotbuf[0] = 0x930000;
5970 slotbuf[0] = 0xa30000;
5976 slotbuf[0] = 0xb30000;
5982 slotbuf[0] = 0x600000;
5988 slotbuf[0] = 0x600100;
5994 slotbuf[0] = 0x20f0;
6000 slotbuf[0] = 0x80;
6006 slotbuf[0] = 0x5100;
6012 slotbuf[0] = 0x5002;
6018 slotbuf[0] = 0x6002;
6024 slotbuf[0] = 0x590000;
6030 slotbuf[0] = 0x4002;
6036 slotbuf[0] = 0x400000;
6042 slotbuf[0] = 0x401000;
6048 slotbuf[0] = 0x402000;
6054 slotbuf[0] = 0x403000;
6060 slotbuf[0] = 0x404000;
6066 slotbuf[0] = 0xa10000;
6072 slotbuf[0] = 0x810000;
6078 slotbuf[0] = 0x910000;
6084 slotbuf[0] = 0xb10000;
6090 slotbuf[0] = 0x10000;
6096 slotbuf[0] = 0x210000;
6102 slotbuf[0] = 0x410000;
6108 slotbuf[0] = 0x20c0;
6114 slotbuf[0] = 0x20d0;
6120 slotbuf[0] = 0x2000;
6126 slotbuf[0] = 0x2010;
6132 slotbuf[0] = 0x2020;
6138 slotbuf[0] = 0x2030;
6144 slotbuf[0] = 0x6000;
6150 slotbuf[0] = 0x30300;
6156 slotbuf[0] = 0x130300;
6162 slotbuf[0] = 0x610300;
6168 slotbuf[0] = 0x36100;
6174 slotbuf[0] = 0x136100;
6180 slotbuf[0] = 0x616100;
6186 slotbuf[0] = 0x30500;
6192 slotbuf[0] = 0x130500;
6198 slotbuf[0] = 0x610500;
6204 slotbuf[0] = 0x3b000;
6210 slotbuf[0] = 0x13b000;
6216 slotbuf[0] = 0x3d000;
6222 slotbuf[0] = 0x3e600;
6228 slotbuf[0] = 0x13e600;
6234 slotbuf[0] = 0x61e600;
6240 slotbuf[0] = 0x3b100;
6246 slotbuf[0] = 0x13b100;
6252 slotbuf[0] = 0x61b100;
6258 slotbuf[0] = 0x3d100;
6264 slotbuf[0] = 0x13d100;
6270 slotbuf[0] = 0x61d100;
6276 slotbuf[0] = 0x3b200;
6282 slotbuf[0] = 0x13b200;
6288 slotbuf[0] = 0x61b200;
6294 slotbuf[0] = 0x3d200;
6300 slotbuf[0] = 0x13d200;
6306 slotbuf[0] = 0x61d200;
6312 slotbuf[0] = 0x3b300;
6318 slotbuf[0] = 0x13b300;
6324 slotbuf[0] = 0x61b300;
6330 slotbuf[0] = 0x3d300;
6336 slotbuf[0] = 0x13d300;
6342 slotbuf[0] = 0x61d300;
6348 slotbuf[0] = 0x3b400;
6354 slotbuf[0] = 0x13b400;
6360 slotbuf[0] = 0x61b400;
6366 slotbuf[0] = 0x3d400;
6372 slotbuf[0] = 0x13d400;
6378 slotbuf[0] = 0x61d400;
6384 slotbuf[0] = 0x3b500;
6390 slotbuf[0] = 0x13b500;
6396 slotbuf[0] = 0x61b500;
6402 slotbuf[0] = 0x3d500;
6408 slotbuf[0] = 0x13d500;
6414 slotbuf[0] = 0x61d500;
6420 slotbuf[0] = 0x3b600;
6426 slotbuf[0] = 0x13b600;
6432 slotbuf[0] = 0x61b600;
6438 slotbuf[0] = 0x3d600;
6444 slotbuf[0] = 0x13d600;
6450 slotbuf[0] = 0x61d600;
6456 slotbuf[0] = 0x3b700;
6462 slotbuf[0] = 0x13b700;
6468 slotbuf[0] = 0x61b700;
6474 slotbuf[0] = 0x3d700;
6480 slotbuf[0] = 0x13d700;
6486 slotbuf[0] = 0x61d700;
6492 slotbuf[0] = 0x3c200;
6498 slotbuf[0] = 0x13c200;
6504 slotbuf[0] = 0x61c200;
6510 slotbuf[0] = 0x3c300;
6516 slotbuf[0] = 0x13c300;
6522 slotbuf[0] = 0x61c300;
6528 slotbuf[0] = 0x3c400;
6534 slotbuf[0] = 0x13c400;
6540 slotbuf[0] = 0x61c400;
6546 slotbuf[0] = 0x3c500;
6552 slotbuf[0] = 0x13c500;
6558 slotbuf[0] = 0x61c500;
6564 slotbuf[0] = 0x3c600;
6570 slotbuf[0] = 0x13c600;
6576 slotbuf[0] = 0x61c600;
6582 slotbuf[0] = 0x3c700;
6588 slotbuf[0] = 0x13c700;
6594 slotbuf[0] = 0x61c700;
6600 slotbuf[0] = 0x3ee00;
6606 slotbuf[0] = 0x13ee00;
6612 slotbuf[0] = 0x61ee00;
6618 slotbuf[0] = 0x3c000;
6624 slotbuf[0] = 0x13c000;
6630 slotbuf[0] = 0x61c000;
6636 slotbuf[0] = 0x3e800;
6642 slotbuf[0] = 0x13e800;
6648 slotbuf[0] = 0x61e800;
6654 slotbuf[0] = 0x3f400;
6660 slotbuf[0] = 0x13f400;
6666 slotbuf[0] = 0x61f400;
6672 slotbuf[0] = 0x3f500;
6678 slotbuf[0] = 0x13f500;
6684 slotbuf[0] = 0x61f500;
6690 slotbuf[0] = 0x3eb00;
6696 slotbuf[0] = 0x3e700;
6702 slotbuf[0] = 0x13e700;
6708 slotbuf[0] = 0x61e700;
6714 slotbuf[0] = 0x720000;
6720 slotbuf[0] = 0x620000;
6726 slotbuf[0] = 0xc10000;
6732 slotbuf[0] = 0xd10000;
6738 slotbuf[0] = 0x820000;
6744 slotbuf[0] = 0x3010;
6750 slotbuf[0] = 0x7000;
6756 slotbuf[0] = 0x3e200;
6762 slotbuf[0] = 0x13e200;
6768 slotbuf[0] = 0x13e300;
6774 slotbuf[0] = 0x3e400;
6780 slotbuf[0] = 0x13e400;
6786 slotbuf[0] = 0x61e400;
6792 slotbuf[0] = 0x4000;
6798 slotbuf[0] = 0xf02d;
6804 slotbuf[0] = 0x39000;
6810 slotbuf[0] = 0x139000;
6816 slotbuf[0] = 0x619000;
6822 slotbuf[0] = 0x3a000;
6828 slotbuf[0] = 0x13a000;
6834 slotbuf[0] = 0x61a000;
6840 slotbuf[0] = 0x39100;
6846 slotbuf[0] = 0x139100;
6852 slotbuf[0] = 0x619100;
6858 slotbuf[0] = 0x3a100;
6864 slotbuf[0] = 0x13a100;
6870 slotbuf[0] = 0x61a100;
6876 slotbuf[0] = 0x38000;
6882 slotbuf[0] = 0x138000;
6888 slotbuf[0] = 0x618000;
6894 slotbuf[0] = 0x38100;
6900 slotbuf[0] = 0x138100;
6906 slotbuf[0] = 0x618100;
6912 slotbuf[0] = 0x36000;
6918 slotbuf[0] = 0x136000;
6924 slotbuf[0] = 0x616000;
6930 slotbuf[0] = 0x3e900;
6936 slotbuf[0] = 0x13e900;
6942 slotbuf[0] = 0x61e900;
6948 slotbuf[0] = 0x3ec00;
6954 slotbuf[0] = 0x13ec00;
6960 slotbuf[0] = 0x61ec00;
6966 slotbuf[0] = 0x3ed00;
6972 slotbuf[0] = 0x13ed00;
6978 slotbuf[0] = 0x61ed00;
6984 slotbuf[0] = 0x36800;
6990 slotbuf[0] = 0x136800;
6996 slotbuf[0] = 0x616800;
7002 slotbuf[0] = 0x70e0;
7008 slotbuf[0] = 0x70f0;
7014 slotbuf[0] = 0xf1e000;
7020 slotbuf[0] = 0xf1e010;
7026 slotbuf[0] = 0x135900;
7032 slotbuf[0] = 0x3ea00;
7038 slotbuf[0] = 0x13ea00;
7044 slotbuf[0] = 0x61ea00;
7050 slotbuf[0] = 0x3f000;
7056 slotbuf[0] = 0x13f000;
7062 slotbuf[0] = 0x61f000;
7068 slotbuf[0] = 0x3f100;
7074 slotbuf[0] = 0x13f100;
7080 slotbuf[0] = 0x61f100;
7086 slotbuf[0] = 0x3f200;
7092 slotbuf[0] = 0x13f200;
7098 slotbuf[0] = 0x61f200;
7104 slotbuf[0] = 0x50c000;
7110 slotbuf[0] = 0x50d000;
7116 slotbuf[0] = 0x50b000;
7122 slotbuf[0] = 0x50f000;
7128 slotbuf[0] = 0x50e000;
7134 slotbuf[0] = 0x504000;
7140 slotbuf[0] = 0x505000;
7146 slotbuf[0] = 0x503000;
7152 slotbuf[0] = 0x507000;
7158 slotbuf[0] = 0x506000;
7164 slotbuf[0] = 0x430000;
7170 slotbuf[0] = 0x530000;
7176 slotbuf[0] = 0x630000;
7182 slotbuf[0] = 0x730000;
7188 slotbuf[0] = 0x40e000;
7194 slotbuf[0] = 0x40f000;
7200 slotbuf[0] = 0x230000;
7206 slotbuf[0] = 0xb002;
7212 slotbuf[0] = 0xf002;
7218 slotbuf[0] = 0xe002;
7224 slotbuf[0] = 0x30c00;
7230 slotbuf[0] = 0x130c00;
7236 slotbuf[0] = 0x610c00;
7242 slotbuf[0] = 0x36300;
7248 slotbuf[0] = 0x136300;
7254 slotbuf[0] = 0x616300;
7260 slotbuf[0] = 0xc20000;
7266 slotbuf[0] = 0xd20000;
7272 slotbuf[0] = 0xe20000;
7278 slotbuf[0] = 0xf20000;
7284 slotbuf[0] = 0x35f00;
7290 slotbuf[0] = 0x135f00;
7296 slotbuf[0] = 0x615f00;
7302 slotbuf[0] = 0x406000;
7308 slotbuf[0] = 0x407000;
7314 slotbuf[0] = 0xe30e60;
7320 slotbuf[0] = 0xf3e600;
7326 slotbuf[0] = 0xe0000;
7332 slotbuf[0] = 0xe1000;
7338 slotbuf[0] = 0xe1200;
7344 slotbuf[0] = 0xe2000;
7348 Opcode_excw_Slot_inst_encode, 0, 0
7352 Opcode_rfe_Slot_inst_encode, 0, 0
7356 Opcode_rfde_Slot_inst_encode, 0, 0
7360 Opcode_syscall_Slot_inst_encode, 0, 0
7364 Opcode_call12_Slot_inst_encode, 0, 0
7368 Opcode_call8_Slot_inst_encode, 0, 0
7372 Opcode_call4_Slot_inst_encode, 0, 0
7376 Opcode_callx12_Slot_inst_encode, 0, 0
7380 Opcode_callx8_Slot_inst_encode, 0, 0
7384 Opcode_callx4_Slot_inst_encode, 0, 0
7388 Opcode_entry_Slot_inst_encode, 0, 0
7392 Opcode_movsp_Slot_inst_encode, 0, 0
7396 Opcode_rotw_Slot_inst_encode, 0, 0
7400 Opcode_retw_Slot_inst_encode, 0, 0
7404 0, 0, Opcode_retw_n_Slot_inst16b_encode
7408 Opcode_rfwo_Slot_inst_encode, 0, 0
7412 Opcode_rfwu_Slot_inst_encode, 0, 0
7416 Opcode_l32e_Slot_inst_encode, 0, 0
7420 Opcode_s32e_Slot_inst_encode, 0, 0
7424 Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
7428 Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
7432 Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
7436 Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
7440 Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
7444 Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
7448 0, Opcode_add_n_Slot_inst16a_encode, 0
7452 0, Opcode_addi_n_Slot_inst16a_encode, 0
7456 0, 0, Opcode_beqz_n_Slot_inst16b_encode
7460 0, 0, Opcode_bnez_n_Slot_inst16b_encode
7464 0, 0, Opcode_ill_n_Slot_inst16b_encode
7468 0, Opcode_l32i_n_Slot_inst16a_encode, 0
7472 0, 0, Opcode_mov_n_Slot_inst16b_encode
7476 0, 0, Opcode_movi_n_Slot_inst16b_encode
7480 0, 0, Opcode_nop_n_Slot_inst16b_encode
7484 0, 0, Opcode_ret_n_Slot_inst16b_encode
7488 0, Opcode_s32i_n_Slot_inst16a_encode, 0
7492 Opcode_addi_Slot_inst_encode, 0, 0
7496 Opcode_addmi_Slot_inst_encode, 0, 0
7500 Opcode_add_Slot_inst_encode, 0, 0
7504 Opcode_sub_Slot_inst_encode, 0, 0
7508 Opcode_addx2_Slot_inst_encode, 0, 0
7512 Opcode_addx4_Slot_inst_encode, 0, 0
7516 Opcode_addx8_Slot_inst_encode, 0, 0
7520 Opcode_subx2_Slot_inst_encode, 0, 0
7524 Opcode_subx4_Slot_inst_encode, 0, 0
7528 Opcode_subx8_Slot_inst_encode, 0, 0
7532 Opcode_and_Slot_inst_encode, 0, 0
7536 Opcode_or_Slot_inst_encode, 0, 0
7540 Opcode_xor_Slot_inst_encode, 0, 0
7544 Opcode_beqi_Slot_inst_encode, 0, 0
7548 Opcode_bnei_Slot_inst_encode, 0, 0
7552 Opcode_bgei_Slot_inst_encode, 0, 0
7556 Opcode_blti_Slot_inst_encode, 0, 0
7560 Opcode_bbci_Slot_inst_encode, 0, 0
7564 Opcode_bbsi_Slot_inst_encode, 0, 0
7568 Opcode_bgeui_Slot_inst_encode, 0, 0
7572 Opcode_bltui_Slot_inst_encode, 0, 0
7576 Opcode_beq_Slot_inst_encode, 0, 0
7580 Opcode_bne_Slot_inst_encode, 0, 0
7584 Opcode_bge_Slot_inst_encode, 0, 0
7588 Opcode_blt_Slot_inst_encode, 0, 0
7592 Opcode_bgeu_Slot_inst_encode, 0, 0
7596 Opcode_bltu_Slot_inst_encode, 0, 0
7600 Opcode_bany_Slot_inst_encode, 0, 0
7604 Opcode_bnone_Slot_inst_encode, 0, 0
7608 Opcode_ball_Slot_inst_encode, 0, 0
7612 Opcode_bnall_Slot_inst_encode, 0, 0
7616 Opcode_bbc_Slot_inst_encode, 0, 0
7620 Opcode_bbs_Slot_inst_encode, 0, 0
7624 Opcode_beqz_Slot_inst_encode, 0, 0
7628 Opcode_bnez_Slot_inst_encode, 0, 0
7632 Opcode_bgez_Slot_inst_encode, 0, 0
7636 Opcode_bltz_Slot_inst_encode, 0, 0
7640 Opcode_call0_Slot_inst_encode, 0, 0
7644 Opcode_callx0_Slot_inst_encode, 0, 0
7648 Opcode_extui_Slot_inst_encode, 0, 0
7652 Opcode_ill_Slot_inst_encode, 0, 0
7656 Opcode_j_Slot_inst_encode, 0, 0
7660 Opcode_jx_Slot_inst_encode, 0, 0
7664 Opcode_l16ui_Slot_inst_encode, 0, 0
7668 Opcode_l16si_Slot_inst_encode, 0, 0
7672 Opcode_l32i_Slot_inst_encode, 0, 0
7676 Opcode_l32r_Slot_inst_encode, 0, 0
7680 Opcode_l8ui_Slot_inst_encode, 0, 0
7684 Opcode_movi_Slot_inst_encode, 0, 0
7688 Opcode_moveqz_Slot_inst_encode, 0, 0
7692 Opcode_movnez_Slot_inst_encode, 0, 0
7696 Opcode_movltz_Slot_inst_encode, 0, 0
7700 Opcode_movgez_Slot_inst_encode, 0, 0
7704 Opcode_neg_Slot_inst_encode, 0, 0
7708 Opcode_abs_Slot_inst_encode, 0, 0
7712 Opcode_nop_Slot_inst_encode, 0, 0
7716 Opcode_ret_Slot_inst_encode, 0, 0
7720 Opcode_simcall_Slot_inst_encode, 0, 0
7724 Opcode_s16i_Slot_inst_encode, 0, 0
7728 Opcode_s32i_Slot_inst_encode, 0, 0
7732 Opcode_s32nb_Slot_inst_encode, 0, 0
7736 Opcode_s8i_Slot_inst_encode, 0, 0
7740 Opcode_ssr_Slot_inst_encode, 0, 0
7744 Opcode_ssl_Slot_inst_encode, 0, 0
7748 Opcode_ssa8l_Slot_inst_encode, 0, 0
7752 Opcode_ssa8b_Slot_inst_encode, 0, 0
7756 Opcode_ssai_Slot_inst_encode, 0, 0
7760 Opcode_sll_Slot_inst_encode, 0, 0
7764 Opcode_src_Slot_inst_encode, 0, 0
7768 Opcode_srl_Slot_inst_encode, 0, 0
7772 Opcode_sra_Slot_inst_encode, 0, 0
7776 Opcode_slli_Slot_inst_encode, 0, 0
7780 Opcode_srai_Slot_inst_encode, 0, 0
7784 Opcode_srli_Slot_inst_encode, 0, 0
7788 Opcode_memw_Slot_inst_encode, 0, 0
7792 Opcode_extw_Slot_inst_encode, 0, 0
7796 Opcode_isync_Slot_inst_encode, 0, 0
7800 Opcode_rsync_Slot_inst_encode, 0, 0
7804 Opcode_esync_Slot_inst_encode, 0, 0
7808 Opcode_dsync_Slot_inst_encode, 0, 0
7812 Opcode_rsil_Slot_inst_encode, 0, 0
7816 Opcode_rsr_sar_Slot_inst_encode, 0, 0
7820 Opcode_wsr_sar_Slot_inst_encode, 0, 0
7824 Opcode_xsr_sar_Slot_inst_encode, 0, 0
7828 Opcode_rsr_memctl_Slot_inst_encode, 0, 0
7832 Opcode_wsr_memctl_Slot_inst_encode, 0, 0
7836 Opcode_xsr_memctl_Slot_inst_encode, 0, 0
7840 Opcode_rsr_litbase_Slot_inst_encode, 0, 0
7844 Opcode_wsr_litbase_Slot_inst_encode, 0, 0
7848 Opcode_xsr_litbase_Slot_inst_encode, 0, 0
7852 Opcode_rsr_configid0_Slot_inst_encode, 0, 0
7856 Opcode_wsr_configid0_Slot_inst_encode, 0, 0
7860 Opcode_rsr_configid1_Slot_inst_encode, 0, 0
7864 Opcode_rsr_ps_Slot_inst_encode, 0, 0
7868 Opcode_wsr_ps_Slot_inst_encode, 0, 0
7872 Opcode_xsr_ps_Slot_inst_encode, 0, 0
7876 Opcode_rsr_epc1_Slot_inst_encode, 0, 0
7880 Opcode_wsr_epc1_Slot_inst_encode, 0, 0
7884 Opcode_xsr_epc1_Slot_inst_encode, 0, 0
7888 Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
7892 Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
7896 Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
7900 Opcode_rsr_epc2_Slot_inst_encode, 0, 0
7904 Opcode_wsr_epc2_Slot_inst_encode, 0, 0
7908 Opcode_xsr_epc2_Slot_inst_encode, 0, 0
7912 Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
7916 Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
7920 Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
7924 Opcode_rsr_epc3_Slot_inst_encode, 0, 0
7928 Opcode_wsr_epc3_Slot_inst_encode, 0, 0
7932 Opcode_xsr_epc3_Slot_inst_encode, 0, 0
7936 Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
7940 Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
7944 Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
7948 Opcode_rsr_epc4_Slot_inst_encode, 0, 0
7952 Opcode_wsr_epc4_Slot_inst_encode, 0, 0
7956 Opcode_xsr_epc4_Slot_inst_encode, 0, 0
7960 Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
7964 Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
7968 Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
7972 Opcode_rsr_epc5_Slot_inst_encode, 0, 0
7976 Opcode_wsr_epc5_Slot_inst_encode, 0, 0
7980 Opcode_xsr_epc5_Slot_inst_encode, 0, 0
7984 Opcode_rsr_excsave5_Slot_inst_encode, 0, 0
7988 Opcode_wsr_excsave5_Slot_inst_encode, 0, 0
7992 Opcode_xsr_excsave5_Slot_inst_encode, 0, 0
7996 Opcode_rsr_epc6_Slot_inst_encode, 0, 0
8000 Opcode_wsr_epc6_Slot_inst_encode, 0, 0
8004 Opcode_xsr_epc6_Slot_inst_encode, 0, 0
8008 Opcode_rsr_excsave6_Slot_inst_encode, 0, 0
8012 Opcode_wsr_excsave6_Slot_inst_encode, 0, 0
8016 Opcode_xsr_excsave6_Slot_inst_encode, 0, 0
8020 Opcode_rsr_epc7_Slot_inst_encode, 0, 0
8024 Opcode_wsr_epc7_Slot_inst_encode, 0, 0
8028 Opcode_xsr_epc7_Slot_inst_encode, 0, 0
8032 Opcode_rsr_excsave7_Slot_inst_encode, 0, 0
8036 Opcode_wsr_excsave7_Slot_inst_encode, 0, 0
8040 Opcode_xsr_excsave7_Slot_inst_encode, 0, 0
8044 Opcode_rsr_eps2_Slot_inst_encode, 0, 0
8048 Opcode_wsr_eps2_Slot_inst_encode, 0, 0
8052 Opcode_xsr_eps2_Slot_inst_encode, 0, 0
8056 Opcode_rsr_eps3_Slot_inst_encode, 0, 0
8060 Opcode_wsr_eps3_Slot_inst_encode, 0, 0
8064 Opcode_xsr_eps3_Slot_inst_encode, 0, 0
8068 Opcode_rsr_eps4_Slot_inst_encode, 0, 0
8072 Opcode_wsr_eps4_Slot_inst_encode, 0, 0
8076 Opcode_xsr_eps4_Slot_inst_encode, 0, 0
8080 Opcode_rsr_eps5_Slot_inst_encode, 0, 0
8084 Opcode_wsr_eps5_Slot_inst_encode, 0, 0
8088 Opcode_xsr_eps5_Slot_inst_encode, 0, 0
8092 Opcode_rsr_eps6_Slot_inst_encode, 0, 0
8096 Opcode_wsr_eps6_Slot_inst_encode, 0, 0
8100 Opcode_xsr_eps6_Slot_inst_encode, 0, 0
8104 Opcode_rsr_eps7_Slot_inst_encode, 0, 0
8108 Opcode_wsr_eps7_Slot_inst_encode, 0, 0
8112 Opcode_xsr_eps7_Slot_inst_encode, 0, 0
8116 Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
8120 Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
8124 Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
8128 Opcode_rsr_depc_Slot_inst_encode, 0, 0
8132 Opcode_wsr_depc_Slot_inst_encode, 0, 0
8136 Opcode_xsr_depc_Slot_inst_encode, 0, 0
8140 Opcode_rsr_exccause_Slot_inst_encode, 0, 0
8144 Opcode_wsr_exccause_Slot_inst_encode, 0, 0
8148 Opcode_xsr_exccause_Slot_inst_encode, 0, 0
8152 Opcode_rsr_misc0_Slot_inst_encode, 0, 0
8156 Opcode_wsr_misc0_Slot_inst_encode, 0, 0
8160 Opcode_xsr_misc0_Slot_inst_encode, 0, 0
8164 Opcode_rsr_misc1_Slot_inst_encode, 0, 0
8168 Opcode_wsr_misc1_Slot_inst_encode, 0, 0
8172 Opcode_xsr_misc1_Slot_inst_encode, 0, 0
8176 Opcode_rsr_prid_Slot_inst_encode, 0, 0
8180 Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
8184 Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
8188 Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
8192 Opcode_salt_Slot_inst_encode, 0, 0
8196 Opcode_saltu_Slot_inst_encode, 0, 0
8200 Opcode_mul16u_Slot_inst_encode, 0, 0
8204 Opcode_mul16s_Slot_inst_encode, 0, 0
8208 Opcode_mull_Slot_inst_encode, 0, 0
8212 Opcode_rfi_Slot_inst_encode, 0, 0
8216 Opcode_waiti_Slot_inst_encode, 0, 0
8220 Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
8224 Opcode_wsr_intset_Slot_inst_encode, 0, 0
8228 Opcode_wsr_intclear_Slot_inst_encode, 0, 0
8232 Opcode_rsr_intenable_Slot_inst_encode, 0, 0
8236 Opcode_wsr_intenable_Slot_inst_encode, 0, 0
8240 Opcode_xsr_intenable_Slot_inst_encode, 0, 0
8244 Opcode_break_Slot_inst_encode, 0, 0
8248 0, 0, Opcode_break_n_Slot_inst16b_encode
8252 Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
8256 Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
8260 Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
8264 Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
8268 Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
8272 Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
8276 Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
8280 Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
8284 Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
8288 Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
8292 Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
8296 Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
8300 Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
8304 Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
8308 Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
8312 Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
8316 Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
8320 Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
8324 Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
8328 Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
8332 Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
8336 Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
8340 Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
8344 Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
8348 Opcode_rsr_icount_Slot_inst_encode, 0, 0
8352 Opcode_wsr_icount_Slot_inst_encode, 0, 0
8356 Opcode_xsr_icount_Slot_inst_encode, 0, 0
8360 Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
8364 Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
8368 Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
8372 Opcode_rsr_ddr_Slot_inst_encode, 0, 0
8376 Opcode_wsr_ddr_Slot_inst_encode, 0, 0
8380 Opcode_xsr_ddr_Slot_inst_encode, 0, 0
8384 Opcode_lddr32_p_Slot_inst_encode, 0, 0
8388 Opcode_sddr32_p_Slot_inst_encode, 0, 0
8392 Opcode_rfdo_Slot_inst_encode, 0, 0
8396 Opcode_rfdd_Slot_inst_encode, 0, 0
8400 Opcode_wsr_mmid_Slot_inst_encode, 0, 0
8404 Opcode_rsr_ccount_Slot_inst_encode, 0, 0
8408 Opcode_wsr_ccount_Slot_inst_encode, 0, 0
8412 Opcode_xsr_ccount_Slot_inst_encode, 0, 0
8416 Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
8420 Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
8424 Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
8428 Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
8432 Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
8436 Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
8440 Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
8444 Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
8448 Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
8452 Opcode_idtlb_Slot_inst_encode, 0, 0
8456 Opcode_pdtlb_Slot_inst_encode, 0, 0
8460 Opcode_rdtlb0_Slot_inst_encode, 0, 0
8464 Opcode_rdtlb1_Slot_inst_encode, 0, 0
8468 Opcode_wdtlb_Slot_inst_encode, 0, 0
8472 Opcode_iitlb_Slot_inst_encode, 0, 0
8476 Opcode_pitlb_Slot_inst_encode, 0, 0
8480 Opcode_ritlb0_Slot_inst_encode, 0, 0
8484 Opcode_ritlb1_Slot_inst_encode, 0, 0
8488 Opcode_witlb_Slot_inst_encode, 0, 0
8492 Opcode_min_Slot_inst_encode, 0, 0
8496 Opcode_max_Slot_inst_encode, 0, 0
8500 Opcode_minu_Slot_inst_encode, 0, 0
8504 Opcode_maxu_Slot_inst_encode, 0, 0
8508 Opcode_nsa_Slot_inst_encode, 0, 0
8512 Opcode_nsau_Slot_inst_encode, 0, 0
8516 Opcode_sext_Slot_inst_encode, 0, 0
8520 Opcode_l32ai_Slot_inst_encode, 0, 0
8524 Opcode_s32ri_Slot_inst_encode, 0, 0
8528 Opcode_s32c1i_Slot_inst_encode, 0, 0
8532 Opcode_rsr_scompare1_Slot_inst_encode, 0, 0
8536 Opcode_wsr_scompare1_Slot_inst_encode, 0, 0
8540 Opcode_xsr_scompare1_Slot_inst_encode, 0, 0
8544 Opcode_rsr_atomctl_Slot_inst_encode, 0, 0
8548 Opcode_wsr_atomctl_Slot_inst_encode, 0, 0
8552 Opcode_xsr_atomctl_Slot_inst_encode, 0, 0
8556 Opcode_quou_Slot_inst_encode, 0, 0
8560 Opcode_quos_Slot_inst_encode, 0, 0
8564 Opcode_remu_Slot_inst_encode, 0, 0
8568 Opcode_rems_Slot_inst_encode, 0, 0
8572 Opcode_rsr_eraccess_Slot_inst_encode, 0, 0
8576 Opcode_wsr_eraccess_Slot_inst_encode, 0, 0
8580 Opcode_xsr_eraccess_Slot_inst_encode, 0, 0
8584 Opcode_rer_Slot_inst_encode, 0, 0
8588 Opcode_wer_Slot_inst_encode, 0, 0
8592 Opcode_rur_expstate_Slot_inst_encode, 0, 0
8596 Opcode_wur_expstate_Slot_inst_encode, 0, 0
8600 Opcode_read_impwire_Slot_inst_encode, 0, 0
8604 Opcode_setb_expstate_Slot_inst_encode, 0, 0
8608 Opcode_clrb_expstate_Slot_inst_encode, 0, 0
8612 Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0
8623 0,
8624 Opcode_excw_encode_fns, 0, 0 },
8627 Opcode_rfe_encode_fns, 0, 0 },
8630 Opcode_rfde_encode_fns, 0, 0 },
8632 0,
8633 Opcode_syscall_encode_fns, 0, 0 },
8636 Opcode_call12_encode_fns, 0, 0 },
8639 Opcode_call8_encode_fns, 0, 0 },
8642 Opcode_call4_encode_fns, 0, 0 },
8645 Opcode_callx12_encode_fns, 0, 0 },
8648 Opcode_callx8_encode_fns, 0, 0 },
8651 Opcode_callx4_encode_fns, 0, 0 },
8653 0,
8654 Opcode_entry_encode_fns, 0, 0 },
8656 0,
8657 Opcode_movsp_encode_fns, 0, 0 },
8659 0,
8660 Opcode_rotw_encode_fns, 0, 0 },
8663 Opcode_retw_encode_fns, 0, 0 },
8666 Opcode_retw_n_encode_fns, 0, 0 },
8669 Opcode_rfwo_encode_fns, 0, 0 },
8672 Opcode_rfwu_encode_fns, 0, 0 },
8674 0,
8675 Opcode_l32e_encode_fns, 0, 0 },
8677 0,
8678 Opcode_s32e_encode_fns, 0, 0 },
8680 0,
8681 Opcode_rsr_windowbase_encode_fns, 0, 0 },
8683 0,
8684 Opcode_wsr_windowbase_encode_fns, 0, 0 },
8686 0,
8687 Opcode_xsr_windowbase_encode_fns, 0, 0 },
8689 0,
8690 Opcode_rsr_windowstart_encode_fns, 0, 0 },
8692 0,
8693 Opcode_wsr_windowstart_encode_fns, 0, 0 },
8695 0,
8696 Opcode_xsr_windowstart_encode_fns, 0, 0 },
8698 0,
8699 Opcode_add_n_encode_fns, 0, 0 },
8701 0,
8702 Opcode_addi_n_encode_fns, 0, 0 },
8705 Opcode_beqz_n_encode_fns, 0, 0 },
8708 Opcode_bnez_n_encode_fns, 0, 0 },
8710 0,
8711 Opcode_ill_n_encode_fns, 0, 0 },
8713 0,
8714 Opcode_l32i_n_encode_fns, 0, 0 },
8716 0,
8717 Opcode_mov_n_encode_fns, 0, 0 },
8719 0,
8720 Opcode_movi_n_encode_fns, 0, 0 },
8722 0,
8723 Opcode_nop_n_encode_fns, 0, 0 },
8726 Opcode_ret_n_encode_fns, 0, 0 },
8728 0,
8729 Opcode_s32i_n_encode_fns, 0, 0 },
8731 0,
8732 Opcode_addi_encode_fns, 0, 0 },
8734 0,
8735 Opcode_addmi_encode_fns, 0, 0 },
8737 0,
8738 Opcode_add_encode_fns, 0, 0 },
8740 0,
8741 Opcode_sub_encode_fns, 0, 0 },
8743 0,
8744 Opcode_addx2_encode_fns, 0, 0 },
8746 0,
8747 Opcode_addx4_encode_fns, 0, 0 },
8749 0,
8750 Opcode_addx8_encode_fns, 0, 0 },
8752 0,
8753 Opcode_subx2_encode_fns, 0, 0 },
8755 0,
8756 Opcode_subx4_encode_fns, 0, 0 },
8758 0,
8759 Opcode_subx8_encode_fns, 0, 0 },
8761 0,
8762 Opcode_and_encode_fns, 0, 0 },
8764 0,
8765 Opcode_or_encode_fns, 0, 0 },
8767 0,
8768 Opcode_xor_encode_fns, 0, 0 },
8771 Opcode_beqi_encode_fns, 0, 0 },
8774 Opcode_bnei_encode_fns, 0, 0 },
8777 Opcode_bgei_encode_fns, 0, 0 },
8780 Opcode_blti_encode_fns, 0, 0 },
8783 Opcode_bbci_encode_fns, 0, 0 },
8786 Opcode_bbsi_encode_fns, 0, 0 },
8789 Opcode_bgeui_encode_fns, 0, 0 },
8792 Opcode_bltui_encode_fns, 0, 0 },
8795 Opcode_beq_encode_fns, 0, 0 },
8798 Opcode_bne_encode_fns, 0, 0 },
8801 Opcode_bge_encode_fns, 0, 0 },
8804 Opcode_blt_encode_fns, 0, 0 },
8807 Opcode_bgeu_encode_fns, 0, 0 },
8810 Opcode_bltu_encode_fns, 0, 0 },
8813 Opcode_bany_encode_fns, 0, 0 },
8816 Opcode_bnone_encode_fns, 0, 0 },
8819 Opcode_ball_encode_fns, 0, 0 },
8822 Opcode_bnall_encode_fns, 0, 0 },
8825 Opcode_bbc_encode_fns, 0, 0 },
8828 Opcode_bbs_encode_fns, 0, 0 },
8831 Opcode_beqz_encode_fns, 0, 0 },
8834 Opcode_bnez_encode_fns, 0, 0 },
8837 Opcode_bgez_encode_fns, 0, 0 },
8840 Opcode_bltz_encode_fns, 0, 0 },
8843 Opcode_call0_encode_fns, 0, 0 },
8846 Opcode_callx0_encode_fns, 0, 0 },
8848 0,
8849 Opcode_extui_encode_fns, 0, 0 },
8851 0,
8852 Opcode_ill_encode_fns, 0, 0 },
8855 Opcode_j_encode_fns, 0, 0 },
8858 Opcode_jx_encode_fns, 0, 0 },
8860 0,
8861 Opcode_l16ui_encode_fns, 0, 0 },
8863 0,
8864 Opcode_l16si_encode_fns, 0, 0 },
8866 0,
8867 Opcode_l32i_encode_fns, 0, 0 },
8869 0,
8870 Opcode_l32r_encode_fns, 0, 0 },
8872 0,
8873 Opcode_l8ui_encode_fns, 0, 0 },
8875 0,
8876 Opcode_movi_encode_fns, 0, 0 },
8878 0,
8879 Opcode_moveqz_encode_fns, 0, 0 },
8881 0,
8882 Opcode_movnez_encode_fns, 0, 0 },
8884 0,
8885 Opcode_movltz_encode_fns, 0, 0 },
8887 0,
8888 Opcode_movgez_encode_fns, 0, 0 },
8890 0,
8891 Opcode_neg_encode_fns, 0, 0 },
8893 0,
8894 Opcode_abs_encode_fns, 0, 0 },
8896 0,
8897 Opcode_nop_encode_fns, 0, 0 },
8900 Opcode_ret_encode_fns, 0, 0 },
8902 0,
8903 Opcode_simcall_encode_fns, 0, 0 },
8905 0,
8906 Opcode_s16i_encode_fns, 0, 0 },
8908 0,
8909 Opcode_s32i_encode_fns, 0, 0 },
8911 0,
8912 Opcode_s32nb_encode_fns, 0, 0 },
8914 0,
8915 Opcode_s8i_encode_fns, 0, 0 },
8917 0,
8918 Opcode_ssr_encode_fns, 0, 0 },
8920 0,
8921 Opcode_ssl_encode_fns, 0, 0 },
8923 0,
8924 Opcode_ssa8l_encode_fns, 0, 0 },
8926 0,
8927 Opcode_ssa8b_encode_fns, 0, 0 },
8929 0,
8930 Opcode_ssai_encode_fns, 0, 0 },
8932 0,
8933 Opcode_sll_encode_fns, 0, 0 },
8935 0,
8936 Opcode_src_encode_fns, 0, 0 },
8938 0,
8939 Opcode_srl_encode_fns, 0, 0 },
8941 0,
8942 Opcode_sra_encode_fns, 0, 0 },
8944 0,
8945 Opcode_slli_encode_fns, 0, 0 },
8947 0,
8948 Opcode_srai_encode_fns, 0, 0 },
8950 0,
8951 Opcode_srli_encode_fns, 0, 0 },
8953 0,
8954 Opcode_memw_encode_fns, 0, 0 },
8956 0,
8957 Opcode_extw_encode_fns, 0, 0 },
8959 0,
8960 Opcode_isync_encode_fns, 0, 0 },
8962 0,
8963 Opcode_rsync_encode_fns, 0, 0 },
8965 0,
8966 Opcode_esync_encode_fns, 0, 0 },
8968 0,
8969 Opcode_dsync_encode_fns, 0, 0 },
8971 0,
8972 Opcode_rsil_encode_fns, 0, 0 },
8974 0,
8975 Opcode_rsr_sar_encode_fns, 0, 0 },
8977 0,
8978 Opcode_wsr_sar_encode_fns, 0, 0 },
8980 0,
8981 Opcode_xsr_sar_encode_fns, 0, 0 },
8983 0,
8984 Opcode_rsr_memctl_encode_fns, 0, 0 },
8986 0,
8987 Opcode_wsr_memctl_encode_fns, 0, 0 },
8989 0,
8990 Opcode_xsr_memctl_encode_fns, 0, 0 },
8992 0,
8993 Opcode_rsr_litbase_encode_fns, 0, 0 },
8995 0,
8996 Opcode_wsr_litbase_encode_fns, 0, 0 },
8998 0,
8999 Opcode_xsr_litbase_encode_fns, 0, 0 },
9001 0,
9002 Opcode_rsr_configid0_encode_fns, 0, 0 },
9004 0,
9005 Opcode_wsr_configid0_encode_fns, 0, 0 },
9007 0,
9008 Opcode_rsr_configid1_encode_fns, 0, 0 },
9010 0,
9011 Opcode_rsr_ps_encode_fns, 0, 0 },
9013 0,
9014 Opcode_wsr_ps_encode_fns, 0, 0 },
9016 0,
9017 Opcode_xsr_ps_encode_fns, 0, 0 },
9019 0,
9020 Opcode_rsr_epc1_encode_fns, 0, 0 },
9022 0,
9023 Opcode_wsr_epc1_encode_fns, 0, 0 },
9025 0,
9026 Opcode_xsr_epc1_encode_fns, 0, 0 },
9028 0,
9029 Opcode_rsr_excsave1_encode_fns, 0, 0 },
9031 0,
9032 Opcode_wsr_excsave1_encode_fns, 0, 0 },
9034 0,
9035 Opcode_xsr_excsave1_encode_fns, 0, 0 },
9037 0,
9038 Opcode_rsr_epc2_encode_fns, 0, 0 },
9040 0,
9041 Opcode_wsr_epc2_encode_fns, 0, 0 },
9043 0,
9044 Opcode_xsr_epc2_encode_fns, 0, 0 },
9046 0,
9047 Opcode_rsr_excsave2_encode_fns, 0, 0 },
9049 0,
9050 Opcode_wsr_excsave2_encode_fns, 0, 0 },
9052 0,
9053 Opcode_xsr_excsave2_encode_fns, 0, 0 },
9055 0,
9056 Opcode_rsr_epc3_encode_fns, 0, 0 },
9058 0,
9059 Opcode_wsr_epc3_encode_fns, 0, 0 },
9061 0,
9062 Opcode_xsr_epc3_encode_fns, 0, 0 },
9064 0,
9065 Opcode_rsr_excsave3_encode_fns, 0, 0 },
9067 0,
9068 Opcode_wsr_excsave3_encode_fns, 0, 0 },
9070 0,
9071 Opcode_xsr_excsave3_encode_fns, 0, 0 },
9073 0,
9074 Opcode_rsr_epc4_encode_fns, 0, 0 },
9076 0,
9077 Opcode_wsr_epc4_encode_fns, 0, 0 },
9079 0,
9080 Opcode_xsr_epc4_encode_fns, 0, 0 },
9082 0,
9083 Opcode_rsr_excsave4_encode_fns, 0, 0 },
9085 0,
9086 Opcode_wsr_excsave4_encode_fns, 0, 0 },
9088 0,
9089 Opcode_xsr_excsave4_encode_fns, 0, 0 },
9091 0,
9092 Opcode_rsr_epc5_encode_fns, 0, 0 },
9094 0,
9095 Opcode_wsr_epc5_encode_fns, 0, 0 },
9097 0,
9098 Opcode_xsr_epc5_encode_fns, 0, 0 },
9100 0,
9101 Opcode_rsr_excsave5_encode_fns, 0, 0 },
9103 0,
9104 Opcode_wsr_excsave5_encode_fns, 0, 0 },
9106 0,
9107 Opcode_xsr_excsave5_encode_fns, 0, 0 },
9109 0,
9110 Opcode_rsr_epc6_encode_fns, 0, 0 },
9112 0,
9113 Opcode_wsr_epc6_encode_fns, 0, 0 },
9115 0,
9116 Opcode_xsr_epc6_encode_fns, 0, 0 },
9118 0,
9119 Opcode_rsr_excsave6_encode_fns, 0, 0 },
9121 0,
9122 Opcode_wsr_excsave6_encode_fns, 0, 0 },
9124 0,
9125 Opcode_xsr_excsave6_encode_fns, 0, 0 },
9127 0,
9128 Opcode_rsr_epc7_encode_fns, 0, 0 },
9130 0,
9131 Opcode_wsr_epc7_encode_fns, 0, 0 },
9133 0,
9134 Opcode_xsr_epc7_encode_fns, 0, 0 },
9136 0,
9137 Opcode_rsr_excsave7_encode_fns, 0, 0 },
9139 0,
9140 Opcode_wsr_excsave7_encode_fns, 0, 0 },
9142 0,
9143 Opcode_xsr_excsave7_encode_fns, 0, 0 },
9145 0,
9146 Opcode_rsr_eps2_encode_fns, 0, 0 },
9148 0,
9149 Opcode_wsr_eps2_encode_fns, 0, 0 },
9151 0,
9152 Opcode_xsr_eps2_encode_fns, 0, 0 },
9154 0,
9155 Opcode_rsr_eps3_encode_fns, 0, 0 },
9157 0,
9158 Opcode_wsr_eps3_encode_fns, 0, 0 },
9160 0,
9161 Opcode_xsr_eps3_encode_fns, 0, 0 },
9163 0,
9164 Opcode_rsr_eps4_encode_fns, 0, 0 },
9166 0,
9167 Opcode_wsr_eps4_encode_fns, 0, 0 },
9169 0,
9170 Opcode_xsr_eps4_encode_fns, 0, 0 },
9172 0,
9173 Opcode_rsr_eps5_encode_fns, 0, 0 },
9175 0,
9176 Opcode_wsr_eps5_encode_fns, 0, 0 },
9178 0,
9179 Opcode_xsr_eps5_encode_fns, 0, 0 },
9181 0,
9182 Opcode_rsr_eps6_encode_fns, 0, 0 },
9184 0,
9185 Opcode_wsr_eps6_encode_fns, 0, 0 },
9187 0,
9188 Opcode_xsr_eps6_encode_fns, 0, 0 },
9190 0,
9191 Opcode_rsr_eps7_encode_fns, 0, 0 },
9193 0,
9194 Opcode_wsr_eps7_encode_fns, 0, 0 },
9196 0,
9197 Opcode_xsr_eps7_encode_fns, 0, 0 },
9199 0,
9200 Opcode_rsr_excvaddr_encode_fns, 0, 0 },
9202 0,
9203 Opcode_wsr_excvaddr_encode_fns, 0, 0 },
9205 0,
9206 Opcode_xsr_excvaddr_encode_fns, 0, 0 },
9208 0,
9209 Opcode_rsr_depc_encode_fns, 0, 0 },
9211 0,
9212 Opcode_wsr_depc_encode_fns, 0, 0 },
9214 0,
9215 Opcode_xsr_depc_encode_fns, 0, 0 },
9217 0,
9218 Opcode_rsr_exccause_encode_fns, 0, 0 },
9220 0,
9221 Opcode_wsr_exccause_encode_fns, 0, 0 },
9223 0,
9224 Opcode_xsr_exccause_encode_fns, 0, 0 },
9226 0,
9227 Opcode_rsr_misc0_encode_fns, 0, 0 },
9229 0,
9230 Opcode_wsr_misc0_encode_fns, 0, 0 },
9232 0,
9233 Opcode_xsr_misc0_encode_fns, 0, 0 },
9235 0,
9236 Opcode_rsr_misc1_encode_fns, 0, 0 },
9238 0,
9239 Opcode_wsr_misc1_encode_fns, 0, 0 },
9241 0,
9242 Opcode_xsr_misc1_encode_fns, 0, 0 },
9244 0,
9245 Opcode_rsr_prid_encode_fns, 0, 0 },
9247 0,
9248 Opcode_rsr_vecbase_encode_fns, 0, 0 },
9250 0,
9251 Opcode_wsr_vecbase_encode_fns, 0, 0 },
9253 0,
9254 Opcode_xsr_vecbase_encode_fns, 0, 0 },
9256 0,
9257 Opcode_salt_encode_fns, 0, 0 },
9259 0,
9260 Opcode_saltu_encode_fns, 0, 0 },
9262 0,
9263 Opcode_mul16u_encode_fns, 0, 0 },
9265 0,
9266 Opcode_mul16s_encode_fns, 0, 0 },
9268 0,
9269 Opcode_mull_encode_fns, 0, 0 },
9272 Opcode_rfi_encode_fns, 0, 0 },
9274 0,
9275 Opcode_waiti_encode_fns, 0, 0 },
9277 0,
9278 Opcode_rsr_interrupt_encode_fns, 0, 0 },
9280 0,
9281 Opcode_wsr_intset_encode_fns, 0, 0 },
9283 0,
9284 Opcode_wsr_intclear_encode_fns, 0, 0 },
9286 0,
9287 Opcode_rsr_intenable_encode_fns, 0, 0 },
9289 0,
9290 Opcode_wsr_intenable_encode_fns, 0, 0 },
9292 0,
9293 Opcode_xsr_intenable_encode_fns, 0, 0 },
9295 0,
9296 Opcode_break_encode_fns, 0, 0 },
9298 0,
9299 Opcode_break_n_encode_fns, 0, 0 },
9301 0,
9302 Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
9304 0,
9305 Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
9307 0,
9308 Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
9310 0,
9311 Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
9313 0,
9314 Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
9316 0,
9317 Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
9319 0,
9320 Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
9322 0,
9323 Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
9325 0,
9326 Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
9328 0,
9329 Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
9331 0,
9332 Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
9334 0,
9335 Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
9337 0,
9338 Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
9340 0,
9341 Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
9343 0,
9344 Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
9346 0,
9347 Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
9349 0,
9350 Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
9352 0,
9353 Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
9355 0,
9356 Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
9358 0,
9359 Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
9361 0,
9362 Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
9364 0,
9365 Opcode_rsr_debugcause_encode_fns, 0, 0 },
9367 0,
9368 Opcode_wsr_debugcause_encode_fns, 0, 0 },
9370 0,
9371 Opcode_xsr_debugcause_encode_fns, 0, 0 },
9373 0,
9374 Opcode_rsr_icount_encode_fns, 0, 0 },
9376 0,
9377 Opcode_wsr_icount_encode_fns, 0, 0 },
9379 0,
9380 Opcode_xsr_icount_encode_fns, 0, 0 },
9382 0,
9383 Opcode_rsr_icountlevel_encode_fns, 0, 0 },
9385 0,
9386 Opcode_wsr_icountlevel_encode_fns, 0, 0 },
9388 0,
9389 Opcode_xsr_icountlevel_encode_fns, 0, 0 },
9391 0,
9392 Opcode_rsr_ddr_encode_fns, 0, 0 },
9394 0,
9395 Opcode_wsr_ddr_encode_fns, 0, 0 },
9397 0,
9398 Opcode_xsr_ddr_encode_fns, 0, 0 },
9400 0,
9401 Opcode_lddr32_p_encode_fns, 0, 0 },
9403 0,
9404 Opcode_sddr32_p_encode_fns, 0, 0 },
9407 Opcode_rfdo_encode_fns, 0, 0 },
9410 Opcode_rfdd_encode_fns, 0, 0 },
9412 0,
9413 Opcode_wsr_mmid_encode_fns, 0, 0 },
9415 0,
9416 Opcode_rsr_ccount_encode_fns, 0, 0 },
9418 0,
9419 Opcode_wsr_ccount_encode_fns, 0, 0 },
9421 0,
9422 Opcode_xsr_ccount_encode_fns, 0, 0 },
9424 0,
9425 Opcode_rsr_ccompare0_encode_fns, 0, 0 },
9427 0,
9428 Opcode_wsr_ccompare0_encode_fns, 0, 0 },
9430 0,
9431 Opcode_xsr_ccompare0_encode_fns, 0, 0 },
9433 0,
9434 Opcode_rsr_ccompare1_encode_fns, 0, 0 },
9436 0,
9437 Opcode_wsr_ccompare1_encode_fns, 0, 0 },
9439 0,
9440 Opcode_xsr_ccompare1_encode_fns, 0, 0 },
9442 0,
9443 Opcode_rsr_ccompare2_encode_fns, 0, 0 },
9445 0,
9446 Opcode_wsr_ccompare2_encode_fns, 0, 0 },
9448 0,
9449 Opcode_xsr_ccompare2_encode_fns, 0, 0 },
9451 0,
9452 Opcode_idtlb_encode_fns, 0, 0 },
9454 0,
9455 Opcode_pdtlb_encode_fns, 0, 0 },
9457 0,
9458 Opcode_rdtlb0_encode_fns, 0, 0 },
9460 0,
9461 Opcode_rdtlb1_encode_fns, 0, 0 },
9463 0,
9464 Opcode_wdtlb_encode_fns, 0, 0 },
9466 0,
9467 Opcode_iitlb_encode_fns, 0, 0 },
9469 0,
9470 Opcode_pitlb_encode_fns, 0, 0 },
9472 0,
9473 Opcode_ritlb0_encode_fns, 0, 0 },
9475 0,
9476 Opcode_ritlb1_encode_fns, 0, 0 },
9478 0,
9479 Opcode_witlb_encode_fns, 0, 0 },
9481 0,
9482 Opcode_min_encode_fns, 0, 0 },
9484 0,
9485 Opcode_max_encode_fns, 0, 0 },
9487 0,
9488 Opcode_minu_encode_fns, 0, 0 },
9490 0,
9491 Opcode_maxu_encode_fns, 0, 0 },
9493 0,
9494 Opcode_nsa_encode_fns, 0, 0 },
9496 0,
9497 Opcode_nsau_encode_fns, 0, 0 },
9499 0,
9500 Opcode_sext_encode_fns, 0, 0 },
9502 0,
9503 Opcode_l32ai_encode_fns, 0, 0 },
9505 0,
9506 Opcode_s32ri_encode_fns, 0, 0 },
9508 0,
9509 Opcode_s32c1i_encode_fns, 0, 0 },
9511 0,
9512 Opcode_rsr_scompare1_encode_fns, 0, 0 },
9514 0,
9515 Opcode_wsr_scompare1_encode_fns, 0, 0 },
9517 0,
9518 Opcode_xsr_scompare1_encode_fns, 0, 0 },
9520 0,
9521 Opcode_rsr_atomctl_encode_fns, 0, 0 },
9523 0,
9524 Opcode_wsr_atomctl_encode_fns, 0, 0 },
9526 0,
9527 Opcode_xsr_atomctl_encode_fns, 0, 0 },
9529 0,
9530 Opcode_quou_encode_fns, 0, 0 },
9532 0,
9533 Opcode_quos_encode_fns, 0, 0 },
9535 0,
9536 Opcode_remu_encode_fns, 0, 0 },
9538 0,
9539 Opcode_rems_encode_fns, 0, 0 },
9541 0,
9542 Opcode_rsr_eraccess_encode_fns, 0, 0 },
9544 0,
9545 Opcode_wsr_eraccess_encode_fns, 0, 0 },
9547 0,
9548 Opcode_xsr_eraccess_encode_fns, 0, 0 },
9550 0,
9551 Opcode_rer_encode_fns, 0, 0 },
9553 0,
9554 Opcode_wer_encode_fns, 0, 0 },
9556 0,
9557 Opcode_rur_expstate_encode_fns, 0, 0 },
9559 0,
9560 Opcode_wur_expstate_encode_fns, 0, 0 },
9562 0,
9563 Opcode_read_impwire_encode_fns, 0, 0 },
9565 0,
9566 Opcode_setb_expstate_encode_fns, 0, 0 },
9568 0,
9569 Opcode_clrb_expstate_encode_fns, 0, 0 },
9571 0,
9572 Opcode_wrmsk_expstate_encode_fns, 0, 0 }
9901 if (Field_op0_Slot_inst_get (insn) == 0)
9903 if (Field_op1_Slot_inst_get (insn) == 0)
9905 if (Field_op2_Slot_inst_get (insn) == 0)
9907 if (Field_r_Slot_inst_get (insn) == 0)
9909 if (Field_m_Slot_inst_get (insn) == 0 &&
9910 Field_s_Slot_inst_get (insn) == 0 &&
9911 Field_n_Slot_inst_get (insn) == 0)
9915 if (Field_n_Slot_inst_get (insn) == 0)
9924 if (Field_n_Slot_inst_get (insn) == 0)
9938 if (Field_s_Slot_inst_get (insn) == 0)
9940 if (Field_t_Slot_inst_get (insn) == 0)
9960 if (Field_t_Slot_inst_get (insn) == 0)
9962 if (Field_s_Slot_inst_get (insn) == 0)
9978 if (Field_s_Slot_inst_get (insn) == 0 &&
9979 Field_t_Slot_inst_get (insn) == 0)
9982 Field_t_Slot_inst_get (insn) == 0)
9988 Field_t_Slot_inst_get (insn) == 0)
10006 if (Field_r_Slot_inst_get (insn) == 0 &&
10007 Field_t_Slot_inst_get (insn) == 0)
10010 Field_t_Slot_inst_get (insn) == 0)
10013 Field_t_Slot_inst_get (insn) == 0)
10016 Field_t_Slot_inst_get (insn) == 0)
10019 Field_thi3_Slot_inst_get (insn) == 0)
10026 Field_s_Slot_inst_get (insn) == 0)
10038 Field_t_Slot_inst_get (insn) == 0)
10049 Field_t_Slot_inst_get (insn) == 0)
10060 if (Field_s_Slot_inst_get (insn) == 0)
10084 if ((Field_op2_Slot_inst_get (insn) == 0 ||
10200 Field_s_Slot_inst_get (insn) == 0)
10203 Field_t_Slot_inst_get (insn) == 0)
10206 Field_s_Slot_inst_get (insn) == 0)
10215 Field_t_Slot_inst_get (insn) == 0)
10241 if (Field_op2_Slot_inst_get (insn) == 0)
10501 if (Field_op2_Slot_inst_get (insn) == 0)
10508 if (Field_r_Slot_inst_get (insn) == 0 &&
10509 Field_s_Slot_inst_get (insn) == 0 &&
10510 Field_op2_Slot_inst_get (insn) == 0 &&
10514 Field_s3to1_Slot_inst_get (insn) == 0 &&
10515 Field_op2_Slot_inst_get (insn) == 0 &&
10520 Field_op2_Slot_inst_get (insn) == 0 &&
10524 Field_op2_Slot_inst_get (insn) == 0 &&
10532 if (Field_r_Slot_inst_get (insn) == 0)
10561 if (Field_n_Slot_inst_get (insn) == 0)
10572 if (Field_n_Slot_inst_get (insn) == 0)
10576 if (Field_m_Slot_inst_get (insn) == 0)
10587 if (Field_m_Slot_inst_get (insn) == 0)
10598 if (Field_m_Slot_inst_get (insn) == 0)
10608 if (Field_r_Slot_inst_get (insn) == 0)
10647 if (Field_i_Slot_inst16b_get (insn) == 0)
10651 if (Field_z_Slot_inst16b_get (insn) == 0)
10659 if (Field_r_Slot_inst16b_get (insn) == 0)
10663 if (Field_t_Slot_inst16b_get (insn) == 0)
10670 Field_s_Slot_inst16b_get (insn) == 0)
10673 Field_s_Slot_inst16b_get (insn) == 0)
10701 slotbuf[0] = (insn[0] & 0xffffff);
10708 insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
10715 slotbuf[0] = (insn[0] & 0xffff);
10722 insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
10729 slotbuf[0] = (insn[0] & 0xffff);
10736 insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
10768 0,
10769 0,
10770 0,
10771 0,
10772 0,
10773 0,
10774 0,
10775 0,
10815 0,
10816 0,
10817 0,
10818 0,
10819 0,
10820 0,
10821 0,
10822 0,
10836 0,
10837 0,
10838 0,
10839 0,
10841 0,
10842 0,
10843 0,
10844 0,
10845 0,
10847 0,
10848 0,
10850 0,
10851 0,
10852 0,
10853 0,
10854 0,
10855 0,
10856 0,
10859 0,
10861 0,
10870 0,
10871 0,
10883 0,
10884 0,
10885 0,
10886 0,
10888 0,
10889 0,
10890 0,
10891 0,
10892 0,
10894 0,
10895 0,
10897 0,
10898 0,
10899 0,
10900 0,
10901 0,
10902 0,
10903 0,
10906 0,
10908 0,
10917 0,
10918 0,
10930 0,
10931 0,
10932 0,
10933 0,
10935 0,
10936 0,
10937 0,
10938 0,
10939 0,
10941 0,
10942 0,
10944 0,
10945 0,
10946 0,
10947 0,
10948 0,
10949 0,
10950 0,
10953 0,
10955 0,
10964 0,
10965 0,
10977 0,
10978 0,
10979 0,
10980 0,
10982 0,
10983 0,
10984 0,
10985 0,
10986 0,
10988 0,
10989 0,
10991 0,
10992 0,
10993 0,
10994 0,
10995 0,
10996 0,
10997 0,
11000 0,
11002 0,
11011 0,
11012 0,
11022 { "Inst", "x24", 0,
11026 { "Inst16a", "x16a", 0,
11030 { "Inst16b", "x16b", 0,
11042 insn[0] = 0;
11048 insn[0] = 0x8;
11054 insn[0] = 0xc;
11057 static int Format_x24_slots[] = { 0 };
11073 if ((insn[0] & 0x8) == 0)
11074 return 0; /* x24 */
11075 if ((insn[0] & 0xc) == 0x8)
11077 if ((insn[0] & 0xe) == 0xc)
11344 int l = insn[0];
11352 0 /* little-endian */,
11353 3 /* insn_size */, 0,
11359 317, opcodes, 0,
11361 NUM_STATES, states, 0,
11362 NUM_SYSREGS, sysregs, 0,
11363 { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
11364 1, interfaces, 0,
11365 0, funcUnits, 0