1a01822e9SManivannan Sadhasivam# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 2a01822e9SManivannan Sadhasivam%YAML 1.2 3a01822e9SManivannan Sadhasivam--- 4a01822e9SManivannan Sadhasivam$id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml# 5a01822e9SManivannan Sadhasivam$schema: http://devicetree.org/meta-schemas/core.yaml# 6a01822e9SManivannan Sadhasivam 7a01822e9SManivannan Sadhasivamtitle: Qualcomm Technologies, Inc. Inter-Processor Communication Controller 8a01822e9SManivannan Sadhasivam 9a01822e9SManivannan Sadhasivammaintainers: 10a01822e9SManivannan Sadhasivam - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 11a01822e9SManivannan Sadhasivam 12a01822e9SManivannan Sadhasivamdescription: 13a01822e9SManivannan Sadhasivam The Inter-Processor Communication Controller (IPCC) is a centralized hardware 14a01822e9SManivannan Sadhasivam to route interrupts across various subsystems. It involves a three-level 15a01822e9SManivannan Sadhasivam addressing scheme called protocol, client and signal. For example, consider an 16a01822e9SManivannan Sadhasivam entity on the Application Processor Subsystem (APSS) that wants to listen to 17a01822e9SManivannan Sadhasivam Modem's interrupts via Shared Memory Point to Point (SMP2P) interface. In such 18a01822e9SManivannan Sadhasivam a case, the client would be Modem (client-id is 2) and the signal would be 19a01822e9SManivannan Sadhasivam SMP2P (signal-id is 2). The SMP2P itself falls under the Multiprocessor (MPROC) 20a01822e9SManivannan Sadhasivam protocol (protocol-id is 0). Refer include/dt-bindings/mailbox/qcom-ipcc.h 21a01822e9SManivannan Sadhasivam for the list of such IDs. 22a01822e9SManivannan Sadhasivam 23a01822e9SManivannan Sadhasivamproperties: 24a01822e9SManivannan Sadhasivam compatible: 25a01822e9SManivannan Sadhasivam items: 26a01822e9SManivannan Sadhasivam - enum: 27*6ccbe33aSMelody Olvera - qcom,qdu1000-ipcc 28c31508c5SBartosz Golaszewski - qcom,sa8775p-ipcc 2976f708f6SLuca Weiss - qcom,sc7280-ipcc 3076f708f6SLuca Weiss - qcom,sc8280xp-ipcc 31fb339971SKonrad Dybcio - qcom,sm6350-ipcc 321a607e10SKonrad Dybcio - qcom,sm6375-ipcc 33a01822e9SManivannan Sadhasivam - qcom,sm8250-ipcc 342a7db0d6SVinod Koul - qcom,sm8350-ipcc 35897c6756SDavid Heidelberg - qcom,sm8450-ipcc 3653c60d10SAbel Vesa - qcom,sm8550-ipcc 37a01822e9SManivannan Sadhasivam - const: qcom,ipcc 38a01822e9SManivannan Sadhasivam 39a01822e9SManivannan Sadhasivam reg: 40a01822e9SManivannan Sadhasivam maxItems: 1 41a01822e9SManivannan Sadhasivam 42a01822e9SManivannan Sadhasivam interrupts: 43a01822e9SManivannan Sadhasivam maxItems: 1 44a01822e9SManivannan Sadhasivam 45a01822e9SManivannan Sadhasivam interrupt-controller: true 46a01822e9SManivannan Sadhasivam 47a01822e9SManivannan Sadhasivam "#interrupt-cells": 48a01822e9SManivannan Sadhasivam const: 3 49a01822e9SManivannan Sadhasivam description: 50a01822e9SManivannan Sadhasivam The first cell is the client-id, the second cell is the signal-id and the 51a01822e9SManivannan Sadhasivam third cell is the interrupt type. 52a01822e9SManivannan Sadhasivam 53a01822e9SManivannan Sadhasivam "#mbox-cells": 54a01822e9SManivannan Sadhasivam const: 2 55a01822e9SManivannan Sadhasivam description: 56a01822e9SManivannan Sadhasivam The first cell is the client-id, and the second cell is the signal-id. 57a01822e9SManivannan Sadhasivam 58a01822e9SManivannan Sadhasivamrequired: 59a01822e9SManivannan Sadhasivam - compatible 60a01822e9SManivannan Sadhasivam - reg 61a01822e9SManivannan Sadhasivam - interrupts 62a01822e9SManivannan Sadhasivam - interrupt-controller 63a01822e9SManivannan Sadhasivam - "#interrupt-cells" 64a01822e9SManivannan Sadhasivam - "#mbox-cells" 65a01822e9SManivannan Sadhasivam 66a01822e9SManivannan SadhasivamadditionalProperties: false 67a01822e9SManivannan Sadhasivam 68a01822e9SManivannan Sadhasivamexamples: 69a01822e9SManivannan Sadhasivam - | 70a01822e9SManivannan Sadhasivam #include <dt-bindings/interrupt-controller/arm-gic.h> 71a01822e9SManivannan Sadhasivam #include <dt-bindings/mailbox/qcom-ipcc.h> 72a01822e9SManivannan Sadhasivam 73a01822e9SManivannan Sadhasivam mailbox@408000 { 74a01822e9SManivannan Sadhasivam compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 75a01822e9SManivannan Sadhasivam reg = <0x408000 0x1000>; 76a01822e9SManivannan Sadhasivam interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 77a01822e9SManivannan Sadhasivam interrupt-controller; 78a01822e9SManivannan Sadhasivam #interrupt-cells = <3>; 79a01822e9SManivannan Sadhasivam #mbox-cells = <2>; 80a01822e9SManivannan Sadhasivam }; 81