1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 28945e37eSKevin Cernekee/ { 38945e37eSKevin Cernekee #address-cells = <1>; 48945e37eSKevin Cernekee #size-cells = <1>; 58945e37eSKevin Cernekee compatible = "brcm,bcm7346"; 68945e37eSKevin Cernekee 78945e37eSKevin Cernekee cpus { 88945e37eSKevin Cernekee #address-cells = <1>; 98945e37eSKevin Cernekee #size-cells = <0>; 108945e37eSKevin Cernekee 118945e37eSKevin Cernekee mips-hpt-frequency = <163125000>; 128945e37eSKevin Cernekee 138945e37eSKevin Cernekee cpu@0 { 148945e37eSKevin Cernekee compatible = "brcm,bmips5000"; 158945e37eSKevin Cernekee device_type = "cpu"; 168945e37eSKevin Cernekee reg = <0>; 178945e37eSKevin Cernekee }; 188945e37eSKevin Cernekee 198945e37eSKevin Cernekee cpu@1 { 208945e37eSKevin Cernekee compatible = "brcm,bmips5000"; 218945e37eSKevin Cernekee device_type = "cpu"; 228945e37eSKevin Cernekee reg = <1>; 238945e37eSKevin Cernekee }; 248945e37eSKevin Cernekee }; 258945e37eSKevin Cernekee 268945e37eSKevin Cernekee aliases { 278945e37eSKevin Cernekee uart0 = &uart0; 288945e37eSKevin Cernekee }; 298945e37eSKevin Cernekee 30a2c510a2SJaedon Shin cpu_intc: interrupt-controller { 318945e37eSKevin Cernekee #address-cells = <0>; 328945e37eSKevin Cernekee compatible = "mti,cpu-interrupt-controller"; 338945e37eSKevin Cernekee 348945e37eSKevin Cernekee interrupt-controller; 358945e37eSKevin Cernekee #interrupt-cells = <1>; 368945e37eSKevin Cernekee }; 378945e37eSKevin Cernekee 388945e37eSKevin Cernekee clocks { 398945e37eSKevin Cernekee uart_clk: uart_clk { 408945e37eSKevin Cernekee compatible = "fixed-clock"; 418945e37eSKevin Cernekee #clock-cells = <0>; 428945e37eSKevin Cernekee clock-frequency = <81000000>; 438945e37eSKevin Cernekee }; 447bbe59ddSJaedon Shin 457bbe59ddSJaedon Shin upg_clk: upg_clk { 467bbe59ddSJaedon Shin compatible = "fixed-clock"; 477bbe59ddSJaedon Shin #clock-cells = <0>; 487bbe59ddSJaedon Shin clock-frequency = <27000000>; 497bbe59ddSJaedon Shin }; 508945e37eSKevin Cernekee }; 518945e37eSKevin Cernekee 528945e37eSKevin Cernekee rdb { 538945e37eSKevin Cernekee #address-cells = <1>; 548945e37eSKevin Cernekee #size-cells = <1>; 558945e37eSKevin Cernekee 568945e37eSKevin Cernekee compatible = "simple-bus"; 578945e37eSKevin Cernekee ranges = <0 0x10000000 0x01000000>; 588945e37eSKevin Cernekee 59a2c510a2SJaedon Shin periph_intc: interrupt-controller@411400 { 608945e37eSKevin Cernekee compatible = "brcm,bcm7038-l1-intc"; 618945e37eSKevin Cernekee reg = <0x411400 0x30>, <0x411600 0x30>; 628945e37eSKevin Cernekee 638945e37eSKevin Cernekee interrupt-controller; 648945e37eSKevin Cernekee #interrupt-cells = <1>; 658945e37eSKevin Cernekee 668945e37eSKevin Cernekee interrupt-parent = <&cpu_intc>; 678945e37eSKevin Cernekee interrupts = <2>, <3>; 688945e37eSKevin Cernekee }; 698945e37eSKevin Cernekee 70a2c510a2SJaedon Shin sun_l2_intc: interrupt-controller@403000 { 718945e37eSKevin Cernekee compatible = "brcm,l2-intc"; 728945e37eSKevin Cernekee reg = <0x403000 0x30>; 738945e37eSKevin Cernekee interrupt-controller; 748945e37eSKevin Cernekee #interrupt-cells = <1>; 758945e37eSKevin Cernekee interrupt-parent = <&periph_intc>; 768945e37eSKevin Cernekee interrupts = <51>; 778945e37eSKevin Cernekee }; 788945e37eSKevin Cernekee 798945e37eSKevin Cernekee gisb-arb@400000 { 808945e37eSKevin Cernekee compatible = "brcm,bcm7400-gisb-arb"; 818945e37eSKevin Cernekee reg = <0x400000 0xdc>; 828945e37eSKevin Cernekee native-endian; 838945e37eSKevin Cernekee interrupt-parent = <&sun_l2_intc>; 848945e37eSKevin Cernekee interrupts = <0>, <2>; 858945e37eSKevin Cernekee brcm,gisb-arb-master-mask = <0x673>; 868945e37eSKevin Cernekee brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0", 878945e37eSKevin Cernekee "rdc_0", "raaga_0", 888945e37eSKevin Cernekee "jtag_0", "svd_0"; 898945e37eSKevin Cernekee }; 908945e37eSKevin Cernekee 91a2c510a2SJaedon Shin upg_irq0_intc: interrupt-controller@406780 { 928945e37eSKevin Cernekee compatible = "brcm,bcm7120-l2-intc"; 938945e37eSKevin Cernekee reg = <0x406780 0x8>; 948945e37eSKevin Cernekee 9539d9b6b2SJaedon Shin brcm,int-map-mask = <0x44>, <0xf000000>; 968945e37eSKevin Cernekee brcm,int-fwd-mask = <0x70000>; 978945e37eSKevin Cernekee 988945e37eSKevin Cernekee interrupt-controller; 998945e37eSKevin Cernekee #interrupt-cells = <1>; 1008945e37eSKevin Cernekee 1018945e37eSKevin Cernekee interrupt-parent = <&periph_intc>; 10239d9b6b2SJaedon Shin interrupts = <59>, <57>; 10339d9b6b2SJaedon Shin interrupt-names = "upg_main", "upg_bsc"; 10439d9b6b2SJaedon Shin }; 10539d9b6b2SJaedon Shin 106a2c510a2SJaedon Shin upg_aon_irq0_intc: interrupt-controller@408b80 { 10739d9b6b2SJaedon Shin compatible = "brcm,bcm7120-l2-intc"; 10839d9b6b2SJaedon Shin reg = <0x408b80 0x8>; 10939d9b6b2SJaedon Shin 11039d9b6b2SJaedon Shin brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>; 11139d9b6b2SJaedon Shin brcm,int-fwd-mask = <0>; 11239d9b6b2SJaedon Shin brcm,irq-can-wake; 11339d9b6b2SJaedon Shin 11439d9b6b2SJaedon Shin interrupt-controller; 11539d9b6b2SJaedon Shin #interrupt-cells = <1>; 11639d9b6b2SJaedon Shin 11739d9b6b2SJaedon Shin interrupt-parent = <&periph_intc>; 11839d9b6b2SJaedon Shin interrupts = <60>, <58>, <62>; 11939d9b6b2SJaedon Shin interrupt-names = "upg_main_aon", "upg_bsc_aon", 12039d9b6b2SJaedon Shin "upg_spi"; 1218945e37eSKevin Cernekee }; 1228945e37eSKevin Cernekee 1238945e37eSKevin Cernekee sun_top_ctrl: syscon@404000 { 1248945e37eSKevin Cernekee compatible = "brcm,bcm7346-sun-top-ctrl", "syscon"; 1258945e37eSKevin Cernekee reg = <0x404000 0x51c>; 12625d6463eSMark Brown native-endian; 1278945e37eSKevin Cernekee }; 1288945e37eSKevin Cernekee 1298945e37eSKevin Cernekee reboot { 1308945e37eSKevin Cernekee compatible = "brcm,brcmstb-reboot"; 1318945e37eSKevin Cernekee syscon = <&sun_top_ctrl 0x304 0x308>; 1328945e37eSKevin Cernekee }; 1338945e37eSKevin Cernekee 1348945e37eSKevin Cernekee uart0: serial@406900 { 1358945e37eSKevin Cernekee compatible = "ns16550a"; 1368945e37eSKevin Cernekee reg = <0x406900 0x20>; 1378945e37eSKevin Cernekee reg-io-width = <0x4>; 1388945e37eSKevin Cernekee reg-shift = <0x2>; 1398945e37eSKevin Cernekee native-endian; 1408945e37eSKevin Cernekee interrupt-parent = <&periph_intc>; 1418945e37eSKevin Cernekee interrupts = <64>; 1428945e37eSKevin Cernekee clocks = <&uart_clk>; 1438945e37eSKevin Cernekee status = "disabled"; 1448945e37eSKevin Cernekee }; 1458945e37eSKevin Cernekee 1468bac078cSJaedon Shin uart1: serial@406940 { 1478bac078cSJaedon Shin compatible = "ns16550a"; 1488bac078cSJaedon Shin reg = <0x406940 0x20>; 1498bac078cSJaedon Shin reg-io-width = <0x4>; 1508bac078cSJaedon Shin reg-shift = <0x2>; 1518bac078cSJaedon Shin native-endian; 1528bac078cSJaedon Shin interrupt-parent = <&periph_intc>; 1538bac078cSJaedon Shin interrupts = <65>; 1548bac078cSJaedon Shin clocks = <&uart_clk>; 1558bac078cSJaedon Shin status = "disabled"; 1568bac078cSJaedon Shin }; 1578bac078cSJaedon Shin 1588bac078cSJaedon Shin uart2: serial@406980 { 1598bac078cSJaedon Shin compatible = "ns16550a"; 1608bac078cSJaedon Shin reg = <0x406980 0x20>; 1618bac078cSJaedon Shin reg-io-width = <0x4>; 1628bac078cSJaedon Shin reg-shift = <0x2>; 1638bac078cSJaedon Shin native-endian; 1648bac078cSJaedon Shin interrupt-parent = <&periph_intc>; 1658bac078cSJaedon Shin interrupts = <66>; 1668bac078cSJaedon Shin clocks = <&uart_clk>; 1678bac078cSJaedon Shin status = "disabled"; 1688bac078cSJaedon Shin }; 1698bac078cSJaedon Shin 17039d9b6b2SJaedon Shin bsca: i2c@406200 { 17139d9b6b2SJaedon Shin clock-frequency = <390000>; 17239d9b6b2SJaedon Shin compatible = "brcm,brcmstb-i2c"; 17339d9b6b2SJaedon Shin interrupt-parent = <&upg_irq0_intc>; 17439d9b6b2SJaedon Shin reg = <0x406200 0x58>; 17539d9b6b2SJaedon Shin interrupts = <24>; 17639d9b6b2SJaedon Shin interrupt-names = "upg_bsca"; 17739d9b6b2SJaedon Shin status = "disabled"; 17839d9b6b2SJaedon Shin }; 17939d9b6b2SJaedon Shin 18039d9b6b2SJaedon Shin bscb: i2c@406280 { 18139d9b6b2SJaedon Shin clock-frequency = <390000>; 18239d9b6b2SJaedon Shin compatible = "brcm,brcmstb-i2c"; 18339d9b6b2SJaedon Shin interrupt-parent = <&upg_irq0_intc>; 18439d9b6b2SJaedon Shin reg = <0x406280 0x58>; 18539d9b6b2SJaedon Shin interrupts = <25>; 18639d9b6b2SJaedon Shin interrupt-names = "upg_bscb"; 18739d9b6b2SJaedon Shin status = "disabled"; 18839d9b6b2SJaedon Shin }; 18939d9b6b2SJaedon Shin 19039d9b6b2SJaedon Shin bscc: i2c@406300 { 19139d9b6b2SJaedon Shin clock-frequency = <390000>; 19239d9b6b2SJaedon Shin compatible = "brcm,brcmstb-i2c"; 19339d9b6b2SJaedon Shin interrupt-parent = <&upg_irq0_intc>; 19439d9b6b2SJaedon Shin reg = <0x406300 0x58>; 19539d9b6b2SJaedon Shin interrupts = <26>; 19639d9b6b2SJaedon Shin interrupt-names = "upg_bscc"; 19739d9b6b2SJaedon Shin status = "disabled"; 19839d9b6b2SJaedon Shin }; 19939d9b6b2SJaedon Shin 20039d9b6b2SJaedon Shin bscd: i2c@406380 { 20139d9b6b2SJaedon Shin clock-frequency = <390000>; 20239d9b6b2SJaedon Shin compatible = "brcm,brcmstb-i2c"; 20339d9b6b2SJaedon Shin interrupt-parent = <&upg_irq0_intc>; 20439d9b6b2SJaedon Shin reg = <0x406380 0x58>; 20539d9b6b2SJaedon Shin interrupts = <27>; 20639d9b6b2SJaedon Shin interrupt-names = "upg_bscd"; 20739d9b6b2SJaedon Shin status = "disabled"; 20839d9b6b2SJaedon Shin }; 20939d9b6b2SJaedon Shin 21039d9b6b2SJaedon Shin bsce: i2c@408980 { 21139d9b6b2SJaedon Shin clock-frequency = <390000>; 21239d9b6b2SJaedon Shin compatible = "brcm,brcmstb-i2c"; 21339d9b6b2SJaedon Shin interrupt-parent = <&upg_aon_irq0_intc>; 21439d9b6b2SJaedon Shin reg = <0x408980 0x58>; 21539d9b6b2SJaedon Shin interrupts = <27>; 21639d9b6b2SJaedon Shin interrupt-names = "upg_bsce"; 21739d9b6b2SJaedon Shin status = "disabled"; 21839d9b6b2SJaedon Shin }; 21939d9b6b2SJaedon Shin 2207bbe59ddSJaedon Shin pwma: pwm@406580 { 2217bbe59ddSJaedon Shin compatible = "brcm,bcm7038-pwm"; 2227bbe59ddSJaedon Shin reg = <0x406580 0x28>; 2237bbe59ddSJaedon Shin #pwm-cells = <2>; 2247bbe59ddSJaedon Shin clocks = <&upg_clk>; 2257bbe59ddSJaedon Shin status = "disabled"; 2267bbe59ddSJaedon Shin }; 2277bbe59ddSJaedon Shin 2287bbe59ddSJaedon Shin pwmb: pwm@406800 { 2297bbe59ddSJaedon Shin compatible = "brcm,bcm7038-pwm"; 2307bbe59ddSJaedon Shin reg = <0x406800 0x28>; 2317bbe59ddSJaedon Shin #pwm-cells = <2>; 2327bbe59ddSJaedon Shin clocks = <&upg_clk>; 2337bbe59ddSJaedon Shin status = "disabled"; 2347bbe59ddSJaedon Shin }; 2357bbe59ddSJaedon Shin 236b68c2575SJaedon Shin watchdog: watchdog@4067e8 { 237b68c2575SJaedon Shin clocks = <&upg_clk>; 238b68c2575SJaedon Shin compatible = "brcm,bcm7038-wdt"; 239b68c2575SJaedon Shin reg = <0x4067e8 0x14>; 240b68c2575SJaedon Shin status = "disabled"; 241b68c2575SJaedon Shin }; 242b68c2575SJaedon Shin 243c707844dSJaedon Shin aon_pm_l2_intc: interrupt-controller@408440 { 244c707844dSJaedon Shin compatible = "brcm,l2-intc"; 245c707844dSJaedon Shin reg = <0x408440 0x30>; 246c707844dSJaedon Shin interrupt-controller; 247c707844dSJaedon Shin #interrupt-cells = <1>; 248c707844dSJaedon Shin interrupt-parent = <&periph_intc>; 249c707844dSJaedon Shin interrupts = <53>; 250c707844dSJaedon Shin brcm,irq-can-wake; 251c707844dSJaedon Shin }; 252c707844dSJaedon Shin 253c7146a2bSJaedon Shin aon_ctrl: syscon@408000 { 254c7146a2bSJaedon Shin compatible = "brcm,brcmstb-aon-ctrl"; 255c7146a2bSJaedon Shin reg = <0x408000 0x100>, <0x408200 0x200>; 256c7146a2bSJaedon Shin reg-names = "aon-ctrl", "aon-sram"; 257c7146a2bSJaedon Shin }; 258c7146a2bSJaedon Shin 259c7146a2bSJaedon Shin timers: timer@4067c0 { 260c7146a2bSJaedon Shin compatible = "brcm,brcmstb-timers"; 261c7146a2bSJaedon Shin reg = <0x4067c0 0x40>; 262c7146a2bSJaedon Shin }; 263c7146a2bSJaedon Shin 264c707844dSJaedon Shin upg_gio: gpio@406700 { 265c707844dSJaedon Shin compatible = "brcm,brcmstb-gpio"; 266c707844dSJaedon Shin reg = <0x406700 0x60>; 267c707844dSJaedon Shin #gpio-cells = <2>; 268c707844dSJaedon Shin #interrupt-cells = <2>; 269c707844dSJaedon Shin gpio-controller; 270c707844dSJaedon Shin interrupt-controller; 271c707844dSJaedon Shin interrupt-parent = <&upg_irq0_intc>; 272c707844dSJaedon Shin interrupts = <6>; 273c707844dSJaedon Shin brcm,gpio-bank-widths = <32 32 16>; 274c707844dSJaedon Shin }; 275c707844dSJaedon Shin 276c707844dSJaedon Shin upg_gio_aon: gpio@408c00 { 277c707844dSJaedon Shin compatible = "brcm,brcmstb-gpio"; 278c707844dSJaedon Shin reg = <0x408c00 0x60>; 279c707844dSJaedon Shin #gpio-cells = <2>; 280c707844dSJaedon Shin #interrupt-cells = <2>; 281c707844dSJaedon Shin gpio-controller; 282c707844dSJaedon Shin interrupt-controller; 283c707844dSJaedon Shin interrupt-parent = <&upg_aon_irq0_intc>; 284c707844dSJaedon Shin interrupts = <6>; 285c707844dSJaedon Shin interrupts-extended = <&upg_aon_irq0_intc 6>, 286c707844dSJaedon Shin <&aon_pm_l2_intc 5>; 287c707844dSJaedon Shin wakeup-source; 288c707844dSJaedon Shin brcm,gpio-bank-widths = <27 32 2>; 289c707844dSJaedon Shin }; 290c707844dSJaedon Shin 2918945e37eSKevin Cernekee enet0: ethernet@430000 { 2928945e37eSKevin Cernekee phy-mode = "internal"; 2938945e37eSKevin Cernekee phy-handle = <&phy1>; 2948945e37eSKevin Cernekee mac-address = [ 00 10 18 36 23 1a ]; 2958945e37eSKevin Cernekee compatible = "brcm,genet-v2"; 2968945e37eSKevin Cernekee #address-cells = <0x1>; 2978945e37eSKevin Cernekee #size-cells = <0x1>; 2988945e37eSKevin Cernekee reg = <0x430000 0x4c8c>; 2998945e37eSKevin Cernekee interrupts = <24>, <25>; 3008945e37eSKevin Cernekee interrupt-parent = <&periph_intc>; 3018945e37eSKevin Cernekee status = "disabled"; 3028945e37eSKevin Cernekee 3038945e37eSKevin Cernekee mdio@e14 { 3048945e37eSKevin Cernekee compatible = "brcm,genet-mdio-v2"; 3058945e37eSKevin Cernekee #address-cells = <0x1>; 3068945e37eSKevin Cernekee #size-cells = <0x0>; 3078945e37eSKevin Cernekee reg = <0xe14 0x8>; 3088945e37eSKevin Cernekee 3098945e37eSKevin Cernekee phy1: ethernet-phy@1 { 3108945e37eSKevin Cernekee max-speed = <100>; 3118945e37eSKevin Cernekee reg = <0x1>; 3128945e37eSKevin Cernekee compatible = "brcm,40nm-ephy", 3138945e37eSKevin Cernekee "ethernet-phy-ieee802.3-c22"; 3148945e37eSKevin Cernekee }; 3158945e37eSKevin Cernekee }; 3168945e37eSKevin Cernekee }; 3178945e37eSKevin Cernekee 3188945e37eSKevin Cernekee ehci0: usb@480300 { 3198945e37eSKevin Cernekee compatible = "brcm,bcm7346-ehci", "generic-ehci"; 3208945e37eSKevin Cernekee reg = <0x480300 0x100>; 3218945e37eSKevin Cernekee native-endian; 3228945e37eSKevin Cernekee interrupt-parent = <&periph_intc>; 3238945e37eSKevin Cernekee interrupts = <68>; 3248945e37eSKevin Cernekee status = "disabled"; 3258945e37eSKevin Cernekee }; 3268945e37eSKevin Cernekee 3278945e37eSKevin Cernekee ohci0: usb@480400 { 3288945e37eSKevin Cernekee compatible = "brcm,bcm7346-ohci", "generic-ohci"; 3298945e37eSKevin Cernekee reg = <0x480400 0x100>; 3308945e37eSKevin Cernekee native-endian; 3318945e37eSKevin Cernekee no-big-frame-no; 3328945e37eSKevin Cernekee interrupt-parent = <&periph_intc>; 3338945e37eSKevin Cernekee interrupts = <70>; 3348945e37eSKevin Cernekee status = "disabled"; 3358945e37eSKevin Cernekee }; 3368945e37eSKevin Cernekee 3378945e37eSKevin Cernekee ehci1: usb@480500 { 3388945e37eSKevin Cernekee compatible = "brcm,bcm7346-ehci", "generic-ehci"; 3398945e37eSKevin Cernekee reg = <0x480500 0x100>; 3408945e37eSKevin Cernekee native-endian; 3418945e37eSKevin Cernekee interrupt-parent = <&periph_intc>; 3428945e37eSKevin Cernekee interrupts = <69>; 3438945e37eSKevin Cernekee status = "disabled"; 3448945e37eSKevin Cernekee }; 3458945e37eSKevin Cernekee 3468945e37eSKevin Cernekee ohci1: usb@480600 { 3478945e37eSKevin Cernekee compatible = "brcm,bcm7346-ohci", "generic-ohci"; 3488945e37eSKevin Cernekee reg = <0x480600 0x100>; 3498945e37eSKevin Cernekee native-endian; 3508945e37eSKevin Cernekee no-big-frame-no; 3518945e37eSKevin Cernekee interrupt-parent = <&periph_intc>; 3528945e37eSKevin Cernekee interrupts = <71>; 3538945e37eSKevin Cernekee status = "disabled"; 3548945e37eSKevin Cernekee }; 3558945e37eSKevin Cernekee 3568945e37eSKevin Cernekee ehci2: usb@490300 { 3578945e37eSKevin Cernekee compatible = "brcm,bcm7346-ehci", "generic-ehci"; 3588945e37eSKevin Cernekee reg = <0x490300 0x100>; 3598945e37eSKevin Cernekee native-endian; 3608945e37eSKevin Cernekee interrupt-parent = <&periph_intc>; 3618945e37eSKevin Cernekee interrupts = <73>; 3628945e37eSKevin Cernekee status = "disabled"; 3638945e37eSKevin Cernekee }; 3648945e37eSKevin Cernekee 3658945e37eSKevin Cernekee ohci2: usb@490400 { 3668945e37eSKevin Cernekee compatible = "brcm,bcm7346-ohci", "generic-ohci"; 3678945e37eSKevin Cernekee reg = <0x490400 0x100>; 3688945e37eSKevin Cernekee native-endian; 3698945e37eSKevin Cernekee no-big-frame-no; 3708945e37eSKevin Cernekee interrupt-parent = <&periph_intc>; 3718945e37eSKevin Cernekee interrupts = <75>; 3728945e37eSKevin Cernekee status = "disabled"; 3738945e37eSKevin Cernekee }; 3748945e37eSKevin Cernekee 3758945e37eSKevin Cernekee ehci3: usb@490500 { 3768945e37eSKevin Cernekee compatible = "brcm,bcm7346-ehci", "generic-ehci"; 3778945e37eSKevin Cernekee reg = <0x490500 0x100>; 3788945e37eSKevin Cernekee native-endian; 3798945e37eSKevin Cernekee interrupt-parent = <&periph_intc>; 3808945e37eSKevin Cernekee interrupts = <74>; 3818945e37eSKevin Cernekee status = "disabled"; 3828945e37eSKevin Cernekee }; 3838945e37eSKevin Cernekee 3848945e37eSKevin Cernekee ohci3: usb@490600 { 3858945e37eSKevin Cernekee compatible = "brcm,bcm7346-ohci", "generic-ohci"; 3868945e37eSKevin Cernekee reg = <0x490600 0x100>; 3878945e37eSKevin Cernekee native-endian; 3888945e37eSKevin Cernekee no-big-frame-no; 3898945e37eSKevin Cernekee interrupt-parent = <&periph_intc>; 3908945e37eSKevin Cernekee interrupts = <76>; 3918945e37eSKevin Cernekee status = "disabled"; 3928945e37eSKevin Cernekee }; 39319e88101SJaedon Shin 394cfc8be04SJaedon Shin hif_l2_intc: interrupt-controller@411000 { 395cfc8be04SJaedon Shin compatible = "brcm,l2-intc"; 396cfc8be04SJaedon Shin reg = <0x411000 0x30>; 397cfc8be04SJaedon Shin interrupt-controller; 398cfc8be04SJaedon Shin #interrupt-cells = <1>; 399cfc8be04SJaedon Shin interrupt-parent = <&periph_intc>; 400cfc8be04SJaedon Shin interrupts = <30>; 401cfc8be04SJaedon Shin }; 402cfc8be04SJaedon Shin 403cfc8be04SJaedon Shin nand: nand@412800 { 404cfc8be04SJaedon Shin compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand"; 405cfc8be04SJaedon Shin #address-cells = <1>; 406cfc8be04SJaedon Shin #size-cells = <0>; 407cfc8be04SJaedon Shin reg-names = "nand"; 408cfc8be04SJaedon Shin reg = <0x412800 0x400>; 409cfc8be04SJaedon Shin interrupt-parent = <&hif_l2_intc>; 410cfc8be04SJaedon Shin interrupts = <24>; 411cfc8be04SJaedon Shin status = "disabled"; 412cfc8be04SJaedon Shin }; 413cfc8be04SJaedon Shin 41419e88101SJaedon Shin sata: sata@181000 { 41519e88101SJaedon Shin compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci"; 41619e88101SJaedon Shin reg-names = "ahci", "top-ctrl"; 41719e88101SJaedon Shin reg = <0x181000 0xa9c>, <0x180020 0x1c>; 41819e88101SJaedon Shin interrupt-parent = <&periph_intc>; 41919e88101SJaedon Shin interrupts = <40>; 42019e88101SJaedon Shin #address-cells = <1>; 42119e88101SJaedon Shin #size-cells = <0>; 42219e88101SJaedon Shin status = "disabled"; 42319e88101SJaedon Shin 42419e88101SJaedon Shin sata0: sata-port@0 { 42519e88101SJaedon Shin reg = <0>; 42619e88101SJaedon Shin phys = <&sata_phy0>; 42719e88101SJaedon Shin }; 42819e88101SJaedon Shin 42919e88101SJaedon Shin sata1: sata-port@1 { 43019e88101SJaedon Shin reg = <1>; 43119e88101SJaedon Shin phys = <&sata_phy1>; 43219e88101SJaedon Shin }; 43319e88101SJaedon Shin }; 43419e88101SJaedon Shin 43569ca2b81SJaedon Shin sata_phy: sata-phy@180100 { 43619e88101SJaedon Shin compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3"; 43719e88101SJaedon Shin reg = <0x180100 0x0eff>; 43819e88101SJaedon Shin reg-names = "phy"; 43919e88101SJaedon Shin #address-cells = <1>; 44019e88101SJaedon Shin #size-cells = <0>; 44119e88101SJaedon Shin status = "disabled"; 44219e88101SJaedon Shin 44319e88101SJaedon Shin sata_phy0: sata-phy@0 { 44419e88101SJaedon Shin reg = <0>; 44519e88101SJaedon Shin #phy-cells = <0>; 44619e88101SJaedon Shin }; 44719e88101SJaedon Shin 44819e88101SJaedon Shin sata_phy1: sata-phy@1 { 44919e88101SJaedon Shin reg = <1>; 45019e88101SJaedon Shin #phy-cells = <0>; 45119e88101SJaedon Shin }; 45219e88101SJaedon Shin }; 453b2420e27SJaedon Shin 454b2420e27SJaedon Shin sdhci0: sdhci@413500 { 455b2420e27SJaedon Shin compatible = "brcm,bcm7425-sdhci"; 456b2420e27SJaedon Shin reg = <0x413500 0x100>; 457b2420e27SJaedon Shin interrupt-parent = <&periph_intc>; 458b2420e27SJaedon Shin interrupts = <85>; 459b2420e27SJaedon Shin status = "disabled"; 460b2420e27SJaedon Shin }; 461d783738cSJaedon Shin 462d783738cSJaedon Shin spi_l2_intc: interrupt-controller@411d00 { 463d783738cSJaedon Shin compatible = "brcm,l2-intc"; 464d783738cSJaedon Shin reg = <0x411d00 0x30>; 465d783738cSJaedon Shin interrupt-controller; 466d783738cSJaedon Shin #interrupt-cells = <1>; 467d783738cSJaedon Shin interrupt-parent = <&periph_intc>; 468d783738cSJaedon Shin interrupts = <31>; 469d783738cSJaedon Shin }; 470d783738cSJaedon Shin 471d783738cSJaedon Shin qspi: spi@413000 { 472d783738cSJaedon Shin #address-cells = <0x1>; 473d783738cSJaedon Shin #size-cells = <0x0>; 474d783738cSJaedon Shin compatible = "brcm,spi-bcm-qspi", 475d783738cSJaedon Shin "brcm,spi-brcmstb-qspi"; 476d783738cSJaedon Shin clocks = <&upg_clk>; 477d783738cSJaedon Shin reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>; 478d783738cSJaedon Shin reg-names = "cs_reg", "hif_mspi", "bspi"; 479d783738cSJaedon Shin interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>; 480d783738cSJaedon Shin interrupt-parent = <&spi_l2_intc>; 481d783738cSJaedon Shin interrupt-names = "spi_lr_fullness_reached", 482d783738cSJaedon Shin "spi_lr_session_aborted", 483d783738cSJaedon Shin "spi_lr_impatient", 484d783738cSJaedon Shin "spi_lr_session_done", 485d783738cSJaedon Shin "spi_lr_overread", 486d783738cSJaedon Shin "mspi_done", 487d783738cSJaedon Shin "mspi_halted"; 488d783738cSJaedon Shin status = "disabled"; 489d783738cSJaedon Shin }; 490d783738cSJaedon Shin 491d783738cSJaedon Shin mspi: spi@408a00 { 492d783738cSJaedon Shin #address-cells = <1>; 493d783738cSJaedon Shin #size-cells = <0>; 494d783738cSJaedon Shin compatible = "brcm,spi-bcm-qspi", 495d783738cSJaedon Shin "brcm,spi-brcmstb-mspi"; 496d783738cSJaedon Shin clocks = <&upg_clk>; 497d783738cSJaedon Shin reg = <0x408a00 0x180>; 498d783738cSJaedon Shin reg-names = "mspi"; 499d783738cSJaedon Shin interrupts = <0x14>; 500d783738cSJaedon Shin interrupt-parent = <&upg_aon_irq0_intc>; 501d783738cSJaedon Shin interrupt-names = "mspi_done"; 502d783738cSJaedon Shin status = "disabled"; 503d783738cSJaedon Shin }; 504e84442c1SJaedon Shin 505e84442c1SJaedon Shin waketimer: waketimer@408e80 { 506e84442c1SJaedon Shin compatible = "brcm,brcmstb-waketimer"; 507e84442c1SJaedon Shin reg = <0x408e80 0x14>; 508e84442c1SJaedon Shin interrupts = <0x3>; 509e84442c1SJaedon Shin interrupt-parent = <&aon_pm_l2_intc>; 510e84442c1SJaedon Shin interrupt-names = "timer"; 511e84442c1SJaedon Shin clocks = <&upg_clk>; 512e84442c1SJaedon Shin status = "disabled"; 513e84442c1SJaedon Shin }; 5148945e37eSKevin Cernekee }; 515c7146a2bSJaedon Shin 516c7146a2bSJaedon Shin memory_controllers { 517c7146a2bSJaedon Shin compatible = "simple-bus"; 518c7146a2bSJaedon Shin ranges = <0x0 0x103b0000 0xa000>; 519c7146a2bSJaedon Shin #address-cells = <1>; 520c7146a2bSJaedon Shin #size-cells = <1>; 521c7146a2bSJaedon Shin 522c7146a2bSJaedon Shin memory-controller@0 { 523c7146a2bSJaedon Shin compatible = "brcm,brcmstb-memc", "simple-bus"; 524c7146a2bSJaedon Shin ranges = <0x0 0x0 0xa000>; 525c7146a2bSJaedon Shin #address-cells = <1>; 526c7146a2bSJaedon Shin #size-cells = <1>; 527c7146a2bSJaedon Shin 528c7146a2bSJaedon Shin memc-arb@1000 { 529c7146a2bSJaedon Shin compatible = "brcm,brcmstb-memc-arb"; 530c7146a2bSJaedon Shin reg = <0x1000 0x248>; 531c7146a2bSJaedon Shin }; 532c7146a2bSJaedon Shin 533c7146a2bSJaedon Shin memc-ddr@2000 { 534c7146a2bSJaedon Shin compatible = "brcm,brcmstb-memc-ddr"; 535c7146a2bSJaedon Shin reg = <0x2000 0x300>; 536c7146a2bSJaedon Shin }; 537c7146a2bSJaedon Shin 538c7146a2bSJaedon Shin ddr-phy@6000 { 539c7146a2bSJaedon Shin compatible = "brcm,brcmstb-ddr-phy"; 540c7146a2bSJaedon Shin reg = <0x6000 0xc8>; 541c7146a2bSJaedon Shin }; 542c7146a2bSJaedon Shin 543c7146a2bSJaedon Shin shimphy@8000 { 544c7146a2bSJaedon Shin compatible = "brcm,brcmstb-ddr-shimphy"; 545c7146a2bSJaedon Shin reg = <0x8000 0x13c>; 546c7146a2bSJaedon Shin }; 547c7146a2bSJaedon Shin }; 548c7146a2bSJaedon Shin }; 5498945e37eSKevin Cernekee}; 550