/openbmc/linux/Documentation/devicetree/bindings/watchdog/ |
H A D | lpc18xx-wdt.txt | 15 reg = <0x40080000 0x24>;
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/openbmc/u-boot/doc/ |
H A D | README.odroid | 42 The block offset is starting from 0 and the block size is 512B. 47 | Bl1 | 1 | 0 | 1 (boot) | 51 | Uboot Env | 2560 | 2560 | 0 (user) | 181 scanning bus 0 for devices... 4 USB Device(s) found 236 Odroid # tftpboot 0x40080000 zImage.3.17 241 Load address: 0x40080000 249 Odroid # tftpboot 0x42000000 exynos4412-odroidu3.dtb 254 Load address: 0x42000000 263 Kernel image @ 0x40080000 [ 0x000000 - 0x30bd58 ] 265 Booting using the fdt blob at 0x42000000 [all …]
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/openbmc/qemu/tests/migration/ |
H A D | migration-test.h | 25 #define PPC_H_PUT_TERM_CHAR 0x58 28 #define ARM_TEST_MEM_START (0x40000000 + 1 * 1024 * 1024) 29 #define ARM_TEST_MEM_END (0x40000000 + 100 * 1024 * 1024) 30 #define ARM_MACH_VIRT_UART 0x09000000 31 /* AArch64 kernel load address is 0x40080000, and the test memory starts at 32 * 0x40100000. So the maximum allowable kernel size is 512KB.
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/openbmc/linux/arch/sh/drivers/pci/ |
H A D | fixups-rts7751r2d.c | 17 #define PCIMCR_MRSET_OFF 0xBFFFFFFF 18 #define PCIMCR_RFSH_OFF 0xFFFFFFFB 44 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ in pci_fixup_pcic() 48 pci_write_reg(chan, 0x0000c3ff, SH4_PCIINTM); in pci_fixup_pcic() 49 pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM); in pci_fixup_pcic() 51 pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1); in pci_fixup_pcic() 52 pci_write_reg(chan, 0xab000001, SH7751_PCICONF4); in pci_fixup_pcic() 58 pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5); in pci_fixup_pcic() 59 pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6); in pci_fixup_pcic() 60 pci_write_reg(chan, 0x0c000000, SH4_PCILAR0); in pci_fixup_pcic() [all …]
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H A D | fixups-landisk.c | 18 #define PCIMCR_MRSET_OFF 0xBFFFFFFF 19 #define PCIMCR_RFSH_OFF 0xFFFFFFFB 29 int irq = ((slot + pin - 1) & 0x3) + evt2irq(0x2a0); in pcibios_map_platform_irq() 31 if ((slot | (pin - 1)) > 0x3) { in pcibios_map_platform_irq() 44 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ in pci_fixup_pcic() 51 pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5); in pci_fixup_pcic() 52 pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6); in pci_fixup_pcic() 53 pci_write_reg(chan, 0x0c000000, SH4_PCILAR0); in pci_fixup_pcic() 54 pci_write_reg(chan, 0x00000000, SH4_PCILAR1); in pci_fixup_pcic() 56 return 0; in pci_fixup_pcic()
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H A D | fixups-se7751.c | 14 case 0: return evt2irq(0x3a0); in pcibios_map_platform_irq() 15 case 1: return evt2irq(0x3a0); /* AMD Ethernet controller */ in pcibios_map_platform_irq() 25 #define PCIMCR_MRSET_OFF 0xBFFFFFFF 26 #define PCIMCR_RFSH_OFF 0xFFFFFFFB 58 bcr1 = bcr1 | 0x00080000; /* Enable Bit 19, BREQEN */ in pci_fixup_pcic() 61 bcr1 = bcr1 | 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ in pci_fixup_pcic() 72 PCIC_WRITE(SH7751_PCIINTM, 0x0000c3ff); in pci_fixup_pcic() 73 PCIC_WRITE(SH7751_PCIAINTM, 0x0000380f); in pci_fixup_pcic() 76 PCIC_WRITE(SH7751_PCICONF1, 0xF39000C7); /* Bus Master, Mem & I/O access */ in pci_fixup_pcic() 77 PCIC_WRITE(SH7751_PCICONF2, 0x00000000); /* PCI Class code & Revision ID */ in pci_fixup_pcic() [all …]
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/openbmc/u-boot/doc/uImage.FIT/ |
H A D | multi_spl.its | 19 #address-cells = <0x1>; 28 load = <0x4a000000>; 36 load = <0x18000>; 37 entry = <0x18000>; 45 load = <0x40000>; 52 load = <0x4fa00000>; 60 load = <0x4fa00000>; 68 load = <0x40080000>; 76 load = <0x4fe00000>;
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/openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/ |
H A D | cpu.h | 12 #define SLC_NAND_BASE 0x20020000 /* SLC NAND Flash registers base */ 13 #define SSP0_BASE 0x20084000 /* SSP0 registers base */ 14 #define SD_CARD_BASE 0x20098000 /* SD card interface registers base */ 15 #define MLC_NAND_BASE 0x200A8000 /* MLC NAND Flash registers base */ 16 #define DMA_BASE 0x31000000 /* DMA controller registers base */ 17 #define USB_BASE 0x31020000 /* USB registers base */ 18 #define LCD_BASE 0x31040000 /* LCD registers base */ 19 #define ETHERNET_BASE 0x31060000 /* Ethernet registers base */ 20 #define EMC_BASE 0x31080000 /* EMC configuration registers base */ 23 #define CLK_PM_BASE 0x40004000 /* System control registers base */ [all …]
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/openbmc/linux/arch/arm64/boot/dts/freescale/ |
H A D | s32v234.dtsi | 9 /memreserve/ 0x80000000 0x00010000; 24 #size-cells = <0>; 26 cpu0: cpu@0 { 29 reg = <0x0 0x0>; 31 cpu-release-addr = <0x0 0x80000000>; 38 reg = <0x0 0x1>; 40 cpu-release-addr = <0x0 0x80000000>; 47 reg = <0x0 0x100>; 49 cpu-release-addr = <0x0 0x80000000>; 56 reg = <0x0 0x101>; [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | vf.dtsi | 37 reg = <0x40000000 0x00070000>; 42 reg = <0x40027000 0x1000>; 48 reg = <0x40028000 0x1000>; 54 reg = <0x40029000 0x1000>; 60 reg = <0x4002a000 0x1000>; 66 #size-cells = <0>; 68 reg = <0x4002c000 0x1000>; 75 #size-cells = <0>; 77 reg = <0x4002d000 0x1000>; 84 #size-cells = <0>; [all …]
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H A D | imx7ulp.dtsi | 38 #size-cells = <0>; 40 cpu0: cpu@0 { 43 reg = <0>; 56 size = <0xC000000>; 57 alignment = <0x2000>; 63 reg = <0x9FF00000 0x100000>; 72 reg = <0x40021000 0x1000>, 73 <0x40022000 0x100>; 78 #size-cells = <0>; 80 ckil: clock@0 { [all …]
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/openbmc/qemu/tests/tcg/xtensa/ |
H A D | test_lsc.S | 18 lsi f0, a2, 0 24 movi a3, 0x3f800000 27 movi a3, 0x40000000 30 movi a3, 0x40400000 41 movi a3, 0x40800000 43 movi a3, 0x40a00000 45 movi a3, 0x40c00000 52 ssi f3, a2, 0 58 movi a3, 0x40800000 61 movi a3, 0x40a00000 [all …]
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/openbmc/linux/drivers/net/wireless/rsi/ |
H A D | rsi_hal.h | 45 #define FLASH_SIZE_ADDR 0x04000016 46 #define PING_BUFFER_ADDRESS 0x19000 47 #define PONG_BUFFER_ADDRESS 0x1a000 48 #define SWBL_REGIN 0x41050034 49 #define SWBL_REGOUT 0x4105003c 50 #define PING_WRITE 0x1 51 #define PONG_WRITE 0x2 56 #define REGIN_VALID 0xA 57 #define REGIN_INPUT 0xA0 58 #define REGOUT_VALID 0xAB [all …]
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/openbmc/linux/Documentation/devicetree/bindings/dma/ |
H A D | fsl,edma.yaml | 162 reg = <0x40018000 0x2000>, 163 <0x40024000 0x1000>, 164 <0x40025000 0x1000>; 165 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, 166 <0 9 IRQ_TYPE_LEVEL_HIGH>; 180 reg = <0x40080000 0x2000>, 181 <0x40210000 0x1000>; 183 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 211 reg = <0x44000000 0x200000>;
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/openbmc/linux/lib/crypto/ |
H A D | des.c | 31 0x00, 0x00, 0x40, 0x04, 0x10, 0x10, 0x50, 0x14, 32 0x04, 0x40, 0x44, 0x44, 0x14, 0x50, 0x54, 0x54, 33 0x02, 0x02, 0x42, 0x06, 0x12, 0x12, 0x52, 0x16, 34 0x06, 0x42, 0x46, 0x46, 0x16, 0x52, 0x56, 0x56, 35 0x80, 0x08, 0xc0, 0x0c, 0x90, 0x18, 0xd0, 0x1c, 36 0x84, 0x48, 0xc4, 0x4c, 0x94, 0x58, 0xd4, 0x5c, 37 0x82, 0x0a, 0xc2, 0x0e, 0x92, 0x1a, 0xd2, 0x1e, 38 0x86, 0x4a, 0xc6, 0x4e, 0x96, 0x5a, 0xd6, 0x5e, 39 0x20, 0x20, 0x60, 0x24, 0x30, 0x30, 0x70, 0x34, 40 0x24, 0x60, 0x64, 0x64, 0x34, 0x70, 0x74, 0x74, [all …]
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/openbmc/linux/arch/x86/pci/ |
H A D | olpc.c | 33 * the size of the region by writing ~0 to a base address register 38 * ~0 to a base address register. 41 static const uint32_t lxnb_hdr[] = { /* dev 1 function 0 - devfn = 8 */ 42 0x0, 0x0, 0x0, 0x0, 43 0x0, 0x0, 0x0, 0x0, 45 0x281022, 0x2200005, 0x6000021, 0x80f808, /* AMD Vendor ID */ 46 0x0, 0x0, 0x0, 0x0, /* No virtual registers, hence no BAR */ 47 0x0, 0x0, 0x0, 0x28100b, 48 0x0, 0x0, 0x0, 0x0, 49 0x0, 0x0, 0x0, 0x0, [all …]
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/openbmc/linux/arch/arm/boot/dts/nxp/lpc/ |
H A D | lpc32xx.dtsi | 20 #size-cells = <0>; 22 cpu@0 { 25 reg = <0x0>; 32 #clock-cells = <0>; 39 #clock-cells = <0>; 49 ranges = <0x00000000 0x00000000 0x10000000>, 50 <0x20000000 0x20000000 0x30000000>, 51 <0xe0000000 0xe0000000 0x04000000>; 55 reg = <0x08000000 0x20000>; 59 ranges = <0x00000000 0x08000000 0x20000>; [all …]
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H A D | lpc18xx.dtsi | 19 #define LPC_PIN(port, pin) (0x##port * 32 + pin) 28 #size-cells = <0>; 30 cpu@0 { 33 reg = <0x0>; 41 #clock-cells = <0>; 47 #clock-cells = <0>; 53 #clock-cells = <0>; 54 clock-frequency = <0>; 60 #clock-cells = <0>; 61 clock-frequency = <0>; [all …]
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/openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imx7ulp.dtsi | 38 #size-cells = <0>; 43 reg = <0xf00>; 51 reg = <0x40021000 0x1000>, 52 <0x40022000 0x1000>; 59 #clock-cells = <0>; 66 #clock-cells = <0>; 73 #clock-cells = <0>; 80 #clock-cells = <0>; 87 #clock-cells = <0>; 94 reg = <0x40000000 0x800000>; [all …]
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/openbmc/qemu/hw/riscv/ |
H A D | opentitan.c | 41 [IBEX_DEV_ROM] = { 0x00008000, 0x8000 }, 42 [IBEX_DEV_RAM] = { 0x10000000, 0x20000 }, 43 [IBEX_DEV_FLASH] = { 0x20000000, 0x100000 }, 44 [IBEX_DEV_UART] = { 0x40000000, 0x40 }, 45 [IBEX_DEV_GPIO] = { 0x40040000, 0x40 }, 46 [IBEX_DEV_SPI_DEVICE] = { 0x40050000, 0x2000 }, 47 [IBEX_DEV_I2C] = { 0x40080000, 0x80 }, 48 [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x40 }, 49 [IBEX_DEV_TIMER] = { 0x40100000, 0x200 }, 50 [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x2000 }, [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-vf610/ |
H A D | imx-regs.h | 11 #define IRAM_BASE_ADDR 0x3F000000 /* internal ram */ 12 #define IRAM_SIZE 0x00080000 /* 512 KB */ 14 #define AIPS0_BASE_ADDR 0x40000000 15 #define AIPS1_BASE_ADDR 0x40080000 17 /* AIPS 0 */ 18 #define MSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000) 19 #define MSCM_IR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001800) 20 #define CA5SCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000) 21 #define CA5_INTD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00003000) 22 #define CA5_L2C_BASE_ADDR (AIPS0_BASE_ADDR + 0x00006000) [all …]
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/openbmc/linux/arch/arm/mach-lpc32xx/ |
H A D | lpc32xx.h | 17 * AHB 0 physical base addresses 19 #define LPC32XX_SLC_BASE 0x20020000 20 #define LPC32XX_SSP0_BASE 0x20084000 21 #define LPC32XX_SPI1_BASE 0x20088000 22 #define LPC32XX_SSP1_BASE 0x2008C000 23 #define LPC32XX_SPI2_BASE 0x20090000 24 #define LPC32XX_I2S0_BASE 0x20094000 25 #define LPC32XX_SD_BASE 0x20098000 26 #define LPC32XX_I2S1_BASE 0x2009C000 27 #define LPC32XX_MLC_BASE 0x200A8000 [all …]
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/openbmc/linux/arch/arm/boot/dts/nxp/vf/ |
H A D | vfxxx.dtsi | 33 #clock-cells = <0>; 39 #clock-cells = <0>; 46 offset = <0x0>; 47 mask = <0x1000>; 66 reg = <0x40000000 0x00070000>; 71 reg = <0x40001000 0x800>; 76 reg = <0x40001800 0x400>; 85 reg = <0x40018000 0x2000>, 86 <0x40024000 0x1000>, 87 <0x40025000 0x1000>; [all …]
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/openbmc/linux/arch/arm/boot/dts/st/ |
H A D | stm32h743.dtsi | 54 #clock-cells = <0>; 56 clock-frequency = <0>; 60 #clock-cells = <0>; 66 #clock-cells = <0>; 68 clock-frequency = <0>; 75 reg = <0x40000c00 0x400>; 82 #size-cells = <0>; 84 reg = <0x40002400 0x400>; 95 trigger@0 { 97 reg = <0>; [all …]
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/openbmc/qemu/hw/arm/ |
H A D | armsse.c | 54 int irq; /* NO_IRQ, or 0..NUM_SSE_IRQS-1, or NMI_0 or NMI_1 */ 85 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), 86 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), 87 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), 88 DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8), 89 DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8), 98 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), 99 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false), 100 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false), 103 DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8), [all …]
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