1b2441318SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0
22d5efc19SPaul Mundt #include <linux/kernel.h>
32d5efc19SPaul Mundt #include <linux/types.h>
42d5efc19SPaul Mundt #include <linux/init.h>
52d5efc19SPaul Mundt #include <linux/delay.h>
62d5efc19SPaul Mundt #include <linux/pci.h>
72d5efc19SPaul Mundt #include <linux/io.h>
858796ce6SPaul Mundt #include <linux/sh_intc.h>
92d5efc19SPaul Mundt #include "pci-sh4.h"
102d5efc19SPaul Mundt
pcibios_map_platform_irq(const struct pci_dev *,u8 slot,u8 pin)112b8ff9f2SMatthew Minter int pcibios_map_platform_irq(const struct pci_dev *, u8 slot, u8 pin)
122d5efc19SPaul Mundt {
132d5efc19SPaul Mundt switch (slot) {
1458796ce6SPaul Mundt case 0: return evt2irq(0x3a0);
1558796ce6SPaul Mundt case 1: return evt2irq(0x3a0); /* AMD Ethernet controller */
162d5efc19SPaul Mundt case 2: return -1;
172d5efc19SPaul Mundt case 3: return -1;
182d5efc19SPaul Mundt case 4: return -1;
192d5efc19SPaul Mundt default:
202d5efc19SPaul Mundt printk("PCI: Bad IRQ mapping request for slot %d\n", slot);
212d5efc19SPaul Mundt return -1;
222d5efc19SPaul Mundt }
232d5efc19SPaul Mundt }
242d5efc19SPaul Mundt
252d5efc19SPaul Mundt #define PCIMCR_MRSET_OFF 0xBFFFFFFF
262d5efc19SPaul Mundt #define PCIMCR_RFSH_OFF 0xFFFFFFFB
272d5efc19SPaul Mundt
282d5efc19SPaul Mundt /*
292d5efc19SPaul Mundt * Only long word accesses of the PCIC's internal local registers and the
302d5efc19SPaul Mundt * configuration registers from the CPU is supported.
312d5efc19SPaul Mundt */
322d5efc19SPaul Mundt #define PCIC_WRITE(x,v) writel((v), PCI_REG(x))
332d5efc19SPaul Mundt #define PCIC_READ(x) readl(PCI_REG(x))
342d5efc19SPaul Mundt
352d5efc19SPaul Mundt /*
362d5efc19SPaul Mundt * Description: This function sets up and initializes the pcic, sets
372d5efc19SPaul Mundt * up the BARS, maps the DRAM into the address space etc, etc.
382d5efc19SPaul Mundt */
pci_fixup_pcic(struct pci_channel * chan)392d5efc19SPaul Mundt int pci_fixup_pcic(struct pci_channel *chan)
402d5efc19SPaul Mundt {
412d5efc19SPaul Mundt unsigned long bcr1, wcr1, wcr2, wcr3, mcr;
422d5efc19SPaul Mundt unsigned short bcr2;
432d5efc19SPaul Mundt
442d5efc19SPaul Mundt /*
452d5efc19SPaul Mundt * Initialize the slave bus controller on the pcic. The values used
462d5efc19SPaul Mundt * here should not be hardcoded, but they should be taken from the bsc
472d5efc19SPaul Mundt * on the processor, to make this function as generic as possible.
482d5efc19SPaul Mundt * (i.e. Another sbc may usr different SDRAM timing settings -- in order
492d5efc19SPaul Mundt * for the pcic to work, its settings need to be exactly the same.)
502d5efc19SPaul Mundt */
512d5efc19SPaul Mundt bcr1 = (*(volatile unsigned long*)(SH7751_BCR1));
522d5efc19SPaul Mundt bcr2 = (*(volatile unsigned short*)(SH7751_BCR2));
532d5efc19SPaul Mundt wcr1 = (*(volatile unsigned long*)(SH7751_WCR1));
542d5efc19SPaul Mundt wcr2 = (*(volatile unsigned long*)(SH7751_WCR2));
552d5efc19SPaul Mundt wcr3 = (*(volatile unsigned long*)(SH7751_WCR3));
562d5efc19SPaul Mundt mcr = (*(volatile unsigned long*)(SH7751_MCR));
572d5efc19SPaul Mundt
582d5efc19SPaul Mundt bcr1 = bcr1 | 0x00080000; /* Enable Bit 19, BREQEN */
592d5efc19SPaul Mundt (*(volatile unsigned long*)(SH7751_BCR1)) = bcr1;
602d5efc19SPaul Mundt
612d5efc19SPaul Mundt bcr1 = bcr1 | 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
622d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCIBCR1, bcr1); /* PCIC BCR1 */
632d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCIBCR2, bcr2); /* PCIC BCR2 */
642d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCIWCR1, wcr1); /* PCIC WCR1 */
652d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCIWCR2, wcr2); /* PCIC WCR2 */
662d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCIWCR3, wcr3); /* PCIC WCR3 */
672d5efc19SPaul Mundt mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
682d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCIMCR, mcr); /* PCIC MCR */
692d5efc19SPaul Mundt
702d5efc19SPaul Mundt
712d5efc19SPaul Mundt /* Enable all interrupts, so we know what to fix */
722d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCIINTM, 0x0000c3ff);
732d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCIAINTM, 0x0000380f);
742d5efc19SPaul Mundt
752d5efc19SPaul Mundt /* Set up standard PCI config registers */
762d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCICONF1, 0xF39000C7); /* Bus Master, Mem & I/O access */
772d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCICONF2, 0x00000000); /* PCI Class code & Revision ID */
782d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCICONF4, 0xab000001); /* PCI I/O address (local regs) */
792d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCICONF5, 0x0c000000); /* PCI MEM address (local RAM) */
802d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCICONF6, 0xd0000000); /* PCI MEM address (unused) */
812d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCICONF11, 0x35051054); /* PCI Subsystem ID & Vendor ID */
822d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCILSR0, 0x03f00000); /* MEM (full 64M exposed) */
832d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCILSR1, 0x00000000); /* MEM (unused) */
842d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCILAR0, 0x0c000000); /* MEM (direct map from PCI) */
852d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCILAR1, 0x00000000); /* MEM (unused) */
862d5efc19SPaul Mundt
872d5efc19SPaul Mundt /* Now turn it on... */
882d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCICR, 0xa5000001);
892d5efc19SPaul Mundt
902d5efc19SPaul Mundt /*
912d5efc19SPaul Mundt * Set PCIMBR and PCIIOBR here, assuming a single window
922d5efc19SPaul Mundt * (16M MEM, 256K IO) is enough. If a larger space is
932d5efc19SPaul Mundt * needed, the readx/writex and inx/outx functions will
942d5efc19SPaul Mundt * have to do more (e.g. setting registers for each call).
952d5efc19SPaul Mundt */
962d5efc19SPaul Mundt
972d5efc19SPaul Mundt /*
982d5efc19SPaul Mundt * Set the MBR so PCI address is one-to-one with window,
992d5efc19SPaul Mundt * meaning all calls go straight through... use BUG_ON to
1002d5efc19SPaul Mundt * catch erroneous assumption.
1012d5efc19SPaul Mundt */
102b6c58b1dSPaul Mundt BUG_ON(chan->resources[1].start != SH7751_PCI_MEMORY_BASE);
1032d5efc19SPaul Mundt
104b6c58b1dSPaul Mundt PCIC_WRITE(SH7751_PCIMBR, chan->resources[1].start);
1052d5efc19SPaul Mundt
1062d5efc19SPaul Mundt /* Set IOBR for window containing area specified in pci.h */
107b6c58b1dSPaul Mundt PCIC_WRITE(SH7751_PCIIOBR, (chan->resources[0].start & SH7751_PCIIOBR_MASK));
1082d5efc19SPaul Mundt
1092d5efc19SPaul Mundt /* All done, may as well say so... */
1102d5efc19SPaul Mundt printk("SH7751 PCI: Finished initialization of the PCI controller\n");
1112d5efc19SPaul Mundt
1122d5efc19SPaul Mundt return 1;
1132d5efc19SPaul Mundt }
114