1bc66392dSStoica Cosmin-Stefan// SPDX-License-Identifier: GPL-2.0-or-later 2bc66392dSStoica Cosmin-Stefan/* 3bc66392dSStoica Cosmin-Stefan * Copyright 2015-2016 Freescale Semiconductor, Inc. 4bc66392dSStoica Cosmin-Stefan * Copyright 2016-2018 NXP 5bc66392dSStoica Cosmin-Stefan */ 6bc66392dSStoica Cosmin-Stefan 7bc66392dSStoica Cosmin-Stefan#include <dt-bindings/interrupt-controller/arm-gic.h> 8bc66392dSStoica Cosmin-Stefan 9bc66392dSStoica Cosmin-Stefan/memreserve/ 0x80000000 0x00010000; 10bc66392dSStoica Cosmin-Stefan 11bc66392dSStoica Cosmin-Stefan/ { 12bc66392dSStoica Cosmin-Stefan compatible = "fsl,s32v234"; 13bc66392dSStoica Cosmin-Stefan interrupt-parent = <&gic>; 14bc66392dSStoica Cosmin-Stefan #address-cells = <2>; 15bc66392dSStoica Cosmin-Stefan #size-cells = <2>; 16bc66392dSStoica Cosmin-Stefan 17bc66392dSStoica Cosmin-Stefan aliases { 18bc66392dSStoica Cosmin-Stefan serial0 = &uart0; 19bc66392dSStoica Cosmin-Stefan serial1 = &uart1; 20bc66392dSStoica Cosmin-Stefan }; 21bc66392dSStoica Cosmin-Stefan 22bc66392dSStoica Cosmin-Stefan cpus { 23bc66392dSStoica Cosmin-Stefan #address-cells = <2>; 24bc66392dSStoica Cosmin-Stefan #size-cells = <0>; 25bc66392dSStoica Cosmin-Stefan 26bc66392dSStoica Cosmin-Stefan cpu0: cpu@0 { 27bc66392dSStoica Cosmin-Stefan device_type = "cpu"; 28bc66392dSStoica Cosmin-Stefan compatible = "arm,cortex-a53"; 29bc66392dSStoica Cosmin-Stefan reg = <0x0 0x0>; 30bc66392dSStoica Cosmin-Stefan enable-method = "spin-table"; 31bc66392dSStoica Cosmin-Stefan cpu-release-addr = <0x0 0x80000000>; 32bc66392dSStoica Cosmin-Stefan next-level-cache = <&cluster0_l2_cache>; 33bc66392dSStoica Cosmin-Stefan }; 34bc66392dSStoica Cosmin-Stefan 35bc66392dSStoica Cosmin-Stefan cpu1: cpu@1 { 36bc66392dSStoica Cosmin-Stefan device_type = "cpu"; 37bc66392dSStoica Cosmin-Stefan compatible = "arm,cortex-a53"; 38bc66392dSStoica Cosmin-Stefan reg = <0x0 0x1>; 39bc66392dSStoica Cosmin-Stefan enable-method = "spin-table"; 40bc66392dSStoica Cosmin-Stefan cpu-release-addr = <0x0 0x80000000>; 41bc66392dSStoica Cosmin-Stefan next-level-cache = <&cluster0_l2_cache>; 42bc66392dSStoica Cosmin-Stefan }; 43bc66392dSStoica Cosmin-Stefan 44bc66392dSStoica Cosmin-Stefan cpu2: cpu@100 { 45bc66392dSStoica Cosmin-Stefan device_type = "cpu"; 46bc66392dSStoica Cosmin-Stefan compatible = "arm,cortex-a53"; 47bc66392dSStoica Cosmin-Stefan reg = <0x0 0x100>; 48bc66392dSStoica Cosmin-Stefan enable-method = "spin-table"; 49bc66392dSStoica Cosmin-Stefan cpu-release-addr = <0x0 0x80000000>; 50bc66392dSStoica Cosmin-Stefan next-level-cache = <&cluster1_l2_cache>; 51bc66392dSStoica Cosmin-Stefan }; 52bc66392dSStoica Cosmin-Stefan 53bc66392dSStoica Cosmin-Stefan cpu3: cpu@101 { 54bc66392dSStoica Cosmin-Stefan device_type = "cpu"; 55bc66392dSStoica Cosmin-Stefan compatible = "arm,cortex-a53"; 56bc66392dSStoica Cosmin-Stefan reg = <0x0 0x101>; 57bc66392dSStoica Cosmin-Stefan enable-method = "spin-table"; 58bc66392dSStoica Cosmin-Stefan cpu-release-addr = <0x0 0x80000000>; 59bc66392dSStoica Cosmin-Stefan next-level-cache = <&cluster1_l2_cache>; 60bc66392dSStoica Cosmin-Stefan }; 61bc66392dSStoica Cosmin-Stefan 62bc66392dSStoica Cosmin-Stefan cluster0_l2_cache: l2-cache0 { 63bc66392dSStoica Cosmin-Stefan compatible = "cache"; 643b450831SPierre Gondois cache-level = <2>; 65*e2b96cebSKrzysztof Kozlowski cache-unified; 66bc66392dSStoica Cosmin-Stefan }; 67bc66392dSStoica Cosmin-Stefan 68bc66392dSStoica Cosmin-Stefan cluster1_l2_cache: l2-cache1 { 69bc66392dSStoica Cosmin-Stefan compatible = "cache"; 703b450831SPierre Gondois cache-level = <2>; 71*e2b96cebSKrzysztof Kozlowski cache-unified; 72bc66392dSStoica Cosmin-Stefan }; 73bc66392dSStoica Cosmin-Stefan }; 74bc66392dSStoica Cosmin-Stefan 75bc66392dSStoica Cosmin-Stefan timer { 76bc66392dSStoica Cosmin-Stefan compatible = "arm,armv8-timer"; 77bc66392dSStoica Cosmin-Stefan interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 78bc66392dSStoica Cosmin-Stefan IRQ_TYPE_LEVEL_LOW)>, 79bc66392dSStoica Cosmin-Stefan <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 80bc66392dSStoica Cosmin-Stefan IRQ_TYPE_LEVEL_LOW)>, 81bc66392dSStoica Cosmin-Stefan <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 82bc66392dSStoica Cosmin-Stefan IRQ_TYPE_LEVEL_LOW)>, 83bc66392dSStoica Cosmin-Stefan <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 84bc66392dSStoica Cosmin-Stefan IRQ_TYPE_LEVEL_LOW)>; 85bc66392dSStoica Cosmin-Stefan /* clock-frequency might be modified by u-boot, depending on the 86bc66392dSStoica Cosmin-Stefan * chip version. 87bc66392dSStoica Cosmin-Stefan */ 88bc66392dSStoica Cosmin-Stefan clock-frequency = <10000000>; 89bc66392dSStoica Cosmin-Stefan }; 90bc66392dSStoica Cosmin-Stefan 91bc66392dSStoica Cosmin-Stefan gic: interrupt-controller@7d001000 { 92bc66392dSStoica Cosmin-Stefan compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; 93bc66392dSStoica Cosmin-Stefan #interrupt-cells = <3>; 94bc66392dSStoica Cosmin-Stefan #address-cells = <0>; 95bc66392dSStoica Cosmin-Stefan interrupt-controller; 96bc66392dSStoica Cosmin-Stefan reg = <0 0x7d001000 0 0x1000>, 97bc66392dSStoica Cosmin-Stefan <0 0x7d002000 0 0x2000>, 98bc66392dSStoica Cosmin-Stefan <0 0x7d004000 0 0x2000>, 99bc66392dSStoica Cosmin-Stefan <0 0x7d006000 0 0x2000>; 100bc66392dSStoica Cosmin-Stefan interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 101bc66392dSStoica Cosmin-Stefan IRQ_TYPE_LEVEL_HIGH)>; 102bc66392dSStoica Cosmin-Stefan }; 103bc66392dSStoica Cosmin-Stefan 104bc66392dSStoica Cosmin-Stefan soc { 105bc66392dSStoica Cosmin-Stefan #address-cells = <2>; 106bc66392dSStoica Cosmin-Stefan #size-cells = <2>; 107bc66392dSStoica Cosmin-Stefan compatible = "simple-bus"; 108bc66392dSStoica Cosmin-Stefan interrupt-parent = <&gic>; 109bc66392dSStoica Cosmin-Stefan ranges; 110bc66392dSStoica Cosmin-Stefan 11170ea3603SPeng Fan aips0: bus@40000000 { 112bc66392dSStoica Cosmin-Stefan compatible = "simple-bus"; 113bc66392dSStoica Cosmin-Stefan #address-cells = <2>; 114bc66392dSStoica Cosmin-Stefan #size-cells = <2>; 115bc66392dSStoica Cosmin-Stefan interrupt-parent = <&gic>; 116bc66392dSStoica Cosmin-Stefan reg = <0x0 0x40000000 0x0 0x7d000>; 117bc66392dSStoica Cosmin-Stefan ranges; 118bc66392dSStoica Cosmin-Stefan 119bc66392dSStoica Cosmin-Stefan uart0: serial@40053000 { 120bc66392dSStoica Cosmin-Stefan compatible = "fsl,s32v234-linflexuart"; 121bc66392dSStoica Cosmin-Stefan reg = <0x0 0x40053000 0x0 0x1000>; 122bc66392dSStoica Cosmin-Stefan interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>; 123bc66392dSStoica Cosmin-Stefan status = "disabled"; 124bc66392dSStoica Cosmin-Stefan }; 125bc66392dSStoica Cosmin-Stefan }; 126bc66392dSStoica Cosmin-Stefan 12770ea3603SPeng Fan aips1: bus@40080000 { 128bc66392dSStoica Cosmin-Stefan compatible = "simple-bus"; 129bc66392dSStoica Cosmin-Stefan #address-cells = <2>; 130bc66392dSStoica Cosmin-Stefan #size-cells = <2>; 131bc66392dSStoica Cosmin-Stefan interrupt-parent = <&gic>; 132bc66392dSStoica Cosmin-Stefan reg = <0x0 0x40080000 0x0 0x70000>; 133bc66392dSStoica Cosmin-Stefan ranges; 134bc66392dSStoica Cosmin-Stefan 135bc66392dSStoica Cosmin-Stefan uart1: serial@400bc000 { 136bc66392dSStoica Cosmin-Stefan compatible = "fsl,s32v234-linflexuart"; 137bc66392dSStoica Cosmin-Stefan reg = <0x0 0x400bc000 0x0 0x1000>; 138bc66392dSStoica Cosmin-Stefan interrupts = <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>; 139bc66392dSStoica Cosmin-Stefan status = "disabled"; 140bc66392dSStoica Cosmin-Stefan }; 141bc66392dSStoica Cosmin-Stefan }; 142bc66392dSStoica Cosmin-Stefan }; 143bc66392dSStoica Cosmin-Stefan}; 144