/openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | clearstate_gfx11.h | 28 0x00000000, // DB_RENDER_CONTROL 29 0x00000000, // DB_COUNT_CONTROL 30 0x00000000, // DB_DEPTH_VIEW 31 0x00000000, // DB_RENDER_OVERRIDE 32 0x00000000, // DB_RENDER_OVERRIDE2 33 0x00000000, // DB_HTILE_DATA_BASE 34 0, // HOLE 35 0x00000000, // DB_DEPTH_SIZE_XY 36 0x00000000, // DB_DEPTH_BOUNDS_MIN 37 0x00000000, // DB_DEPTH_BOUNDS_MAX [all …]
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H A D | clearstate_vi.h | 26 0x00000000, // DB_RENDER_CONTROL 27 0x00000000, // DB_COUNT_CONTROL 28 0x00000000, // DB_DEPTH_VIEW 29 0x00000000, // DB_RENDER_OVERRIDE 30 0x00000000, // DB_RENDER_OVERRIDE2 31 0x00000000, // DB_HTILE_DATA_BASE 32 0, // HOLE 33 0, // HOLE 34 0x00000000, // DB_DEPTH_BOUNDS_MIN 35 0x00000000, // DB_DEPTH_BOUNDS_MAX [all …]
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H A D | clearstate_ci.h | 26 0x00000000, // DB_RENDER_CONTROL 27 0x00000000, // DB_COUNT_CONTROL 28 0x00000000, // DB_DEPTH_VIEW 29 0x00000000, // DB_RENDER_OVERRIDE 30 0x00000000, // DB_RENDER_OVERRIDE2 31 0x00000000, // DB_HTILE_DATA_BASE 32 0, // HOLE 33 0, // HOLE 34 0x00000000, // DB_DEPTH_BOUNDS_MIN 35 0x00000000, // DB_DEPTH_BOUNDS_MAX [all …]
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H A D | clearstate_si.h | 26 0x00000000, // DB_RENDER_CONTROL 27 0x00000000, // DB_COUNT_CONTROL 28 0x00000000, // DB_DEPTH_VIEW 29 0x00000000, // DB_RENDER_OVERRIDE 30 0x00000000, // DB_RENDER_OVERRIDE2 31 0x00000000, // DB_HTILE_DATA_BASE 32 0, // HOLE 33 0, // HOLE 34 0x00000000, // DB_DEPTH_BOUNDS_MIN 35 0x00000000, // DB_DEPTH_BOUNDS_MAX [all …]
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H A D | clearstate_gfx9.h | 26 0x00000000, // DB_RENDER_CONTROL 27 0x00000000, // DB_COUNT_CONTROL 28 0x00000000, // DB_DEPTH_VIEW 29 0x00000000, // DB_RENDER_OVERRIDE 30 0x00000000, // DB_RENDER_OVERRIDE2 31 0x00000000, // DB_HTILE_DATA_BASE 32 0x00000000, // DB_HTILE_DATA_BASE_HI 33 0x00000000, // DB_DEPTH_SIZE 34 0x00000000, // DB_DEPTH_BOUNDS_MIN 35 0x00000000, // DB_DEPTH_BOUNDS_MAX [all …]
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H A D | clearstate_gfx10.h | 25 0x00000000, // DB_RENDER_CONTROL 26 0x00000000, // DB_COUNT_CONTROL 27 0x00000000, // DB_DEPTH_VIEW 28 0x00000000, // DB_RENDER_OVERRIDE 29 0x00000000, // DB_RENDER_OVERRIDE2 30 0x00000000, // DB_HTILE_DATA_BASE 31 0x00000000, // HOLE 32 0x00000000, // DB_DEPTH_SIZE_XY 33 0x00000000, // DB_DEPTH_BOUNDS_MIN 34 0x00000000, // DB_DEPTH_BOUNDS_MAX [all …]
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/openbmc/linux/drivers/gpu/drm/radeon/ |
H A D | clearstate_ci.h | 28 0x00000000, // DB_RENDER_CONTROL 29 0x00000000, // DB_COUNT_CONTROL 30 0x00000000, // DB_DEPTH_VIEW 31 0x00000000, // DB_RENDER_OVERRIDE 32 0x00000000, // DB_RENDER_OVERRIDE2 33 0x00000000, // DB_HTILE_DATA_BASE 34 0, // HOLE 35 0, // HOLE 36 0x00000000, // DB_DEPTH_BOUNDS_MIN 37 0x00000000, // DB_DEPTH_BOUNDS_MAX [all …]
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H A D | clearstate_si.h | 27 0x00000000, // DB_RENDER_CONTROL 28 0x00000000, // DB_COUNT_CONTROL 29 0x00000000, // DB_DEPTH_VIEW 30 0x00000000, // DB_RENDER_OVERRIDE 31 0x00000000, // DB_RENDER_OVERRIDE2 32 0x00000000, // DB_HTILE_DATA_BASE 33 0, // HOLE 34 0, // HOLE 35 0x00000000, // DB_DEPTH_BOUNDS_MIN 36 0x00000000, // DB_DEPTH_BOUNDS_MAX [all …]
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H A D | clearstate_evergreen.h | 26 0x00000000, // DB_RENDER_CONTROL 27 0x00000000, // DB_COUNT_CONTROL 28 0x00000000, // DB_DEPTH_VIEW 29 0x00000000, // DB_RENDER_OVERRIDE 30 0x00000000, // DB_RENDER_OVERRIDE2 31 0x00000000, // DB_HTILE_DATA_BASE 32 0, // HOLE 33 0, // HOLE 34 0, // HOLE 35 0, // HOLE [all …]
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H A D | clearstate_cayman.h | 28 0x00000000, // DB_RENDER_CONTROL 29 0x00000000, // DB_COUNT_CONTROL 30 0x00000000, // DB_DEPTH_VIEW 31 0x00000000, // DB_RENDER_OVERRIDE 32 0x00000000, // DB_RENDER_OVERRIDE2 33 0x00000000, // DB_HTILE_DATA_BASE 34 0, // HOLE 35 0, // HOLE 36 0, // HOLE 37 0, // HOLE [all …]
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/openbmc/linux/Documentation/devicetree/bindings/serial/ |
H A D | arm,mps2-uart.txt | 16 reg = <0x40004000 0x1000>; 17 interrupts = <0 1 12>;
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/openbmc/linux/Documentation/devicetree/bindings/sound/ |
H A D | st,stm32-spdifrx.yaml | 25 const: 0 71 #sound-dai-cells = <0>; 72 reg = <0x40004000 0x400>; 76 dmas = <&dmamux1 2 93 0x400 0x0>, 77 <&dmamux1 3 94 0x400 0x0>; 79 pinctrl-0 = <&spdifrx_pins>;
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/openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/ |
H A D | cpu.h | 12 #define SLC_NAND_BASE 0x20020000 /* SLC NAND Flash registers base */ 13 #define SSP0_BASE 0x20084000 /* SSP0 registers base */ 14 #define SD_CARD_BASE 0x20098000 /* SD card interface registers base */ 15 #define MLC_NAND_BASE 0x200A8000 /* MLC NAND Flash registers base */ 16 #define DMA_BASE 0x31000000 /* DMA controller registers base */ 17 #define USB_BASE 0x31020000 /* USB registers base */ 18 #define LCD_BASE 0x31040000 /* LCD registers base */ 19 #define ETHERNET_BASE 0x31060000 /* Ethernet registers base */ 20 #define EMC_BASE 0x31080000 /* EMC configuration registers base */ 23 #define CLK_PM_BASE 0x40004000 /* System control registers base */ [all …]
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/openbmc/qemu/hw/arm/ |
H A D | mps2.c | 130 memory_region_init_alias(mr, NULL, name, orig, 0, in make_ram_alias() 166 * 0x21000000 .. 0x21ffffff : PSRAM (16MB) in mps2_common_init() 168 * 0x00000000 .. 0x003fffff : ZBT SSRAM1 in mps2_common_init() 169 * 0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1 in mps2_common_init() 170 * 0x20000000 .. 0x203fffff : ZBT SSRAM 2&3 in mps2_common_init() 171 * 0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3 in mps2_common_init() 173 * 0x01000000 .. 0x01003fff : block RAM (16K) in mps2_common_init() 174 * 0x01004000 .. 0x01007fff : mirror of above in mps2_common_init() 175 * 0x01008000 .. 0x0100bfff : mirror of above in mps2_common_init() 176 * 0x0100c000 .. 0x0100ffff : mirror of above in mps2_common_init() [all …]
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H A D | msf2-soc.c | 35 #define MSF2_TIMER_BASE 0x40004000 36 #define MSF2_SYSREG_BASE 0x40038000 37 #define MSF2_EMAC_BASE 0x40041000 39 #define ENVM_BASE_ADDRESS 0x60000000 41 #define SRAM_BASE_ADDRESS 0x20000000 54 static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 }; 55 static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 }; 72 for (i = 0; i < MSF2_NUM_SPIS; i++) { in m2sxxx_soc_initfn() 78 s->m3clk = qdev_init_clock_in(DEVICE(obj), "m3clk", NULL, NULL, 0); in m2sxxx_soc_initfn() 79 s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk", NULL, NULL, 0); in m2sxxx_soc_initfn() [all …]
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H A D | stm32f405_soc.c | 33 #define RCC_ADDR 0x40023800 34 #define SYSCFG_ADD 0x40013800 35 static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800, 36 0x40004C00, 0x40005000, 0x40011400, 37 0x40007800, 0x40007C00 }; 39 static const uint32_t timer_addr[] = { 0x40000000, 0x40000400, 40 0x40000800, 0x40000C00 }; 41 static const uint32_t adc_addr[] = { 0x40012000, 0x40012100, 0x40012200, 42 0x40012300, 0x40012400, 0x40012500 }; 43 static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00, [all …]
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H A D | stm32l4x5_soc.c | 36 #define FLASH_BASE_ADDRESS 0x08000000 37 #define SRAM1_BASE_ADDRESS 0x20000000 39 #define SRAM2_BASE_ADDRESS 0x10000000 42 #define EXTI_ADDR 0x40010400 43 #define SYSCFG_ADDR 0x40010000 53 6, /* GPIO[0] */ 81 #define RCC_BASE_ADDRESS 0x40021000 114 { 0x48000000, 0xABFFFFFF, 0x0C000000, 0x64000000 }, 115 { 0x48000400, 0xFFFFFEBF, 0x00000000, 0x00000100 }, 116 { 0x48000800, 0xFFFFFFFF, 0x00000000, 0x00000000 }, [all …]
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H A D | armsse.c | 54 int irq; /* NO_IRQ, or 0..NUM_SSE_IRQS-1, or NMI_0 or NMI_1 */ 85 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), 86 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), 87 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), 88 DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8), 89 DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8), 98 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), 99 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false), 100 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false), 103 DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8), [all …]
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/openbmc/linux/arch/sparc/ |
H A D | Kconfig | 387 default 0x40004000 391 This address is normally the base address of main memory + 0x4000. 395 default 0x00080000 404 default 0xf0004000
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/openbmc/linux/drivers/gpu/drm/i915/gt/ |
H A D | gen9_renderstate.c | 11 0x000007a8, 12 0x000007b4, 13 0x000007bc, 14 0x000007cc, 19 0x7a000004, 20 0x01000000, 21 0x00000000, 22 0x00000000, 23 0x00000000, 24 0x00000000, [all …]
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H A D | gen8_renderstate.c | 11 0x00000798, 12 0x000007a4, 13 0x000007ac, 14 0x000007bc, 19 0x7a000004, 20 0x01000000, 21 0x00000000, 22 0x00000000, 23 0x00000000, 24 0x00000000, [all …]
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/openbmc/linux/arch/arm/boot/dts/nxp/lpc/ |
H A D | lpc32xx.dtsi | 20 #size-cells = <0>; 22 cpu@0 { 25 reg = <0x0>; 32 #clock-cells = <0>; 39 #clock-cells = <0>; 49 ranges = <0x00000000 0x00000000 0x10000000>, 50 <0x20000000 0x20000000 0x30000000>, 51 <0xe0000000 0xe0000000 0x04000000>; 55 reg = <0x08000000 0x20000>; 59 ranges = <0x00000000 0x08000000 0x20000>; [all …]
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H A D | lpc18xx.dtsi | 19 #define LPC_PIN(port, pin) (0x##port * 32 + pin) 28 #size-cells = <0>; 30 cpu@0 { 33 reg = <0x0>; 41 #clock-cells = <0>; 47 #clock-cells = <0>; 53 #clock-cells = <0>; 54 clock-frequency = <0>; 60 #clock-cells = <0>; 61 clock-frequency = <0>; [all …]
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/openbmc/linux/arch/arm/mach-lpc32xx/ |
H A D | lpc32xx.h | 17 * AHB 0 physical base addresses 19 #define LPC32XX_SLC_BASE 0x20020000 20 #define LPC32XX_SSP0_BASE 0x20084000 21 #define LPC32XX_SPI1_BASE 0x20088000 22 #define LPC32XX_SSP1_BASE 0x2008C000 23 #define LPC32XX_SPI2_BASE 0x20090000 24 #define LPC32XX_I2S0_BASE 0x20094000 25 #define LPC32XX_SD_BASE 0x20098000 26 #define LPC32XX_I2S1_BASE 0x2009C000 27 #define LPC32XX_MLC_BASE 0x200A8000 [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | stm32mp157c.dtsi | 16 #size-cells = <0>; 18 cpu0: cpu@0 { 21 reg = <0>; 34 cpu_off = <0x84000002>; 35 cpu_on = <0x84000003>; 64 reg = <0xa0021000 0x1000>, 65 <0xa0022000 0x2000>; 79 #clock-cells = <0>; 85 #clock-cells = <0>; 91 #clock-cells = <0>; [all …]
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