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12

/openbmc/qemu/target/m68k/
H A Dsoftfloat_fpsp_tables.h26 make_floatx80_init(0x3FFE, 0xFE03F80FE03F80FE),
27 make_floatx80_init(0x3FF7, 0xFF015358833C47E2),
28 make_floatx80_init(0x3FFE, 0xFA232CF252138AC0),
29 make_floatx80_init(0x3FF9, 0xBDC8D83EAD88D549),
30 make_floatx80_init(0x3FFE, 0xF6603D980F6603DA),
31 make_floatx80_init(0x3FFA, 0x9CF43DCFF5EAFD48),
32 make_floatx80_init(0x3FFE, 0xF2B9D6480F2B9D65),
33 make_floatx80_init(0x3FFA, 0xDA16EB88CB8DF614),
34 make_floatx80_init(0x3FFE, 0xEF2EB71FC4345238),
35 make_floatx80_init(0x3FFB, 0x8B29B7751BD70743),
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_scl_filters.c31 // <sharpness> = 0
37 0x1000, 0x0000,
38 0x0FF0, 0x0010,
39 0x0FB0, 0x0050,
40 0x0F34, 0x00CC,
41 0x0E68, 0x0198,
42 0x0D44, 0x02BC,
43 0x0BC4, 0x043C,
44 0x09FC, 0x0604,
45 0x0800, 0x0800
[all …]
/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zc1232-revA.dts30 memory@0 {
32 reg = <0x0 0x0 0x0 0x80000000>;
42 flash@0 {
46 reg = <0x0>;
56 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
57 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
58 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
59 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
60 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
61 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
[all …]
H A Dzynqmp-zc1751-xm017-dc3.dts37 memory@0 {
39 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
44 #clock-cells = <0>;
50 #clock-cells = <0>;
91 phy0: ethernet-phy@0 { /* VSC8211 */
92 reg = <0>;
107 reg = <0x20>;
115 reg = <0x68>;
146 ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
147 ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
[all …]
H A Dzynqmp-sck-kv-g-revA.dtso25 si5332_0: si5332-0 { /* u17 */
27 #clock-cells = <0>;
33 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #clock-cells = <0>;
51 #clock-cells = <0>;
57 #clock-cells = <0>;
64 #size-cells = <0>;
66 pinctrl-0 = <&pinctrl_i2c1_default>;
71 /* u14 - 0x40 - ina260 */
[all …]
H A Dzynqmp-zc1751-xm015-dc1.dts39 memory@0 {
41 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
46 #clock-cells = <0>;
52 #clock-cells = <0>;
58 #clock-cells = <0>;
100 pinctrl-0 = <&pinctrl_gem3_default>;
101 phy0: ethernet-phy@0 {
102 reg = <0>;
109 pinctrl-0 = <&pinctrl_gpio_default>;
120 pinctrl-0 = <&pinctrl_i2c1_default>;
[all …]
H A Dzynqmp-zcu104-revC.dts41 memory@0 {
43 reg = <0x0 0x0 0x0 0x80000000>;
48 io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
53 #clock-cells = <0>;
59 #clock-cells = <0>;
65 #clock-cells = <0>;
73 pinctrl-0 = <&pinctrl_can1_default>;
117 pinctrl-0 = <&pinctrl_gem3_default>;
120 #size-cells = <0>;
124 reg = <0xc>;
[all …]
H A Dzynqmp-zcu104-revA.dts41 memory@0 {
43 reg = <0x0 0x0 0x0 0x80000000>;
48 #clock-cells = <0>;
54 #clock-cells = <0>;
60 #clock-cells = <0>;
68 pinctrl-0 = <&pinctrl_can1_default>;
112 pinctrl-0 = <&pinctrl_gem3_default>;
115 #size-cells = <0>;
119 reg = <0xc>;
120 ti,rx-internal-delay = <0x8>;
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vce/
H A Dvce_2_0_sh_mask.h27 #define VCE_STATUS__JOB_BUSY_MASK 0x1
28 #define VCE_STATUS__JOB_BUSY__SHIFT 0x0
29 #define VCE_STATUS__VCPU_REPORT_MASK 0xfe
30 #define VCE_STATUS__VCPU_REPORT__SHIFT 0x1
31 #define VCE_STATUS__UENC_BUSY_MASK 0x100
32 #define VCE_STATUS__UENC_BUSY__SHIFT 0x8
33 #define VCE_VCPU_CNTL__CLK_EN_MASK 0x1
34 #define VCE_VCPU_CNTL__CLK_EN__SHIFT 0x0
35 #define VCE_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x40000
36 #define VCE_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x12
[all …]
H A Dvce_3_0_sh_mask.h27 #define VCE_STATUS__JOB_BUSY_MASK 0x1
28 #define VCE_STATUS__JOB_BUSY__SHIFT 0x0
29 #define VCE_STATUS__VCPU_REPORT_MASK 0xfe
30 #define VCE_STATUS__VCPU_REPORT__SHIFT 0x1
31 #define VCE_STATUS__UENC_BUSY_MASK 0x100
32 #define VCE_STATUS__UENC_BUSY__SHIFT 0x8
33 #define VCE_STATUS__VCE_CONFIGURATION_MASK 0xc00000
34 #define VCE_STATUS__VCE_CONFIGURATION__SHIFT 0x16
35 #define VCE_STATUS__VCE_INSTANCE_ID_MASK 0x3000000
36 #define VCE_STATUS__VCE_INSTANCE_ID__SHIFT 0x18
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp-zc1232-revA.dts31 memory@0 {
33 reg = <0x0 0x0 0x0 0x80000000>;
43 flash@0 {
47 reg = <0x0>;
53 reg = <0x0 0x100000>;
57 reg = <0x100000 0x500000>;
61 reg = <0x600000 0x20000>;
65 reg = <0x620000 0x5E0000>;
73 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
74 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
[all …]
H A Dzynqmp-zc1751-xm015-dc1.dts36 memory@0 {
38 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
78 phy0: phy@0 {
79 reg = <0>;
97 reg = <0x55>;
103 flash@0 {
107 reg = <0x0>;
113 reg = <0x0 0x100000>;
117 reg = <0x100000 0x500000>;
121 reg = <0x600000 0x20000>;
[all …]
H A Dzynqmp-zc1751-xm017-dc3.dts37 memory@0 {
39 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
79 phy0: phy@0 { /* VSC8211 */
80 reg = <0>;
95 reg = <0x20>;
103 reg = <0x68>;
119 partition@0 { /* for testing purpose */
121 reg = <0x0 0x0 0x400000>;
125 reg = <0x0 0x400000 0x1400000>;
129 reg = <0x0 0x1800000 0x400000>;
[all …]
H A Dzynqmp-zcu104-revC.dts40 memory@0 {
42 reg = <0x0 0x0 0x0 0x80000000>;
59 reg = <0xc>;
60 ti,rx-internal-delay = <0x8>;
61 ti,tx-internal-delay = <0xa>;
62 ti,fifo-depth = <0x1>;
80 reg = <0x20>;
86 * 0 - IRPS5401_ALERT_B
101 #size-cells = <0>;
102 reg = <0x74>;
[all …]
H A Dzynqmp-zcu104-revA.dts39 memory@0 {
41 reg = <0x0 0x0 0x0 0x80000000>;
58 reg = <0xc>;
59 ti,rx-internal-delay = <0x8>;
60 ti,tx-internal-delay = <0xa>;
61 ti,fifo-depth = <0x1>;
81 #size-cells = <0>;
82 reg = <0x74>;
83 i2c@0 {
85 #size-cells = <0>;
[all …]
H A Dzynqmp-zcu111-revA.dts41 memory@0 {
43 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
110 reg = <0xc>;
111 ti,rx-internal-delay = <0x8>;
112 ti,tx-internal-delay = <0xa>;
113 ti,fifo-depth = <0x1>;
131 reg = <0x20>;
137 * 0 - MAX6643_OT_B
155 #size-cells = <0>;
156 reg = <0x75>;
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/include/
H A Dsoc.h9 #define SI_ENUM_BASE_DEFAULT 0x18000000
12 #define SICF_BIST_EN 0x8000
13 #define SICF_PME_EN 0x4000
14 #define SICF_CORE_BITS 0x3ffc
15 #define SICF_FGC 0x0002
16 #define SICF_CLOCK_EN 0x0001
19 #define SISF_BIST_DONE 0x8000
20 #define SISF_BIST_ERROR 0x4000
21 #define SISF_GATED_CLK 0x2000
22 #define SISF_DMA64 0x1000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/hwinfo/
H A Dloongson,ls2k-chipid.yaml36 reg = <0x1fe00000 0x3ffc>;
/openbmc/linux/arch/arm/mach-omap1/
H A Dserial.h28 #define OMAP_UART_INFO_OFS 0x3ffc
31 #define OMAP7XX_PORT_SHIFT 0
/openbmc/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Ddcore0_tpc0_eml_stm_regs.h23 #define mmDCORE0_TPC0_EML_STM_STMDMASTARTR 0x3C04
25 #define mmDCORE0_TPC0_EML_STM_STMDMASTOPR 0x3C08
27 #define mmDCORE0_TPC0_EML_STM_STMDMASTATR 0x3C0C
29 #define mmDCORE0_TPC0_EML_STM_STMDMACTLR 0x3C10
31 #define mmDCORE0_TPC0_EML_STM_STMDMAIDR 0x3CFC
33 #define mmDCORE0_TPC0_EML_STM_STMHEER 0x3D00
35 #define mmDCORE0_TPC0_EML_STM_STMHETER 0x3D20
37 #define mmDCORE0_TPC0_EML_STM_STMHEBSR 0x3D60
39 #define mmDCORE0_TPC0_EML_STM_STMHEMCR 0x3D64
41 #define mmDCORE0_TPC0_EML_STM_STMHEEXTMUXR 0x3D68
[all …]
/openbmc/qemu/target/i386/tcg/
H A Dfpu_helper.c40 #define FPU_RC_NEAR 0x000
41 #define FPU_RC_DOWN 0x400
42 #define FPU_RC_UP 0x800
43 #define FPU_RC_CHOP 0xc00
48 #define MAXEXPD 0x7fff
50 #define EXPD(fp) (fp.l.upper & 0x7fff)
51 #define SIGND(fp) ((fp.l.upper) & 0x8000)
53 #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) | EXPBIAS
55 #define FPUS_IE (1 << 0)
65 #define FPUC_EM 0x3f
[all …]
/openbmc/linux/arch/powerpc/platforms/cell/spufs/
H A Dspu_restore_crt0.S19 .space SIZEOF_SPU_SPILL_REGS, 0x0
28 il $0, 0
30 stqd $0, 0($SP)
40 brsl $0, main
52 .balignl 16, 0x40200000
54 lqd $16, 0($3)
58 andi $5, $4, 0x7F
64 lqa $0, regs_spill + 0
87 * following the 'stop 0x3ffc' have been modified at run
97 stop 0
[all …]
/openbmc/linux/drivers/net/ethernet/ezchip/
H A Dnps_enet.h10 #define NPS_ENET_NAPI_POLL_WEIGHT 0x2
11 #define NPS_ENET_MAX_FRAME_LENGTH 0x3FFF
12 #define NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR 0x7
13 #define NPS_ENET_GE_MAC_CFG_0_RX_IFG 0x5
14 #define NPS_ENET_GE_MAC_CFG_0_TX_IFG 0xC
15 #define NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN 0x7
16 #define NPS_ENET_GE_MAC_CFG_2_STAT_EN 0x3
17 #define NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH 0x14
18 #define NPS_ENET_GE_MAC_CFG_3_MAX_LEN 0x3FFC
20 #define NPS_ENET_DISABLE 0
[all …]
/openbmc/linux/include/linux/bcma/
H A Dbcma_regs.h7 #define BCMA_CLKCTLST 0x01E0 /* Clock control and status */
8 #define BCMA_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */
9 #define BCMA_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */
10 #define BCMA_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */
11 #define BCMA_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
12 #define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
13 #define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
14 #define BCMA_CLKCTLST_HQCLKREQ 0x00000040 /* HQ Clock */
15 #define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
17 #define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dspu_csa.h23 #define SPU_SAVE_COMPLETE 0x3FFB
24 #define SPU_RESTORE_COMPLETE 0x3FFC
43 #define SPU_DECR_STATUS_RUNNING 0x1
44 #define SPU_DECR_STATUS_WRAPPED 0x2

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