1683595a6SAlex Deucher /* 2683595a6SAlex Deucher * VCE_2_0 Register documentation 3683595a6SAlex Deucher * 4683595a6SAlex Deucher * Copyright (C) 2014 Advanced Micro Devices, Inc. 5683595a6SAlex Deucher * 6683595a6SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 7683595a6SAlex Deucher * copy of this software and associated documentation files (the "Software"), 8683595a6SAlex Deucher * to deal in the Software without restriction, including without limitation 9683595a6SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10683595a6SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 11683595a6SAlex Deucher * Software is furnished to do so, subject to the following conditions: 12683595a6SAlex Deucher * 13683595a6SAlex Deucher * The above copyright notice and this permission notice shall be included 14683595a6SAlex Deucher * in all copies or substantial portions of the Software. 15683595a6SAlex Deucher * 16683595a6SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17683595a6SAlex Deucher * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18683595a6SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19683595a6SAlex Deucher * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20683595a6SAlex Deucher * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21683595a6SAlex Deucher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22683595a6SAlex Deucher */ 23683595a6SAlex Deucher 24683595a6SAlex Deucher #ifndef VCE_2_0_SH_MASK_H 25683595a6SAlex Deucher #define VCE_2_0_SH_MASK_H 26683595a6SAlex Deucher 27683595a6SAlex Deucher #define VCE_STATUS__JOB_BUSY_MASK 0x1 28683595a6SAlex Deucher #define VCE_STATUS__JOB_BUSY__SHIFT 0x0 29683595a6SAlex Deucher #define VCE_STATUS__VCPU_REPORT_MASK 0xfe 30683595a6SAlex Deucher #define VCE_STATUS__VCPU_REPORT__SHIFT 0x1 31683595a6SAlex Deucher #define VCE_STATUS__UENC_BUSY_MASK 0x100 32683595a6SAlex Deucher #define VCE_STATUS__UENC_BUSY__SHIFT 0x8 33683595a6SAlex Deucher #define VCE_VCPU_CNTL__CLK_EN_MASK 0x1 34683595a6SAlex Deucher #define VCE_VCPU_CNTL__CLK_EN__SHIFT 0x0 35683595a6SAlex Deucher #define VCE_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x40000 36683595a6SAlex Deucher #define VCE_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x12 37683595a6SAlex Deucher #define VCE_VCPU_CACHE_OFFSET0__OFFSET_MASK 0xfffffff 38683595a6SAlex Deucher #define VCE_VCPU_CACHE_OFFSET0__OFFSET__SHIFT 0x0 39683595a6SAlex Deucher #define VCE_VCPU_CACHE_SIZE0__SIZE_MASK 0xffffff 40683595a6SAlex Deucher #define VCE_VCPU_CACHE_SIZE0__SIZE__SHIFT 0x0 41683595a6SAlex Deucher #define VCE_VCPU_CACHE_OFFSET1__OFFSET_MASK 0xfffffff 42683595a6SAlex Deucher #define VCE_VCPU_CACHE_OFFSET1__OFFSET__SHIFT 0x0 43683595a6SAlex Deucher #define VCE_VCPU_CACHE_SIZE1__SIZE_MASK 0xffffff 44683595a6SAlex Deucher #define VCE_VCPU_CACHE_SIZE1__SIZE__SHIFT 0x0 45683595a6SAlex Deucher #define VCE_VCPU_CACHE_OFFSET2__OFFSET_MASK 0xfffffff 46683595a6SAlex Deucher #define VCE_VCPU_CACHE_OFFSET2__OFFSET__SHIFT 0x0 47683595a6SAlex Deucher #define VCE_VCPU_CACHE_SIZE2__SIZE_MASK 0xffffff 48683595a6SAlex Deucher #define VCE_VCPU_CACHE_SIZE2__SIZE__SHIFT 0x0 49683595a6SAlex Deucher #define VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK 0x1 50683595a6SAlex Deucher #define VCE_SOFT_RESET__ECPU_SOFT_RESET__SHIFT 0x0 51683595a6SAlex Deucher #define VCE_RB_BASE_LO2__RB_BASE_LO_MASK 0xffffffc0 52683595a6SAlex Deucher #define VCE_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6 53683595a6SAlex Deucher #define VCE_RB_BASE_HI2__RB_BASE_HI_MASK 0xffffffff 54683595a6SAlex Deucher #define VCE_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0 55683595a6SAlex Deucher #define VCE_RB_SIZE2__RB_SIZE_MASK 0x7ffff0 56683595a6SAlex Deucher #define VCE_RB_SIZE2__RB_SIZE__SHIFT 0x4 57683595a6SAlex Deucher #define VCE_RB_RPTR2__RB_RPTR_MASK 0x7ffff0 58683595a6SAlex Deucher #define VCE_RB_RPTR2__RB_RPTR__SHIFT 0x4 59683595a6SAlex Deucher #define VCE_RB_WPTR2__RB_WPTR_MASK 0x7ffff0 60683595a6SAlex Deucher #define VCE_RB_WPTR2__RB_WPTR__SHIFT 0x4 61683595a6SAlex Deucher #define VCE_RB_BASE_LO__RB_BASE_LO_MASK 0xffffffc0 62683595a6SAlex Deucher #define VCE_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 63683595a6SAlex Deucher #define VCE_RB_BASE_HI__RB_BASE_HI_MASK 0xffffffff 64683595a6SAlex Deucher #define VCE_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 65683595a6SAlex Deucher #define VCE_RB_SIZE__RB_SIZE_MASK 0x7ffff0 66683595a6SAlex Deucher #define VCE_RB_SIZE__RB_SIZE__SHIFT 0x4 67683595a6SAlex Deucher #define VCE_RB_RPTR__RB_RPTR_MASK 0x7ffff0 68683595a6SAlex Deucher #define VCE_RB_RPTR__RB_RPTR__SHIFT 0x4 69683595a6SAlex Deucher #define VCE_RB_WPTR__RB_WPTR_MASK 0x7ffff0 70683595a6SAlex Deucher #define VCE_RB_WPTR__RB_WPTR__SHIFT 0x4 71683595a6SAlex Deucher #define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK 0x1 72683595a6SAlex Deucher #define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON__SHIFT 0x0 73683595a6SAlex Deucher #define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK 0x2 74683595a6SAlex Deucher #define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON__SHIFT 0x1 75683595a6SAlex Deucher #define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK 0x4 76683595a6SAlex Deucher #define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON__SHIFT 0x2 77683595a6SAlex Deucher #define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK 0x8 78683595a6SAlex Deucher #define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN__SHIFT 0x3 79683595a6SAlex Deucher #define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK 0x8 80683595a6SAlex Deucher #define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT__SHIFT 0x3 81683595a6SAlex Deucher #define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK_MASK 0x8 82683595a6SAlex Deucher #define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK__SHIFT 0x3 83683595a6SAlex Deucher #define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR_MASK 0xffffffff 84683595a6SAlex Deucher #define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR__SHIFT 0x0 85683595a6SAlex Deucher #define VCE_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100 86683595a6SAlex Deucher #define VCE_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 87683595a6SAlex Deucher #define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP_MASK 0x3 88683595a6SAlex Deucher #define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP__SHIFT 0x0 89683595a6SAlex Deucher #define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000 90683595a6SAlex Deucher #define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 91683595a6SAlex Deucher #define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x3 92683595a6SAlex Deucher #define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x0 93683595a6SAlex Deucher #define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP_MASK 0x3ffc 94683595a6SAlex Deucher #define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP__SHIFT 0x2 95683595a6SAlex Deucher #define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP_MASK 0x3 96683595a6SAlex Deucher #define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP__SHIFT 0x0 97683595a6SAlex Deucher #define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP_MASK 0x3ffc 98683595a6SAlex Deucher #define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP__SHIFT 0x2 99683595a6SAlex Deucher #define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP_MASK 0xff 100683595a6SAlex Deucher #define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP__SHIFT 0x0 101683595a6SAlex Deucher #define VCE_LMI_CACHE_CTRL__VCPU_EN_MASK 0x1 102683595a6SAlex Deucher #define VCE_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x0 103683595a6SAlex Deucher 104683595a6SAlex Deucher #endif /* VCE_2_0_SH_MASK_H */ 105