1c481a680SAlex Deucher /* 2c481a680SAlex Deucher * VCE_3_0 Register documentation 3c481a680SAlex Deucher * 4c481a680SAlex Deucher * Copyright (C) 2014 Advanced Micro Devices, Inc. 5c481a680SAlex Deucher * 6c481a680SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 7c481a680SAlex Deucher * copy of this software and associated documentation files (the "Software"), 8c481a680SAlex Deucher * to deal in the Software without restriction, including without limitation 9c481a680SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10c481a680SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 11c481a680SAlex Deucher * Software is furnished to do so, subject to the following conditions: 12c481a680SAlex Deucher * 13c481a680SAlex Deucher * The above copyright notice and this permission notice shall be included 14c481a680SAlex Deucher * in all copies or substantial portions of the Software. 15c481a680SAlex Deucher * 16c481a680SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17c481a680SAlex Deucher * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18c481a680SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19c481a680SAlex Deucher * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20c481a680SAlex Deucher * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21c481a680SAlex Deucher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22c481a680SAlex Deucher */ 23c481a680SAlex Deucher 24c481a680SAlex Deucher #ifndef VCE_3_0_SH_MASK_H 25c481a680SAlex Deucher #define VCE_3_0_SH_MASK_H 26c481a680SAlex Deucher 27c481a680SAlex Deucher #define VCE_STATUS__JOB_BUSY_MASK 0x1 28c481a680SAlex Deucher #define VCE_STATUS__JOB_BUSY__SHIFT 0x0 29c481a680SAlex Deucher #define VCE_STATUS__VCPU_REPORT_MASK 0xfe 30c481a680SAlex Deucher #define VCE_STATUS__VCPU_REPORT__SHIFT 0x1 31c481a680SAlex Deucher #define VCE_STATUS__UENC_BUSY_MASK 0x100 32c481a680SAlex Deucher #define VCE_STATUS__UENC_BUSY__SHIFT 0x8 33c481a680SAlex Deucher #define VCE_STATUS__VCE_CONFIGURATION_MASK 0xc00000 34c481a680SAlex Deucher #define VCE_STATUS__VCE_CONFIGURATION__SHIFT 0x16 35c481a680SAlex Deucher #define VCE_STATUS__VCE_INSTANCE_ID_MASK 0x3000000 36c481a680SAlex Deucher #define VCE_STATUS__VCE_INSTANCE_ID__SHIFT 0x18 37c481a680SAlex Deucher #define VCE_VCPU_CNTL__CLK_EN_MASK 0x1 38c481a680SAlex Deucher #define VCE_VCPU_CNTL__CLK_EN__SHIFT 0x0 39c481a680SAlex Deucher #define VCE_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x40000 40c481a680SAlex Deucher #define VCE_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x12 41c481a680SAlex Deucher #define VCE_VCPU_CACHE_OFFSET0__OFFSET_MASK 0xfffffff 42c481a680SAlex Deucher #define VCE_VCPU_CACHE_OFFSET0__OFFSET__SHIFT 0x0 43c481a680SAlex Deucher #define VCE_VCPU_CACHE_SIZE0__SIZE_MASK 0xffffff 44c481a680SAlex Deucher #define VCE_VCPU_CACHE_SIZE0__SIZE__SHIFT 0x0 45c481a680SAlex Deucher #define VCE_VCPU_CACHE_OFFSET1__OFFSET_MASK 0xfffffff 46c481a680SAlex Deucher #define VCE_VCPU_CACHE_OFFSET1__OFFSET__SHIFT 0x0 47c481a680SAlex Deucher #define VCE_VCPU_CACHE_SIZE1__SIZE_MASK 0xffffff 48c481a680SAlex Deucher #define VCE_VCPU_CACHE_SIZE1__SIZE__SHIFT 0x0 49c481a680SAlex Deucher #define VCE_VCPU_CACHE_OFFSET2__OFFSET_MASK 0xfffffff 50c481a680SAlex Deucher #define VCE_VCPU_CACHE_OFFSET2__OFFSET__SHIFT 0x0 51c481a680SAlex Deucher #define VCE_VCPU_CACHE_SIZE2__SIZE_MASK 0xffffff 52c481a680SAlex Deucher #define VCE_VCPU_CACHE_SIZE2__SIZE__SHIFT 0x0 53c481a680SAlex Deucher #define VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK 0x1 54c481a680SAlex Deucher #define VCE_SOFT_RESET__ECPU_SOFT_RESET__SHIFT 0x0 55c481a680SAlex Deucher #define VCE_RB_BASE_LO2__RB_BASE_LO_MASK 0xffffffc0 56c481a680SAlex Deucher #define VCE_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6 57c481a680SAlex Deucher #define VCE_RB_BASE_HI2__RB_BASE_HI_MASK 0xffffffff 58c481a680SAlex Deucher #define VCE_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0 59c481a680SAlex Deucher #define VCE_RB_SIZE2__RB_SIZE_MASK 0x7ffff0 60c481a680SAlex Deucher #define VCE_RB_SIZE2__RB_SIZE__SHIFT 0x4 61c481a680SAlex Deucher #define VCE_RB_RPTR2__RB_RPTR_MASK 0x7ffff0 62c481a680SAlex Deucher #define VCE_RB_RPTR2__RB_RPTR__SHIFT 0x4 63c481a680SAlex Deucher #define VCE_RB_WPTR2__RB_WPTR_MASK 0x7ffff0 64c481a680SAlex Deucher #define VCE_RB_WPTR2__RB_WPTR__SHIFT 0x4 65c481a680SAlex Deucher #define VCE_RB_BASE_LO__RB_BASE_LO_MASK 0xffffffc0 66c481a680SAlex Deucher #define VCE_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 67c481a680SAlex Deucher #define VCE_RB_BASE_HI__RB_BASE_HI_MASK 0xffffffff 68c481a680SAlex Deucher #define VCE_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 69c481a680SAlex Deucher #define VCE_RB_SIZE__RB_SIZE_MASK 0x7ffff0 70c481a680SAlex Deucher #define VCE_RB_SIZE__RB_SIZE__SHIFT 0x4 71c481a680SAlex Deucher #define VCE_RB_RPTR__RB_RPTR_MASK 0x7ffff0 72c481a680SAlex Deucher #define VCE_RB_RPTR__RB_RPTR__SHIFT 0x4 73c481a680SAlex Deucher #define VCE_RB_WPTR__RB_WPTR_MASK 0x7ffff0 74c481a680SAlex Deucher #define VCE_RB_WPTR__RB_WPTR__SHIFT 0x4 75c481a680SAlex Deucher #define VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE_MASK 0x10000 76c481a680SAlex Deucher #define VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE__SHIFT 0x10 77c481a680SAlex Deucher #define VCE_RB_BASE_LO3__RB_BASE_LO_MASK 0xffffffc0 78c481a680SAlex Deucher #define VCE_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6 79c481a680SAlex Deucher #define VCE_RB_BASE_HI3__RB_BASE_HI_MASK 0xffffffff 80c481a680SAlex Deucher #define VCE_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0 81c481a680SAlex Deucher #define VCE_RB_SIZE3__RB_SIZE_MASK 0x7ffff0 82c481a680SAlex Deucher #define VCE_RB_SIZE3__RB_SIZE__SHIFT 0x4 83c481a680SAlex Deucher #define VCE_RB_RPTR3__RB_RPTR_MASK 0x7ffff0 84c481a680SAlex Deucher #define VCE_RB_RPTR3__RB_RPTR__SHIFT 0x4 85c481a680SAlex Deucher #define VCE_RB_WPTR3__RB_WPTR_MASK 0x7ffff0 86c481a680SAlex Deucher #define VCE_RB_WPTR3__RB_WPTR__SHIFT 0x4 87c481a680SAlex Deucher #define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK 0x1 88c481a680SAlex Deucher #define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON__SHIFT 0x0 89c481a680SAlex Deucher #define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK 0x2 90c481a680SAlex Deucher #define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON__SHIFT 0x1 91c481a680SAlex Deucher #define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK 0x4 92c481a680SAlex Deucher #define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON__SHIFT 0x2 93c481a680SAlex Deucher #define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK 0x8 94c481a680SAlex Deucher #define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN__SHIFT 0x3 95c481a680SAlex Deucher #define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK 0x8 96c481a680SAlex Deucher #define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT__SHIFT 0x3 97c481a680SAlex Deucher #define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK_MASK 0x8 98c481a680SAlex Deucher #define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK__SHIFT 0x3 99c481a680SAlex Deucher #define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR_MASK 0xffffffff 100c481a680SAlex Deucher #define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR__SHIFT 0x0 101c481a680SAlex Deucher #define VCE_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100 102c481a680SAlex Deucher #define VCE_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 103c481a680SAlex Deucher #define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP_MASK 0x3 104c481a680SAlex Deucher #define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP__SHIFT 0x0 105c481a680SAlex Deucher #define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000 106c481a680SAlex Deucher #define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 107c481a680SAlex Deucher #define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x3 108c481a680SAlex Deucher #define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x0 109c481a680SAlex Deucher #define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP_MASK 0x3ffc 110c481a680SAlex Deucher #define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP__SHIFT 0x2 111c481a680SAlex Deucher #define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP_MASK 0x3 112c481a680SAlex Deucher #define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP__SHIFT 0x0 113c481a680SAlex Deucher #define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP_MASK 0x3ffc 114c481a680SAlex Deucher #define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP__SHIFT 0x2 115c481a680SAlex Deucher #define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP_MASK 0xff 116c481a680SAlex Deucher #define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP__SHIFT 0x0 117c481a680SAlex Deucher #define VCE_LMI_CACHE_CTRL__VCPU_EN_MASK 0x1 118c481a680SAlex Deucher #define VCE_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x0 119c481a680SAlex Deucher 120c481a680SAlex Deucher #endif /* VCE_3_0_SH_MASK_H */ 121