/openbmc/u-boot/board/topic/zynq/zynq-topic-miamilite/ |
H A D | ps7_regs.txt | 1 0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 433 MHz (?) 2 0xf8000700 0x202 3 0xf8000704 0x202 4 0xf8000708 0x202 5 0xf800070c 0x202 6 0xf8000710 0x202 7 0xf8000714 0x202 8 0xf8000718 0x202 9 0xf800071c 0x200 10 0xf8000720 0x202 [all …]
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/openbmc/u-boot/board/topic/zynq/zynq-topic-miamiplus/ |
H A D | ps7_regs.txt | 1 0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 (433 MHz) 2 0xf8000700 0x1202 // MIO configuration 3 0xf8000704 0x1202 4 0xf8000708 0x202 5 0xf800070c 0x202 6 0xf8000710 0x202 7 0xf8000714 0x202 8 0xf8000718 0x202 9 0xf800071c 0x200 10 0xf8000720 0x202 [all …]
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/openbmc/u-boot/board/topic/zynq/zynq-topic-miami/ |
H A D | ps7_regs.txt | 1 0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 433 MHz (?) 2 0xf8000700 0x1210 // MIO configuration 3 0xf8000704 0x202 4 0xf8000708 0x202 5 0xf800070c 0x202 6 0xf8000710 0x202 7 0xf8000714 0x202 8 0xf8000718 0x202 9 0xf800071c 0x210 10 0xf8000720 0x202 [all …]
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/openbmc/linux/drivers/accel/habanalabs/goya/ |
H A D | goya_coresight.c | 18 #define SPMU_EVENT_TYPES_OFFSET 0x400 220 "Timeout while waiting for coresight, addr: 0x%llx, position: %d, up: %d\n", in goya_coresight_timeout() 225 return 0; in goya_coresight_timeout() 243 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); in goya_config_stm() 251 WREG32(base_reg + 0xE80, 0x80004); in goya_config_stm() 252 WREG32(base_reg + 0xD64, 7); in goya_config_stm() 253 WREG32(base_reg + 0xD60, 0); in goya_config_stm() 254 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask)); in goya_config_stm() 255 WREG32(base_reg + 0xD20, lower_32_bits(input->sp_mask)); in goya_config_stm() 256 WREG32(base_reg + 0xD60, 1); in goya_config_stm() [all …]
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/openbmc/linux/arch/arm/boot/dts/arm/ |
H A D | vexpress-v2p-ca5s.dts | 16 arm,hbi = <0x225>; 17 arm,vexpress,site = <0xf>; 36 #size-cells = <0>; 38 cpu@0 { 41 reg = <0>; 55 reg = <0x80000000 0x40000000>; 63 /* Chipselect 2 is physically at 0x18000000 */ 67 reg = <0x18000000 0x00800000>; 74 reg = <0x2a110000 0x1000>; 75 interrupts = <0 85 4>; [all …]
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/openbmc/linux/drivers/accel/habanalabs/gaudi/ |
H A D | gaudi_coresight.c | 17 #define SPMU_EVENT_TYPES_OFFSET 0x400 382 "Timeout while waiting for coresight, addr: 0x%llx, position: %d, up: %d\n", in gaudi_coresight_timeout() 387 return 0; in gaudi_coresight_timeout() 405 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); in gaudi_config_stm() 413 WREG32(base_reg + 0xE80, 0x80004); in gaudi_config_stm() 414 WREG32(base_reg + 0xD64, 7); in gaudi_config_stm() 415 WREG32(base_reg + 0xD60, 0); in gaudi_config_stm() 416 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask)); in gaudi_config_stm() 417 WREG32(base_reg + 0xD60, 1); in gaudi_config_stm() 418 WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask)); in gaudi_config_stm() [all …]
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/openbmc/linux/drivers/usb/host/ |
H A D | ssb-hcd.c | 45 if (dev->id.revision == 2 && dev->bus->chip_id == 0x5354) { in ssb_hcd_5354wa() 47 ssb_write32(dev, 0x894, 0x00fe00fe); in ssb_hcd_5354wa() 50 ssb_write32(dev, 0x89c, ssb_read32(dev, 0x89c) | 0x1); in ssb_hcd_5354wa() 65 ssb_write32(dev, 0x200, 0x7ff); in ssb_hcd_usb20wa() 68 ssb_write32(dev, 0x400, ssb_read32(dev, 0x400) & ~8); in ssb_hcd_usb20wa() 69 ssb_read32(dev, 0x400); in ssb_hcd_usb20wa() 72 ssb_write32(dev, 0x304, ssb_read32(dev, 0x304) & ~0x100); in ssb_hcd_usb20wa() 73 ssb_read32(dev, 0x304); in ssb_hcd_usb20wa() 84 u32 flags = 0; in ssb_hcd_init_chip() 109 memset(hci_res, 0, sizeof(hci_res)); in ssb_hcd_create_pdev() [all …]
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/openbmc/linux/drivers/hwtracing/coresight/ |
H A D | coresight-tpiu.c | 22 #define TPIU_SUPP_PORTSZ 0x000 23 #define TPIU_CURR_PORTSZ 0x004 24 #define TPIU_SUPP_TRIGMODES 0x100 25 #define TPIU_TRIG_CNTRVAL 0x104 26 #define TPIU_TRIG_MULT 0x108 27 #define TPIU_SUPP_TESTPATM 0x200 28 #define TPIU_CURR_TESTPATM 0x204 29 #define TPIU_TEST_PATREPCNTR 0x208 30 #define TPIU_FFSR 0x300 31 #define TPIU_FFCR 0x304 [all …]
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H A D | coresight-tmc.h | 16 #define TMC_RSZ 0x004 17 #define TMC_STS 0x00c 18 #define TMC_RRD 0x010 19 #define TMC_RRP 0x014 20 #define TMC_RWP 0x018 21 #define TMC_TRG 0x01c 22 #define TMC_CTL 0x020 23 #define TMC_RWD 0x024 24 #define TMC_MODE 0x028 25 #define TMC_LBUFLEVEL 0x02c [all …]
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/openbmc/u-boot/board/renesas/r7780mp/ |
H A D | r7780mp.h | 13 #define FPGA_BASE 0xa4000000 14 #define FPGA_IRLMSK (FPGA_BASE + 0x00) 15 #define FPGA_IRLMON (FPGA_BASE + 0x02) 16 #define FPGA_IRLPRI1 (FPGA_BASE + 0x04) 17 #define FPGA_IRLPRI2 (FPGA_BASE + 0x06) 18 #define FPGA_IRLPRI3 (FPGA_BASE + 0x08) 19 #define FPGA_IRLPRI4 (FPGA_BASE + 0x0A) 20 #define FPGA_RSTCTL (FPGA_BASE + 0x0C) 21 #define FPGA_PCIBD (FPGA_BASE + 0x0E) 22 #define FPGA_PCICD (FPGA_BASE + 0x10) [all …]
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/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/ |
H A D | dpu_hwio.h | 13 #define DISP_INTF_SEL 0x004 14 #define INTR_EN 0x010 15 #define INTR_STATUS 0x014 16 #define INTR_CLEAR 0x018 17 #define INTR2_EN 0x008 18 #define INTR2_STATUS 0x00c 19 #define SSPP_SPARE 0x028 20 #define INTR2_CLEAR 0x02c 21 #define HIST_INTR_EN 0x01c 22 #define HIST_INTR_STATUS 0x020 [all …]
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/openbmc/qemu/include/hw/timer/ |
H A D | nrf51_timer.h | 5 * + sysbus MMIO regions 0: GPIO registers 24 #define NRF51_TIMER_TASK_START 0x000 25 #define NRF51_TIMER_TASK_STOP 0x004 26 #define NRF51_TIMER_TASK_COUNT 0x008 27 #define NRF51_TIMER_TASK_CLEAR 0x00C 28 #define NRF51_TIMER_TASK_SHUTDOWN 0x010 29 #define NRF51_TIMER_TASK_CAPTURE_0 0x040 30 #define NRF51_TIMER_TASK_CAPTURE_3 0x04C 32 #define NRF51_TIMER_EVENT_COMPARE_0 0x140 33 #define NRF51_TIMER_EVENT_COMPARE_1 0x144 [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
H A D | grf_rk3036.h | 11 unsigned int reserved[0x2a]; 27 unsigned int reserved2[0x0a]; 29 unsigned int reserved3[0x05]; 73 unsigned int reserved13[0x10]; 76 unsigned int reserved14[0x10]; 80 check_member(rk3036_grf, sdmmc_det_cnt, 0x304);
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/openbmc/linux/include/dt-bindings/reset/ |
H A D | hisi,hi6220-resets.h | 9 #define PERIPH_RSTDIS0_MMC0 0x000 10 #define PERIPH_RSTDIS0_MMC1 0x001 11 #define PERIPH_RSTDIS0_MMC2 0x002 12 #define PERIPH_RSTDIS0_NANDC 0x003 13 #define PERIPH_RSTDIS0_USBOTG_BUS 0x004 14 #define PERIPH_RSTDIS0_POR_PICOPHY 0x005 15 #define PERIPH_RSTDIS0_USBOTG 0x006 16 #define PERIPH_RSTDIS0_USBOTG_32K 0x007 17 #define PERIPH_RSTDIS1_HIFI 0x100 18 #define PERIPH_RSTDIS1_DIGACODEC 0x105 [all …]
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/openbmc/qemu/include/hw/char/ |
H A D | nrf51_uart.h | 20 #define UART_SIZE 0x1000 25 REG32(UART_STARTRX, 0x000) 26 REG32(UART_STOPRX, 0x004) 27 REG32(UART_STARTTX, 0x008) 28 REG32(UART_STOPTX, 0x00C) 29 REG32(UART_SUSPEND, 0x01C) 31 REG32(UART_CTS, 0x100) 32 REG32(UART_NCTS, 0x104) 33 REG32(UART_RXDRDY, 0x108) 34 REG32(UART_TXDRDY, 0x11C) [all …]
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/openbmc/qemu/include/hw/misc/ |
H A D | nrf51_rng.h | 9 * + sysbus MMIO regions 0: Memory Region with tasks, events and registers 43 #define NRF51_RNG_SIZE 0x1000 45 #define NRF51_RNG_TASK_START 0x000 46 #define NRF51_RNG_TASK_STOP 0x004 47 #define NRF51_RNG_EVENT_VALRDY 0x100 48 #define NRF51_RNG_REG_SHORTS 0x200 49 #define NRF51_RNG_REG_SHORTS_VALRDY_STOP 0 50 #define NRF51_RNG_REG_INTEN 0x300 51 #define NRF51_RNG_REG_INTEN_VALRDY 0 52 #define NRF51_RNG_REG_INTENSET 0x304 [all …]
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/openbmc/linux/Documentation/devicetree/bindings/arm/ux500/ |
H A D | boards.txt | 51 reg = <0x80150000 0x2000>; 59 reg = <0xa0411000 0x1000>, 60 <0xa0410100 0x100>; 65 reg = <0xa0410000 0x100>; 70 reg = <0xa0410600 0x20>; 71 interrupts = <1 13 0x304>; /* IRQ level high per-CPU */ 79 #clock-cells = <0>;
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/openbmc/u-boot/arch/arm/include/asm/arch-meson/ |
H A D | clock-axg.h | 18 #define HHI_GP0_PLL_CNTL 0x40 19 #define HHI_GP0_PLL_CNTL2 0x44 20 #define HHI_GP0_PLL_CNTL3 0x48 21 #define HHI_GP0_PLL_CNTL4 0x4c 22 #define HHI_GP0_PLL_CNTL5 0x50 23 #define HHI_GP0_PLL_STS 0x54 24 #define HHI_GP0_PLL_CNTL1 0x58 25 #define HHI_HIFI_PLL_CNTL 0x80 26 #define HHI_HIFI_PLL_CNTL2 0x84 27 #define HHI_HIFI_PLL_CNTL3 0x88 [all …]
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/openbmc/linux/drivers/clk/meson/ |
H A D | axg.h | 19 #define HHI_GP0_PLL_CNTL 0x40 20 #define HHI_GP0_PLL_CNTL2 0x44 21 #define HHI_GP0_PLL_CNTL3 0x48 22 #define HHI_GP0_PLL_CNTL4 0x4c 23 #define HHI_GP0_PLL_CNTL5 0x50 24 #define HHI_GP0_PLL_STS 0x54 25 #define HHI_GP0_PLL_CNTL1 0x58 26 #define HHI_HIFI_PLL_CNTL 0x80 27 #define HHI_HIFI_PLL_CNTL2 0x84 28 #define HHI_HIFI_PLL_CNTL3 0x88 [all …]
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H A D | g12a.h | 20 #define HHI_MIPI_CNTL0 0x000 21 #define HHI_MIPI_CNTL1 0x004 22 #define HHI_MIPI_CNTL2 0x008 23 #define HHI_MIPI_STS 0x00C 24 #define HHI_GP0_PLL_CNTL0 0x040 25 #define HHI_GP0_PLL_CNTL1 0x044 26 #define HHI_GP0_PLL_CNTL2 0x048 27 #define HHI_GP0_PLL_CNTL3 0x04C 28 #define HHI_GP0_PLL_CNTL4 0x050 29 #define HHI_GP0_PLL_CNTL5 0x054 [all …]
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/openbmc/linux/include/linux/bcma/ |
H A D | bcma_driver_gmac_cmn.h | 7 #define BCMA_GMAC_CMN_STAG0 0x000 8 #define BCMA_GMAC_CMN_STAG1 0x004 9 #define BCMA_GMAC_CMN_STAG2 0x008 10 #define BCMA_GMAC_CMN_STAG3 0x00C 11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020 12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024 13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100 14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff 15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000 17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000 [all …]
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/openbmc/linux/sound/soc/tegra/ |
H A D | tegra186_asrc.h | 13 #define TEGRA186_ASRC_CFG 0x0 14 #define TEGRA186_ASRC_RATIO_INT_PART 0x4 15 #define TEGRA186_ASRC_RATIO_FRAC_PART 0x8 16 #define TEGRA186_ASRC_RATIO_LOCK_STATUS 0xc 17 #define TEGRA186_ASRC_MUTE_UNMUTE_DURATION 0x10 18 #define TEGRA186_ASRC_TX_THRESHOLD 0x14 19 #define TEGRA186_ASRC_RX_THRESHOLD 0x18 20 #define TEGRA186_ASRC_RATIO_COMP 0x1c 21 #define TEGRA186_ASRC_RX_STATUS 0x20 22 #define TEGRA186_ASRC_RX_CIF_CTRL 0x24 [all …]
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/openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imxrt1050-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000 17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0 18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0 19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1 20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0 21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0 22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0 24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0 25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0 26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1 [all …]
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/openbmc/u-boot/arch/arm/mach-davinci/include/mach/ |
H A D | psc_defs.h | 14 unsigned int pid; /* 0x000 */ 15 unsigned char rsvd0[16]; /* 0x004 */ 16 unsigned char rsvd1[4]; /* 0x014 */ 17 unsigned int inteval; /* 0x018 */ 18 unsigned char rsvd2[36]; /* 0x01C */ 19 unsigned int merrpr0; /* 0x040 */ 20 unsigned int merrpr1; /* 0x044 */ 21 unsigned char rsvd3[8]; /* 0x048 */ 22 unsigned int merrcr0; /* 0x050 */ 23 unsigned int merrcr1; /* 0x054 */ [all …]
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/openbmc/linux/drivers/media/common/b2c2/ |
H A D | flexcop-reg.h | 11 FLEXCOP_UNK = 0, 18 FC_UNK = 0, 32 FC_USB = 0, 47 #define fc_data_Tag_ID_DVB 0x3e 48 #define fc_data_Tag_ID_ATSC 0x3f 49 #define fc_data_Tag_ID_IDSB 0x8b 51 #define fc_key_code_default 0x1 52 #define fc_key_code_even 0x2 53 #define fc_key_code_odd 0x3 64 FC_WRITE = 0, [all …]
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