1*e65e175bSOded Gabbay // SPDX-License-Identifier: GPL-2.0
2*e65e175bSOded Gabbay
3*e65e175bSOded Gabbay /*
4*e65e175bSOded Gabbay * Copyright 2016-2019 HabanaLabs, Ltd.
5*e65e175bSOded Gabbay * All Rights Reserved.
6*e65e175bSOded Gabbay */
7*e65e175bSOded Gabbay
8*e65e175bSOded Gabbay #include "goyaP.h"
9*e65e175bSOded Gabbay #include "../include/goya/goya_coresight.h"
10*e65e175bSOded Gabbay #include "../include/goya/asic_reg/goya_regs.h"
11*e65e175bSOded Gabbay #include "../include/goya/asic_reg/goya_masks.h"
12*e65e175bSOded Gabbay
13*e65e175bSOded Gabbay #include <uapi/drm/habanalabs_accel.h>
14*e65e175bSOded Gabbay
15*e65e175bSOded Gabbay #define GOYA_PLDM_CORESIGHT_TIMEOUT_USEC (CORESIGHT_TIMEOUT_USEC * 100)
16*e65e175bSOded Gabbay
17*e65e175bSOded Gabbay #define SPMU_SECTION_SIZE DMA_CH_0_CS_SPMU_MAX_OFFSET
18*e65e175bSOded Gabbay #define SPMU_EVENT_TYPES_OFFSET 0x400
19*e65e175bSOded Gabbay #define SPMU_MAX_COUNTERS 6
20*e65e175bSOded Gabbay
21*e65e175bSOded Gabbay static u64 debug_stm_regs[GOYA_STM_LAST + 1] = {
22*e65e175bSOded Gabbay [GOYA_STM_CPU] = mmCPU_STM_BASE,
23*e65e175bSOded Gabbay [GOYA_STM_DMA_CH_0_CS] = mmDMA_CH_0_CS_STM_BASE,
24*e65e175bSOded Gabbay [GOYA_STM_DMA_CH_1_CS] = mmDMA_CH_1_CS_STM_BASE,
25*e65e175bSOded Gabbay [GOYA_STM_DMA_CH_2_CS] = mmDMA_CH_2_CS_STM_BASE,
26*e65e175bSOded Gabbay [GOYA_STM_DMA_CH_3_CS] = mmDMA_CH_3_CS_STM_BASE,
27*e65e175bSOded Gabbay [GOYA_STM_DMA_CH_4_CS] = mmDMA_CH_4_CS_STM_BASE,
28*e65e175bSOded Gabbay [GOYA_STM_DMA_MACRO_CS] = mmDMA_MACRO_CS_STM_BASE,
29*e65e175bSOded Gabbay [GOYA_STM_MME1_SBA] = mmMME1_SBA_STM_BASE,
30*e65e175bSOded Gabbay [GOYA_STM_MME3_SBB] = mmMME3_SBB_STM_BASE,
31*e65e175bSOded Gabbay [GOYA_STM_MME4_WACS2] = mmMME4_WACS2_STM_BASE,
32*e65e175bSOded Gabbay [GOYA_STM_MME4_WACS] = mmMME4_WACS_STM_BASE,
33*e65e175bSOded Gabbay [GOYA_STM_MMU_CS] = mmMMU_CS_STM_BASE,
34*e65e175bSOded Gabbay [GOYA_STM_PCIE] = mmPCIE_STM_BASE,
35*e65e175bSOded Gabbay [GOYA_STM_PSOC] = mmPSOC_STM_BASE,
36*e65e175bSOded Gabbay [GOYA_STM_TPC0_EML] = mmTPC0_EML_STM_BASE,
37*e65e175bSOded Gabbay [GOYA_STM_TPC1_EML] = mmTPC1_EML_STM_BASE,
38*e65e175bSOded Gabbay [GOYA_STM_TPC2_EML] = mmTPC2_EML_STM_BASE,
39*e65e175bSOded Gabbay [GOYA_STM_TPC3_EML] = mmTPC3_EML_STM_BASE,
40*e65e175bSOded Gabbay [GOYA_STM_TPC4_EML] = mmTPC4_EML_STM_BASE,
41*e65e175bSOded Gabbay [GOYA_STM_TPC5_EML] = mmTPC5_EML_STM_BASE,
42*e65e175bSOded Gabbay [GOYA_STM_TPC6_EML] = mmTPC6_EML_STM_BASE,
43*e65e175bSOded Gabbay [GOYA_STM_TPC7_EML] = mmTPC7_EML_STM_BASE
44*e65e175bSOded Gabbay };
45*e65e175bSOded Gabbay
46*e65e175bSOded Gabbay static u64 debug_etf_regs[GOYA_ETF_LAST + 1] = {
47*e65e175bSOded Gabbay [GOYA_ETF_CPU_0] = mmCPU_ETF_0_BASE,
48*e65e175bSOded Gabbay [GOYA_ETF_CPU_1] = mmCPU_ETF_1_BASE,
49*e65e175bSOded Gabbay [GOYA_ETF_CPU_TRACE] = mmCPU_ETF_TRACE_BASE,
50*e65e175bSOded Gabbay [GOYA_ETF_DMA_CH_0_CS] = mmDMA_CH_0_CS_ETF_BASE,
51*e65e175bSOded Gabbay [GOYA_ETF_DMA_CH_1_CS] = mmDMA_CH_1_CS_ETF_BASE,
52*e65e175bSOded Gabbay [GOYA_ETF_DMA_CH_2_CS] = mmDMA_CH_2_CS_ETF_BASE,
53*e65e175bSOded Gabbay [GOYA_ETF_DMA_CH_3_CS] = mmDMA_CH_3_CS_ETF_BASE,
54*e65e175bSOded Gabbay [GOYA_ETF_DMA_CH_4_CS] = mmDMA_CH_4_CS_ETF_BASE,
55*e65e175bSOded Gabbay [GOYA_ETF_DMA_MACRO_CS] = mmDMA_MACRO_CS_ETF_BASE,
56*e65e175bSOded Gabbay [GOYA_ETF_MME1_SBA] = mmMME1_SBA_ETF_BASE,
57*e65e175bSOded Gabbay [GOYA_ETF_MME3_SBB] = mmMME3_SBB_ETF_BASE,
58*e65e175bSOded Gabbay [GOYA_ETF_MME4_WACS2] = mmMME4_WACS2_ETF_BASE,
59*e65e175bSOded Gabbay [GOYA_ETF_MME4_WACS] = mmMME4_WACS_ETF_BASE,
60*e65e175bSOded Gabbay [GOYA_ETF_MMU_CS] = mmMMU_CS_ETF_BASE,
61*e65e175bSOded Gabbay [GOYA_ETF_PCIE] = mmPCIE_ETF_BASE,
62*e65e175bSOded Gabbay [GOYA_ETF_PSOC] = mmPSOC_ETF_BASE,
63*e65e175bSOded Gabbay [GOYA_ETF_TPC0_EML] = mmTPC0_EML_ETF_BASE,
64*e65e175bSOded Gabbay [GOYA_ETF_TPC1_EML] = mmTPC1_EML_ETF_BASE,
65*e65e175bSOded Gabbay [GOYA_ETF_TPC2_EML] = mmTPC2_EML_ETF_BASE,
66*e65e175bSOded Gabbay [GOYA_ETF_TPC3_EML] = mmTPC3_EML_ETF_BASE,
67*e65e175bSOded Gabbay [GOYA_ETF_TPC4_EML] = mmTPC4_EML_ETF_BASE,
68*e65e175bSOded Gabbay [GOYA_ETF_TPC5_EML] = mmTPC5_EML_ETF_BASE,
69*e65e175bSOded Gabbay [GOYA_ETF_TPC6_EML] = mmTPC6_EML_ETF_BASE,
70*e65e175bSOded Gabbay [GOYA_ETF_TPC7_EML] = mmTPC7_EML_ETF_BASE
71*e65e175bSOded Gabbay };
72*e65e175bSOded Gabbay
73*e65e175bSOded Gabbay static u64 debug_funnel_regs[GOYA_FUNNEL_LAST + 1] = {
74*e65e175bSOded Gabbay [GOYA_FUNNEL_CPU] = mmCPU_FUNNEL_BASE,
75*e65e175bSOded Gabbay [GOYA_FUNNEL_DMA_CH_6_1] = mmDMA_CH_FUNNEL_6_1_BASE,
76*e65e175bSOded Gabbay [GOYA_FUNNEL_DMA_MACRO_3_1] = mmDMA_MACRO_FUNNEL_3_1_BASE,
77*e65e175bSOded Gabbay [GOYA_FUNNEL_MME0_RTR] = mmMME0_RTR_FUNNEL_BASE,
78*e65e175bSOded Gabbay [GOYA_FUNNEL_MME1_RTR] = mmMME1_RTR_FUNNEL_BASE,
79*e65e175bSOded Gabbay [GOYA_FUNNEL_MME2_RTR] = mmMME2_RTR_FUNNEL_BASE,
80*e65e175bSOded Gabbay [GOYA_FUNNEL_MME3_RTR] = mmMME3_RTR_FUNNEL_BASE,
81*e65e175bSOded Gabbay [GOYA_FUNNEL_MME4_RTR] = mmMME4_RTR_FUNNEL_BASE,
82*e65e175bSOded Gabbay [GOYA_FUNNEL_MME5_RTR] = mmMME5_RTR_FUNNEL_BASE,
83*e65e175bSOded Gabbay [GOYA_FUNNEL_PCIE] = mmPCIE_FUNNEL_BASE,
84*e65e175bSOded Gabbay [GOYA_FUNNEL_PSOC] = mmPSOC_FUNNEL_BASE,
85*e65e175bSOded Gabbay [GOYA_FUNNEL_TPC0_EML] = mmTPC0_EML_FUNNEL_BASE,
86*e65e175bSOded Gabbay [GOYA_FUNNEL_TPC1_EML] = mmTPC1_EML_FUNNEL_BASE,
87*e65e175bSOded Gabbay [GOYA_FUNNEL_TPC1_RTR] = mmTPC1_RTR_FUNNEL_BASE,
88*e65e175bSOded Gabbay [GOYA_FUNNEL_TPC2_EML] = mmTPC2_EML_FUNNEL_BASE,
89*e65e175bSOded Gabbay [GOYA_FUNNEL_TPC2_RTR] = mmTPC2_RTR_FUNNEL_BASE,
90*e65e175bSOded Gabbay [GOYA_FUNNEL_TPC3_EML] = mmTPC3_EML_FUNNEL_BASE,
91*e65e175bSOded Gabbay [GOYA_FUNNEL_TPC3_RTR] = mmTPC3_RTR_FUNNEL_BASE,
92*e65e175bSOded Gabbay [GOYA_FUNNEL_TPC4_EML] = mmTPC4_EML_FUNNEL_BASE,
93*e65e175bSOded Gabbay [GOYA_FUNNEL_TPC4_RTR] = mmTPC4_RTR_FUNNEL_BASE,
94*e65e175bSOded Gabbay [GOYA_FUNNEL_TPC5_EML] = mmTPC5_EML_FUNNEL_BASE,
95*e65e175bSOded Gabbay [GOYA_FUNNEL_TPC5_RTR] = mmTPC5_RTR_FUNNEL_BASE,
96*e65e175bSOded Gabbay [GOYA_FUNNEL_TPC6_EML] = mmTPC6_EML_FUNNEL_BASE,
97*e65e175bSOded Gabbay [GOYA_FUNNEL_TPC6_RTR] = mmTPC6_RTR_FUNNEL_BASE,
98*e65e175bSOded Gabbay [GOYA_FUNNEL_TPC7_EML] = mmTPC7_EML_FUNNEL_BASE
99*e65e175bSOded Gabbay };
100*e65e175bSOded Gabbay
101*e65e175bSOded Gabbay static u64 debug_bmon_regs[GOYA_BMON_LAST + 1] = {
102*e65e175bSOded Gabbay [GOYA_BMON_CPU_RD] = mmCPU_RD_BMON_BASE,
103*e65e175bSOded Gabbay [GOYA_BMON_CPU_WR] = mmCPU_WR_BMON_BASE,
104*e65e175bSOded Gabbay [GOYA_BMON_DMA_CH_0_0] = mmDMA_CH_0_BMON_0_BASE,
105*e65e175bSOded Gabbay [GOYA_BMON_DMA_CH_0_1] = mmDMA_CH_0_BMON_1_BASE,
106*e65e175bSOded Gabbay [GOYA_BMON_DMA_CH_1_0] = mmDMA_CH_1_BMON_0_BASE,
107*e65e175bSOded Gabbay [GOYA_BMON_DMA_CH_1_1] = mmDMA_CH_1_BMON_1_BASE,
108*e65e175bSOded Gabbay [GOYA_BMON_DMA_CH_2_0] = mmDMA_CH_2_BMON_0_BASE,
109*e65e175bSOded Gabbay [GOYA_BMON_DMA_CH_2_1] = mmDMA_CH_2_BMON_1_BASE,
110*e65e175bSOded Gabbay [GOYA_BMON_DMA_CH_3_0] = mmDMA_CH_3_BMON_0_BASE,
111*e65e175bSOded Gabbay [GOYA_BMON_DMA_CH_3_1] = mmDMA_CH_3_BMON_1_BASE,
112*e65e175bSOded Gabbay [GOYA_BMON_DMA_CH_4_0] = mmDMA_CH_4_BMON_0_BASE,
113*e65e175bSOded Gabbay [GOYA_BMON_DMA_CH_4_1] = mmDMA_CH_4_BMON_1_BASE,
114*e65e175bSOded Gabbay [GOYA_BMON_DMA_MACRO_0] = mmDMA_MACRO_BMON_0_BASE,
115*e65e175bSOded Gabbay [GOYA_BMON_DMA_MACRO_1] = mmDMA_MACRO_BMON_1_BASE,
116*e65e175bSOded Gabbay [GOYA_BMON_DMA_MACRO_2] = mmDMA_MACRO_BMON_2_BASE,
117*e65e175bSOded Gabbay [GOYA_BMON_DMA_MACRO_3] = mmDMA_MACRO_BMON_3_BASE,
118*e65e175bSOded Gabbay [GOYA_BMON_DMA_MACRO_4] = mmDMA_MACRO_BMON_4_BASE,
119*e65e175bSOded Gabbay [GOYA_BMON_DMA_MACRO_5] = mmDMA_MACRO_BMON_5_BASE,
120*e65e175bSOded Gabbay [GOYA_BMON_DMA_MACRO_6] = mmDMA_MACRO_BMON_6_BASE,
121*e65e175bSOded Gabbay [GOYA_BMON_DMA_MACRO_7] = mmDMA_MACRO_BMON_7_BASE,
122*e65e175bSOded Gabbay [GOYA_BMON_MME1_SBA_0] = mmMME1_SBA_BMON0_BASE,
123*e65e175bSOded Gabbay [GOYA_BMON_MME1_SBA_1] = mmMME1_SBA_BMON1_BASE,
124*e65e175bSOded Gabbay [GOYA_BMON_MME3_SBB_0] = mmMME3_SBB_BMON0_BASE,
125*e65e175bSOded Gabbay [GOYA_BMON_MME3_SBB_1] = mmMME3_SBB_BMON1_BASE,
126*e65e175bSOded Gabbay [GOYA_BMON_MME4_WACS2_0] = mmMME4_WACS2_BMON0_BASE,
127*e65e175bSOded Gabbay [GOYA_BMON_MME4_WACS2_1] = mmMME4_WACS2_BMON1_BASE,
128*e65e175bSOded Gabbay [GOYA_BMON_MME4_WACS2_2] = mmMME4_WACS2_BMON2_BASE,
129*e65e175bSOded Gabbay [GOYA_BMON_MME4_WACS_0] = mmMME4_WACS_BMON0_BASE,
130*e65e175bSOded Gabbay [GOYA_BMON_MME4_WACS_1] = mmMME4_WACS_BMON1_BASE,
131*e65e175bSOded Gabbay [GOYA_BMON_MME4_WACS_2] = mmMME4_WACS_BMON2_BASE,
132*e65e175bSOded Gabbay [GOYA_BMON_MME4_WACS_3] = mmMME4_WACS_BMON3_BASE,
133*e65e175bSOded Gabbay [GOYA_BMON_MME4_WACS_4] = mmMME4_WACS_BMON4_BASE,
134*e65e175bSOded Gabbay [GOYA_BMON_MME4_WACS_5] = mmMME4_WACS_BMON5_BASE,
135*e65e175bSOded Gabbay [GOYA_BMON_MME4_WACS_6] = mmMME4_WACS_BMON6_BASE,
136*e65e175bSOded Gabbay [GOYA_BMON_MMU_0] = mmMMU_BMON_0_BASE,
137*e65e175bSOded Gabbay [GOYA_BMON_MMU_1] = mmMMU_BMON_1_BASE,
138*e65e175bSOded Gabbay [GOYA_BMON_PCIE_MSTR_RD] = mmPCIE_BMON_MSTR_RD_BASE,
139*e65e175bSOded Gabbay [GOYA_BMON_PCIE_MSTR_WR] = mmPCIE_BMON_MSTR_WR_BASE,
140*e65e175bSOded Gabbay [GOYA_BMON_PCIE_SLV_RD] = mmPCIE_BMON_SLV_RD_BASE,
141*e65e175bSOded Gabbay [GOYA_BMON_PCIE_SLV_WR] = mmPCIE_BMON_SLV_WR_BASE,
142*e65e175bSOded Gabbay [GOYA_BMON_TPC0_EML_0] = mmTPC0_EML_BUSMON_0_BASE,
143*e65e175bSOded Gabbay [GOYA_BMON_TPC0_EML_1] = mmTPC0_EML_BUSMON_1_BASE,
144*e65e175bSOded Gabbay [GOYA_BMON_TPC0_EML_2] = mmTPC0_EML_BUSMON_2_BASE,
145*e65e175bSOded Gabbay [GOYA_BMON_TPC0_EML_3] = mmTPC0_EML_BUSMON_3_BASE,
146*e65e175bSOded Gabbay [GOYA_BMON_TPC1_EML_0] = mmTPC1_EML_BUSMON_0_BASE,
147*e65e175bSOded Gabbay [GOYA_BMON_TPC1_EML_1] = mmTPC1_EML_BUSMON_1_BASE,
148*e65e175bSOded Gabbay [GOYA_BMON_TPC1_EML_2] = mmTPC1_EML_BUSMON_2_BASE,
149*e65e175bSOded Gabbay [GOYA_BMON_TPC1_EML_3] = mmTPC1_EML_BUSMON_3_BASE,
150*e65e175bSOded Gabbay [GOYA_BMON_TPC2_EML_0] = mmTPC2_EML_BUSMON_0_BASE,
151*e65e175bSOded Gabbay [GOYA_BMON_TPC2_EML_1] = mmTPC2_EML_BUSMON_1_BASE,
152*e65e175bSOded Gabbay [GOYA_BMON_TPC2_EML_2] = mmTPC2_EML_BUSMON_2_BASE,
153*e65e175bSOded Gabbay [GOYA_BMON_TPC2_EML_3] = mmTPC2_EML_BUSMON_3_BASE,
154*e65e175bSOded Gabbay [GOYA_BMON_TPC3_EML_0] = mmTPC3_EML_BUSMON_0_BASE,
155*e65e175bSOded Gabbay [GOYA_BMON_TPC3_EML_1] = mmTPC3_EML_BUSMON_1_BASE,
156*e65e175bSOded Gabbay [GOYA_BMON_TPC3_EML_2] = mmTPC3_EML_BUSMON_2_BASE,
157*e65e175bSOded Gabbay [GOYA_BMON_TPC3_EML_3] = mmTPC3_EML_BUSMON_3_BASE,
158*e65e175bSOded Gabbay [GOYA_BMON_TPC4_EML_0] = mmTPC4_EML_BUSMON_0_BASE,
159*e65e175bSOded Gabbay [GOYA_BMON_TPC4_EML_1] = mmTPC4_EML_BUSMON_1_BASE,
160*e65e175bSOded Gabbay [GOYA_BMON_TPC4_EML_2] = mmTPC4_EML_BUSMON_2_BASE,
161*e65e175bSOded Gabbay [GOYA_BMON_TPC4_EML_3] = mmTPC4_EML_BUSMON_3_BASE,
162*e65e175bSOded Gabbay [GOYA_BMON_TPC5_EML_0] = mmTPC5_EML_BUSMON_0_BASE,
163*e65e175bSOded Gabbay [GOYA_BMON_TPC5_EML_1] = mmTPC5_EML_BUSMON_1_BASE,
164*e65e175bSOded Gabbay [GOYA_BMON_TPC5_EML_2] = mmTPC5_EML_BUSMON_2_BASE,
165*e65e175bSOded Gabbay [GOYA_BMON_TPC5_EML_3] = mmTPC5_EML_BUSMON_3_BASE,
166*e65e175bSOded Gabbay [GOYA_BMON_TPC6_EML_0] = mmTPC6_EML_BUSMON_0_BASE,
167*e65e175bSOded Gabbay [GOYA_BMON_TPC6_EML_1] = mmTPC6_EML_BUSMON_1_BASE,
168*e65e175bSOded Gabbay [GOYA_BMON_TPC6_EML_2] = mmTPC6_EML_BUSMON_2_BASE,
169*e65e175bSOded Gabbay [GOYA_BMON_TPC6_EML_3] = mmTPC6_EML_BUSMON_3_BASE,
170*e65e175bSOded Gabbay [GOYA_BMON_TPC7_EML_0] = mmTPC7_EML_BUSMON_0_BASE,
171*e65e175bSOded Gabbay [GOYA_BMON_TPC7_EML_1] = mmTPC7_EML_BUSMON_1_BASE,
172*e65e175bSOded Gabbay [GOYA_BMON_TPC7_EML_2] = mmTPC7_EML_BUSMON_2_BASE,
173*e65e175bSOded Gabbay [GOYA_BMON_TPC7_EML_3] = mmTPC7_EML_BUSMON_3_BASE
174*e65e175bSOded Gabbay };
175*e65e175bSOded Gabbay
176*e65e175bSOded Gabbay static u64 debug_spmu_regs[GOYA_SPMU_LAST + 1] = {
177*e65e175bSOded Gabbay [GOYA_SPMU_DMA_CH_0_CS] = mmDMA_CH_0_CS_SPMU_BASE,
178*e65e175bSOded Gabbay [GOYA_SPMU_DMA_CH_1_CS] = mmDMA_CH_1_CS_SPMU_BASE,
179*e65e175bSOded Gabbay [GOYA_SPMU_DMA_CH_2_CS] = mmDMA_CH_2_CS_SPMU_BASE,
180*e65e175bSOded Gabbay [GOYA_SPMU_DMA_CH_3_CS] = mmDMA_CH_3_CS_SPMU_BASE,
181*e65e175bSOded Gabbay [GOYA_SPMU_DMA_CH_4_CS] = mmDMA_CH_4_CS_SPMU_BASE,
182*e65e175bSOded Gabbay [GOYA_SPMU_DMA_MACRO_CS] = mmDMA_MACRO_CS_SPMU_BASE,
183*e65e175bSOded Gabbay [GOYA_SPMU_MME1_SBA] = mmMME1_SBA_SPMU_BASE,
184*e65e175bSOded Gabbay [GOYA_SPMU_MME3_SBB] = mmMME3_SBB_SPMU_BASE,
185*e65e175bSOded Gabbay [GOYA_SPMU_MME4_WACS2] = mmMME4_WACS2_SPMU_BASE,
186*e65e175bSOded Gabbay [GOYA_SPMU_MME4_WACS] = mmMME4_WACS_SPMU_BASE,
187*e65e175bSOded Gabbay [GOYA_SPMU_MMU_CS] = mmMMU_CS_SPMU_BASE,
188*e65e175bSOded Gabbay [GOYA_SPMU_PCIE] = mmPCIE_SPMU_BASE,
189*e65e175bSOded Gabbay [GOYA_SPMU_TPC0_EML] = mmTPC0_EML_SPMU_BASE,
190*e65e175bSOded Gabbay [GOYA_SPMU_TPC1_EML] = mmTPC1_EML_SPMU_BASE,
191*e65e175bSOded Gabbay [GOYA_SPMU_TPC2_EML] = mmTPC2_EML_SPMU_BASE,
192*e65e175bSOded Gabbay [GOYA_SPMU_TPC3_EML] = mmTPC3_EML_SPMU_BASE,
193*e65e175bSOded Gabbay [GOYA_SPMU_TPC4_EML] = mmTPC4_EML_SPMU_BASE,
194*e65e175bSOded Gabbay [GOYA_SPMU_TPC5_EML] = mmTPC5_EML_SPMU_BASE,
195*e65e175bSOded Gabbay [GOYA_SPMU_TPC6_EML] = mmTPC6_EML_SPMU_BASE,
196*e65e175bSOded Gabbay [GOYA_SPMU_TPC7_EML] = mmTPC7_EML_SPMU_BASE
197*e65e175bSOded Gabbay };
198*e65e175bSOded Gabbay
goya_coresight_timeout(struct hl_device * hdev,u64 addr,int position,bool up)199*e65e175bSOded Gabbay static int goya_coresight_timeout(struct hl_device *hdev, u64 addr,
200*e65e175bSOded Gabbay int position, bool up)
201*e65e175bSOded Gabbay {
202*e65e175bSOded Gabbay int rc;
203*e65e175bSOded Gabbay u32 val, timeout_usec;
204*e65e175bSOded Gabbay
205*e65e175bSOded Gabbay if (hdev->pldm)
206*e65e175bSOded Gabbay timeout_usec = GOYA_PLDM_CORESIGHT_TIMEOUT_USEC;
207*e65e175bSOded Gabbay else
208*e65e175bSOded Gabbay timeout_usec = CORESIGHT_TIMEOUT_USEC;
209*e65e175bSOded Gabbay
210*e65e175bSOded Gabbay rc = hl_poll_timeout(
211*e65e175bSOded Gabbay hdev,
212*e65e175bSOded Gabbay addr,
213*e65e175bSOded Gabbay val,
214*e65e175bSOded Gabbay up ? val & BIT(position) : !(val & BIT(position)),
215*e65e175bSOded Gabbay 1000,
216*e65e175bSOded Gabbay timeout_usec);
217*e65e175bSOded Gabbay
218*e65e175bSOded Gabbay if (rc) {
219*e65e175bSOded Gabbay dev_err(hdev->dev,
220*e65e175bSOded Gabbay "Timeout while waiting for coresight, addr: 0x%llx, position: %d, up: %d\n",
221*e65e175bSOded Gabbay addr, position, up);
222*e65e175bSOded Gabbay return -EFAULT;
223*e65e175bSOded Gabbay }
224*e65e175bSOded Gabbay
225*e65e175bSOded Gabbay return 0;
226*e65e175bSOded Gabbay }
227*e65e175bSOded Gabbay
goya_config_stm(struct hl_device * hdev,struct hl_debug_params * params)228*e65e175bSOded Gabbay static int goya_config_stm(struct hl_device *hdev,
229*e65e175bSOded Gabbay struct hl_debug_params *params)
230*e65e175bSOded Gabbay {
231*e65e175bSOded Gabbay struct hl_debug_params_stm *input;
232*e65e175bSOded Gabbay u64 base_reg;
233*e65e175bSOded Gabbay u32 frequency;
234*e65e175bSOded Gabbay int rc;
235*e65e175bSOded Gabbay
236*e65e175bSOded Gabbay if (params->reg_idx >= ARRAY_SIZE(debug_stm_regs)) {
237*e65e175bSOded Gabbay dev_err(hdev->dev, "Invalid register index in STM\n");
238*e65e175bSOded Gabbay return -EINVAL;
239*e65e175bSOded Gabbay }
240*e65e175bSOded Gabbay
241*e65e175bSOded Gabbay base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE;
242*e65e175bSOded Gabbay
243*e65e175bSOded Gabbay WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
244*e65e175bSOded Gabbay
245*e65e175bSOded Gabbay if (params->enable) {
246*e65e175bSOded Gabbay input = params->input;
247*e65e175bSOded Gabbay
248*e65e175bSOded Gabbay if (!input)
249*e65e175bSOded Gabbay return -EINVAL;
250*e65e175bSOded Gabbay
251*e65e175bSOded Gabbay WREG32(base_reg + 0xE80, 0x80004);
252*e65e175bSOded Gabbay WREG32(base_reg + 0xD64, 7);
253*e65e175bSOded Gabbay WREG32(base_reg + 0xD60, 0);
254*e65e175bSOded Gabbay WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask));
255*e65e175bSOded Gabbay WREG32(base_reg + 0xD20, lower_32_bits(input->sp_mask));
256*e65e175bSOded Gabbay WREG32(base_reg + 0xD60, 1);
257*e65e175bSOded Gabbay WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask));
258*e65e175bSOded Gabbay WREG32(base_reg + 0xD20, upper_32_bits(input->sp_mask));
259*e65e175bSOded Gabbay WREG32(base_reg + 0xE70, 0x10);
260*e65e175bSOded Gabbay WREG32(base_reg + 0xE60, 0);
261*e65e175bSOded Gabbay WREG32(base_reg + 0xE64, 0x420000);
262*e65e175bSOded Gabbay WREG32(base_reg + 0xE00, 0xFFFFFFFF);
263*e65e175bSOded Gabbay WREG32(base_reg + 0xE20, 0xFFFFFFFF);
264*e65e175bSOded Gabbay WREG32(base_reg + 0xEF4, input->id);
265*e65e175bSOded Gabbay WREG32(base_reg + 0xDF4, 0x80);
266*e65e175bSOded Gabbay frequency = hdev->asic_prop.psoc_timestamp_frequency;
267*e65e175bSOded Gabbay if (frequency == 0)
268*e65e175bSOded Gabbay frequency = input->frequency;
269*e65e175bSOded Gabbay WREG32(base_reg + 0xE8C, frequency);
270*e65e175bSOded Gabbay WREG32(base_reg + 0xE90, 0x7FF);
271*e65e175bSOded Gabbay WREG32(base_reg + 0xE80, 0x27 | (input->id << 16));
272*e65e175bSOded Gabbay } else {
273*e65e175bSOded Gabbay WREG32(base_reg + 0xE80, 4);
274*e65e175bSOded Gabbay WREG32(base_reg + 0xD64, 0);
275*e65e175bSOded Gabbay WREG32(base_reg + 0xD60, 1);
276*e65e175bSOded Gabbay WREG32(base_reg + 0xD00, 0);
277*e65e175bSOded Gabbay WREG32(base_reg + 0xD20, 0);
278*e65e175bSOded Gabbay WREG32(base_reg + 0xD60, 0);
279*e65e175bSOded Gabbay WREG32(base_reg + 0xE20, 0);
280*e65e175bSOded Gabbay WREG32(base_reg + 0xE00, 0);
281*e65e175bSOded Gabbay WREG32(base_reg + 0xDF4, 0x80);
282*e65e175bSOded Gabbay WREG32(base_reg + 0xE70, 0);
283*e65e175bSOded Gabbay WREG32(base_reg + 0xE60, 0);
284*e65e175bSOded Gabbay WREG32(base_reg + 0xE64, 0);
285*e65e175bSOded Gabbay WREG32(base_reg + 0xE8C, 0);
286*e65e175bSOded Gabbay
287*e65e175bSOded Gabbay rc = goya_coresight_timeout(hdev, base_reg + 0xE80, 23, false);
288*e65e175bSOded Gabbay if (rc) {
289*e65e175bSOded Gabbay dev_err(hdev->dev,
290*e65e175bSOded Gabbay "Failed to disable STM on timeout, error %d\n",
291*e65e175bSOded Gabbay rc);
292*e65e175bSOded Gabbay return rc;
293*e65e175bSOded Gabbay }
294*e65e175bSOded Gabbay
295*e65e175bSOded Gabbay WREG32(base_reg + 0xE80, 4);
296*e65e175bSOded Gabbay }
297*e65e175bSOded Gabbay
298*e65e175bSOded Gabbay return 0;
299*e65e175bSOded Gabbay }
300*e65e175bSOded Gabbay
goya_config_etf(struct hl_device * hdev,struct hl_debug_params * params)301*e65e175bSOded Gabbay static int goya_config_etf(struct hl_device *hdev,
302*e65e175bSOded Gabbay struct hl_debug_params *params)
303*e65e175bSOded Gabbay {
304*e65e175bSOded Gabbay struct hl_debug_params_etf *input;
305*e65e175bSOded Gabbay u64 base_reg;
306*e65e175bSOded Gabbay u32 val;
307*e65e175bSOded Gabbay int rc;
308*e65e175bSOded Gabbay
309*e65e175bSOded Gabbay if (params->reg_idx >= ARRAY_SIZE(debug_etf_regs)) {
310*e65e175bSOded Gabbay dev_err(hdev->dev, "Invalid register index in ETF\n");
311*e65e175bSOded Gabbay return -EINVAL;
312*e65e175bSOded Gabbay }
313*e65e175bSOded Gabbay
314*e65e175bSOded Gabbay base_reg = debug_etf_regs[params->reg_idx] - CFG_BASE;
315*e65e175bSOded Gabbay
316*e65e175bSOded Gabbay WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
317*e65e175bSOded Gabbay
318*e65e175bSOded Gabbay val = RREG32(base_reg + 0x304);
319*e65e175bSOded Gabbay val |= 0x1000;
320*e65e175bSOded Gabbay WREG32(base_reg + 0x304, val);
321*e65e175bSOded Gabbay val |= 0x40;
322*e65e175bSOded Gabbay WREG32(base_reg + 0x304, val);
323*e65e175bSOded Gabbay
324*e65e175bSOded Gabbay rc = goya_coresight_timeout(hdev, base_reg + 0x304, 6, false);
325*e65e175bSOded Gabbay if (rc) {
326*e65e175bSOded Gabbay dev_err(hdev->dev,
327*e65e175bSOded Gabbay "Failed to %s ETF on timeout, error %d\n",
328*e65e175bSOded Gabbay params->enable ? "enable" : "disable", rc);
329*e65e175bSOded Gabbay return rc;
330*e65e175bSOded Gabbay }
331*e65e175bSOded Gabbay
332*e65e175bSOded Gabbay rc = goya_coresight_timeout(hdev, base_reg + 0xC, 2, true);
333*e65e175bSOded Gabbay if (rc) {
334*e65e175bSOded Gabbay dev_err(hdev->dev,
335*e65e175bSOded Gabbay "Failed to %s ETF on timeout, error %d\n",
336*e65e175bSOded Gabbay params->enable ? "enable" : "disable", rc);
337*e65e175bSOded Gabbay return rc;
338*e65e175bSOded Gabbay }
339*e65e175bSOded Gabbay
340*e65e175bSOded Gabbay WREG32(base_reg + 0x20, 0);
341*e65e175bSOded Gabbay
342*e65e175bSOded Gabbay if (params->enable) {
343*e65e175bSOded Gabbay input = params->input;
344*e65e175bSOded Gabbay
345*e65e175bSOded Gabbay if (!input)
346*e65e175bSOded Gabbay return -EINVAL;
347*e65e175bSOded Gabbay
348*e65e175bSOded Gabbay WREG32(base_reg + 0x34, 0x3FFC);
349*e65e175bSOded Gabbay WREG32(base_reg + 0x28, input->sink_mode);
350*e65e175bSOded Gabbay WREG32(base_reg + 0x304, 0x4001);
351*e65e175bSOded Gabbay WREG32(base_reg + 0x308, 0xA);
352*e65e175bSOded Gabbay WREG32(base_reg + 0x20, 1);
353*e65e175bSOded Gabbay } else {
354*e65e175bSOded Gabbay WREG32(base_reg + 0x34, 0);
355*e65e175bSOded Gabbay WREG32(base_reg + 0x28, 0);
356*e65e175bSOded Gabbay WREG32(base_reg + 0x304, 0);
357*e65e175bSOded Gabbay }
358*e65e175bSOded Gabbay
359*e65e175bSOded Gabbay return 0;
360*e65e175bSOded Gabbay }
361*e65e175bSOded Gabbay
goya_etr_validate_address(struct hl_device * hdev,u64 addr,u64 size)362*e65e175bSOded Gabbay static int goya_etr_validate_address(struct hl_device *hdev, u64 addr,
363*e65e175bSOded Gabbay u64 size)
364*e65e175bSOded Gabbay {
365*e65e175bSOded Gabbay struct asic_fixed_properties *prop = &hdev->asic_prop;
366*e65e175bSOded Gabbay u64 range_start, range_end;
367*e65e175bSOded Gabbay
368*e65e175bSOded Gabbay if (addr > (addr + size)) {
369*e65e175bSOded Gabbay dev_err(hdev->dev,
370*e65e175bSOded Gabbay "ETR buffer size %llu overflow\n", size);
371*e65e175bSOded Gabbay return false;
372*e65e175bSOded Gabbay }
373*e65e175bSOded Gabbay
374*e65e175bSOded Gabbay range_start = prop->dmmu.start_addr;
375*e65e175bSOded Gabbay range_end = prop->dmmu.end_addr;
376*e65e175bSOded Gabbay
377*e65e175bSOded Gabbay return hl_mem_area_inside_range(addr, size, range_start, range_end);
378*e65e175bSOded Gabbay }
379*e65e175bSOded Gabbay
goya_config_etr(struct hl_device * hdev,struct hl_debug_params * params)380*e65e175bSOded Gabbay static int goya_config_etr(struct hl_device *hdev,
381*e65e175bSOded Gabbay struct hl_debug_params *params)
382*e65e175bSOded Gabbay {
383*e65e175bSOded Gabbay struct hl_debug_params_etr *input;
384*e65e175bSOded Gabbay u32 val;
385*e65e175bSOded Gabbay int rc;
386*e65e175bSOded Gabbay
387*e65e175bSOded Gabbay WREG32(mmPSOC_ETR_LAR, CORESIGHT_UNLOCK);
388*e65e175bSOded Gabbay
389*e65e175bSOded Gabbay val = RREG32(mmPSOC_ETR_FFCR);
390*e65e175bSOded Gabbay val |= 0x1000;
391*e65e175bSOded Gabbay WREG32(mmPSOC_ETR_FFCR, val);
392*e65e175bSOded Gabbay val |= 0x40;
393*e65e175bSOded Gabbay WREG32(mmPSOC_ETR_FFCR, val);
394*e65e175bSOded Gabbay
395*e65e175bSOded Gabbay rc = goya_coresight_timeout(hdev, mmPSOC_ETR_FFCR, 6, false);
396*e65e175bSOded Gabbay if (rc) {
397*e65e175bSOded Gabbay dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n",
398*e65e175bSOded Gabbay params->enable ? "enable" : "disable", rc);
399*e65e175bSOded Gabbay return rc;
400*e65e175bSOded Gabbay }
401*e65e175bSOded Gabbay
402*e65e175bSOded Gabbay rc = goya_coresight_timeout(hdev, mmPSOC_ETR_STS, 2, true);
403*e65e175bSOded Gabbay if (rc) {
404*e65e175bSOded Gabbay dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n",
405*e65e175bSOded Gabbay params->enable ? "enable" : "disable", rc);
406*e65e175bSOded Gabbay return rc;
407*e65e175bSOded Gabbay }
408*e65e175bSOded Gabbay
409*e65e175bSOded Gabbay WREG32(mmPSOC_ETR_CTL, 0);
410*e65e175bSOded Gabbay
411*e65e175bSOded Gabbay if (params->enable) {
412*e65e175bSOded Gabbay input = params->input;
413*e65e175bSOded Gabbay
414*e65e175bSOded Gabbay if (!input)
415*e65e175bSOded Gabbay return -EINVAL;
416*e65e175bSOded Gabbay
417*e65e175bSOded Gabbay if (input->buffer_size == 0) {
418*e65e175bSOded Gabbay dev_err(hdev->dev,
419*e65e175bSOded Gabbay "ETR buffer size should be bigger than 0\n");
420*e65e175bSOded Gabbay return -EINVAL;
421*e65e175bSOded Gabbay }
422*e65e175bSOded Gabbay
423*e65e175bSOded Gabbay if (!goya_etr_validate_address(hdev,
424*e65e175bSOded Gabbay input->buffer_address, input->buffer_size)) {
425*e65e175bSOded Gabbay dev_err(hdev->dev, "buffer address is not valid\n");
426*e65e175bSOded Gabbay return -EINVAL;
427*e65e175bSOded Gabbay }
428*e65e175bSOded Gabbay
429*e65e175bSOded Gabbay WREG32(mmPSOC_ETR_BUFWM, 0x3FFC);
430*e65e175bSOded Gabbay WREG32(mmPSOC_ETR_RSZ, input->buffer_size);
431*e65e175bSOded Gabbay WREG32(mmPSOC_ETR_MODE, input->sink_mode);
432*e65e175bSOded Gabbay if (!hdev->asic_prop.fw_security_enabled) {
433*e65e175bSOded Gabbay /* make ETR not privileged */
434*e65e175bSOded Gabbay val = FIELD_PREP(PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK, 0);
435*e65e175bSOded Gabbay /* make ETR non-secured (inverted logic) */
436*e65e175bSOded Gabbay val |= FIELD_PREP(PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK, 1);
437*e65e175bSOded Gabbay /* burst size 8 */
438*e65e175bSOded Gabbay val |= FIELD_PREP(PSOC_ETR_AXICTL_WRBURSTLEN_MASK, 7);
439*e65e175bSOded Gabbay WREG32(mmPSOC_ETR_AXICTL, val);
440*e65e175bSOded Gabbay }
441*e65e175bSOded Gabbay WREG32(mmPSOC_ETR_DBALO,
442*e65e175bSOded Gabbay lower_32_bits(input->buffer_address));
443*e65e175bSOded Gabbay WREG32(mmPSOC_ETR_DBAHI,
444*e65e175bSOded Gabbay upper_32_bits(input->buffer_address));
445*e65e175bSOded Gabbay WREG32(mmPSOC_ETR_FFCR, 3);
446*e65e175bSOded Gabbay WREG32(mmPSOC_ETR_PSCR, 0xA);
447*e65e175bSOded Gabbay WREG32(mmPSOC_ETR_CTL, 1);
448*e65e175bSOded Gabbay } else {
449*e65e175bSOded Gabbay WREG32(mmPSOC_ETR_BUFWM, 0);
450*e65e175bSOded Gabbay WREG32(mmPSOC_ETR_RSZ, 0x400);
451*e65e175bSOded Gabbay WREG32(mmPSOC_ETR_DBALO, 0);
452*e65e175bSOded Gabbay WREG32(mmPSOC_ETR_DBAHI, 0);
453*e65e175bSOded Gabbay WREG32(mmPSOC_ETR_PSCR, 0);
454*e65e175bSOded Gabbay WREG32(mmPSOC_ETR_MODE, 0);
455*e65e175bSOded Gabbay WREG32(mmPSOC_ETR_FFCR, 0);
456*e65e175bSOded Gabbay
457*e65e175bSOded Gabbay if (params->output_size >= sizeof(u64)) {
458*e65e175bSOded Gabbay u32 rwp, rwphi;
459*e65e175bSOded Gabbay
460*e65e175bSOded Gabbay /*
461*e65e175bSOded Gabbay * The trace buffer address is 40 bits wide. The end of
462*e65e175bSOded Gabbay * the buffer is set in the RWP register (lower 32
463*e65e175bSOded Gabbay * bits), and in the RWPHI register (upper 8 bits).
464*e65e175bSOded Gabbay */
465*e65e175bSOded Gabbay rwp = RREG32(mmPSOC_ETR_RWP);
466*e65e175bSOded Gabbay rwphi = RREG32(mmPSOC_ETR_RWPHI) & 0xff;
467*e65e175bSOded Gabbay *(u64 *) params->output = ((u64) rwphi << 32) | rwp;
468*e65e175bSOded Gabbay }
469*e65e175bSOded Gabbay }
470*e65e175bSOded Gabbay
471*e65e175bSOded Gabbay return 0;
472*e65e175bSOded Gabbay }
473*e65e175bSOded Gabbay
goya_config_funnel(struct hl_device * hdev,struct hl_debug_params * params)474*e65e175bSOded Gabbay static int goya_config_funnel(struct hl_device *hdev,
475*e65e175bSOded Gabbay struct hl_debug_params *params)
476*e65e175bSOded Gabbay {
477*e65e175bSOded Gabbay u64 base_reg;
478*e65e175bSOded Gabbay
479*e65e175bSOded Gabbay if (params->reg_idx >= ARRAY_SIZE(debug_funnel_regs)) {
480*e65e175bSOded Gabbay dev_err(hdev->dev, "Invalid register index in FUNNEL\n");
481*e65e175bSOded Gabbay return -EINVAL;
482*e65e175bSOded Gabbay }
483*e65e175bSOded Gabbay
484*e65e175bSOded Gabbay base_reg = debug_funnel_regs[params->reg_idx] - CFG_BASE;
485*e65e175bSOded Gabbay
486*e65e175bSOded Gabbay WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
487*e65e175bSOded Gabbay
488*e65e175bSOded Gabbay WREG32(base_reg, params->enable ? 0x33F : 0);
489*e65e175bSOded Gabbay
490*e65e175bSOded Gabbay return 0;
491*e65e175bSOded Gabbay }
492*e65e175bSOded Gabbay
goya_config_bmon(struct hl_device * hdev,struct hl_debug_params * params)493*e65e175bSOded Gabbay static int goya_config_bmon(struct hl_device *hdev,
494*e65e175bSOded Gabbay struct hl_debug_params *params)
495*e65e175bSOded Gabbay {
496*e65e175bSOded Gabbay struct hl_debug_params_bmon *input;
497*e65e175bSOded Gabbay u64 base_reg;
498*e65e175bSOded Gabbay u32 pcie_base = 0;
499*e65e175bSOded Gabbay
500*e65e175bSOded Gabbay if (params->reg_idx >= ARRAY_SIZE(debug_bmon_regs)) {
501*e65e175bSOded Gabbay dev_err(hdev->dev, "Invalid register index in BMON\n");
502*e65e175bSOded Gabbay return -EINVAL;
503*e65e175bSOded Gabbay }
504*e65e175bSOded Gabbay
505*e65e175bSOded Gabbay base_reg = debug_bmon_regs[params->reg_idx] - CFG_BASE;
506*e65e175bSOded Gabbay
507*e65e175bSOded Gabbay WREG32(base_reg + 0x104, 1);
508*e65e175bSOded Gabbay
509*e65e175bSOded Gabbay if (params->enable) {
510*e65e175bSOded Gabbay input = params->input;
511*e65e175bSOded Gabbay
512*e65e175bSOded Gabbay if (!input)
513*e65e175bSOded Gabbay return -EINVAL;
514*e65e175bSOded Gabbay
515*e65e175bSOded Gabbay WREG32(base_reg + 0x200, lower_32_bits(input->start_addr0));
516*e65e175bSOded Gabbay WREG32(base_reg + 0x204, upper_32_bits(input->start_addr0));
517*e65e175bSOded Gabbay WREG32(base_reg + 0x208, lower_32_bits(input->addr_mask0));
518*e65e175bSOded Gabbay WREG32(base_reg + 0x20C, upper_32_bits(input->addr_mask0));
519*e65e175bSOded Gabbay WREG32(base_reg + 0x240, lower_32_bits(input->start_addr1));
520*e65e175bSOded Gabbay WREG32(base_reg + 0x244, upper_32_bits(input->start_addr1));
521*e65e175bSOded Gabbay WREG32(base_reg + 0x248, lower_32_bits(input->addr_mask1));
522*e65e175bSOded Gabbay WREG32(base_reg + 0x24C, upper_32_bits(input->addr_mask1));
523*e65e175bSOded Gabbay WREG32(base_reg + 0x224, 0);
524*e65e175bSOded Gabbay WREG32(base_reg + 0x234, 0);
525*e65e175bSOded Gabbay WREG32(base_reg + 0x30C, input->bw_win);
526*e65e175bSOded Gabbay WREG32(base_reg + 0x308, input->win_capture);
527*e65e175bSOded Gabbay
528*e65e175bSOded Gabbay /* PCIE IF BMON bug WA */
529*e65e175bSOded Gabbay if (params->reg_idx != GOYA_BMON_PCIE_MSTR_RD &&
530*e65e175bSOded Gabbay params->reg_idx != GOYA_BMON_PCIE_MSTR_WR &&
531*e65e175bSOded Gabbay params->reg_idx != GOYA_BMON_PCIE_SLV_RD &&
532*e65e175bSOded Gabbay params->reg_idx != GOYA_BMON_PCIE_SLV_WR)
533*e65e175bSOded Gabbay pcie_base = 0xA000000;
534*e65e175bSOded Gabbay
535*e65e175bSOded Gabbay WREG32(base_reg + 0x700, pcie_base | 0xB00 | (input->id << 12));
536*e65e175bSOded Gabbay WREG32(base_reg + 0x708, pcie_base | 0xA00 | (input->id << 12));
537*e65e175bSOded Gabbay WREG32(base_reg + 0x70C, pcie_base | 0xC00 | (input->id << 12));
538*e65e175bSOded Gabbay
539*e65e175bSOded Gabbay WREG32(base_reg + 0x100, 0x11);
540*e65e175bSOded Gabbay WREG32(base_reg + 0x304, 0x1);
541*e65e175bSOded Gabbay } else {
542*e65e175bSOded Gabbay WREG32(base_reg + 0x200, 0);
543*e65e175bSOded Gabbay WREG32(base_reg + 0x204, 0);
544*e65e175bSOded Gabbay WREG32(base_reg + 0x208, 0xFFFFFFFF);
545*e65e175bSOded Gabbay WREG32(base_reg + 0x20C, 0xFFFFFFFF);
546*e65e175bSOded Gabbay WREG32(base_reg + 0x240, 0);
547*e65e175bSOded Gabbay WREG32(base_reg + 0x244, 0);
548*e65e175bSOded Gabbay WREG32(base_reg + 0x248, 0xFFFFFFFF);
549*e65e175bSOded Gabbay WREG32(base_reg + 0x24C, 0xFFFFFFFF);
550*e65e175bSOded Gabbay WREG32(base_reg + 0x224, 0xFFFFFFFF);
551*e65e175bSOded Gabbay WREG32(base_reg + 0x234, 0x1070F);
552*e65e175bSOded Gabbay WREG32(base_reg + 0x30C, 0);
553*e65e175bSOded Gabbay WREG32(base_reg + 0x308, 0xFFFF);
554*e65e175bSOded Gabbay WREG32(base_reg + 0x700, 0xA000B00);
555*e65e175bSOded Gabbay WREG32(base_reg + 0x708, 0xA000A00);
556*e65e175bSOded Gabbay WREG32(base_reg + 0x70C, 0xA000C00);
557*e65e175bSOded Gabbay WREG32(base_reg + 0x100, 1);
558*e65e175bSOded Gabbay WREG32(base_reg + 0x304, 0);
559*e65e175bSOded Gabbay WREG32(base_reg + 0x104, 0);
560*e65e175bSOded Gabbay }
561*e65e175bSOded Gabbay
562*e65e175bSOded Gabbay return 0;
563*e65e175bSOded Gabbay }
564*e65e175bSOded Gabbay
goya_config_spmu(struct hl_device * hdev,struct hl_debug_params * params)565*e65e175bSOded Gabbay static int goya_config_spmu(struct hl_device *hdev,
566*e65e175bSOded Gabbay struct hl_debug_params *params)
567*e65e175bSOded Gabbay {
568*e65e175bSOded Gabbay u64 base_reg;
569*e65e175bSOded Gabbay struct hl_debug_params_spmu *input = params->input;
570*e65e175bSOded Gabbay u64 *output;
571*e65e175bSOded Gabbay u32 output_arr_len;
572*e65e175bSOded Gabbay u32 events_num;
573*e65e175bSOded Gabbay u32 overflow_idx;
574*e65e175bSOded Gabbay u32 cycle_cnt_idx;
575*e65e175bSOded Gabbay int i;
576*e65e175bSOded Gabbay
577*e65e175bSOded Gabbay if (params->reg_idx >= ARRAY_SIZE(debug_spmu_regs)) {
578*e65e175bSOded Gabbay dev_err(hdev->dev, "Invalid register index in SPMU\n");
579*e65e175bSOded Gabbay return -EINVAL;
580*e65e175bSOded Gabbay }
581*e65e175bSOded Gabbay
582*e65e175bSOded Gabbay base_reg = debug_spmu_regs[params->reg_idx] - CFG_BASE;
583*e65e175bSOded Gabbay
584*e65e175bSOded Gabbay if (params->enable) {
585*e65e175bSOded Gabbay input = params->input;
586*e65e175bSOded Gabbay
587*e65e175bSOded Gabbay if (!input)
588*e65e175bSOded Gabbay return -EINVAL;
589*e65e175bSOded Gabbay
590*e65e175bSOded Gabbay if (input->event_types_num < 3) {
591*e65e175bSOded Gabbay dev_err(hdev->dev,
592*e65e175bSOded Gabbay "not enough event types values for SPMU enable\n");
593*e65e175bSOded Gabbay return -EINVAL;
594*e65e175bSOded Gabbay }
595*e65e175bSOded Gabbay
596*e65e175bSOded Gabbay if (input->event_types_num > SPMU_MAX_COUNTERS) {
597*e65e175bSOded Gabbay dev_err(hdev->dev,
598*e65e175bSOded Gabbay "too many event types values for SPMU enable\n");
599*e65e175bSOded Gabbay return -EINVAL;
600*e65e175bSOded Gabbay }
601*e65e175bSOded Gabbay
602*e65e175bSOded Gabbay WREG32(base_reg + 0xE04, 0x41013046);
603*e65e175bSOded Gabbay WREG32(base_reg + 0xE04, 0x41013040);
604*e65e175bSOded Gabbay
605*e65e175bSOded Gabbay for (i = 0 ; i < input->event_types_num ; i++)
606*e65e175bSOded Gabbay WREG32(base_reg + SPMU_EVENT_TYPES_OFFSET + i * 4,
607*e65e175bSOded Gabbay input->event_types[i]);
608*e65e175bSOded Gabbay
609*e65e175bSOded Gabbay WREG32(base_reg + 0xE04, 0x41013041);
610*e65e175bSOded Gabbay WREG32(base_reg + 0xC00, 0x8000003F);
611*e65e175bSOded Gabbay } else {
612*e65e175bSOded Gabbay output = params->output;
613*e65e175bSOded Gabbay output_arr_len = params->output_size / 8;
614*e65e175bSOded Gabbay events_num = output_arr_len - 2;
615*e65e175bSOded Gabbay overflow_idx = output_arr_len - 2;
616*e65e175bSOded Gabbay cycle_cnt_idx = output_arr_len - 1;
617*e65e175bSOded Gabbay
618*e65e175bSOded Gabbay if (!output)
619*e65e175bSOded Gabbay return -EINVAL;
620*e65e175bSOded Gabbay
621*e65e175bSOded Gabbay if (output_arr_len < 3) {
622*e65e175bSOded Gabbay dev_err(hdev->dev,
623*e65e175bSOded Gabbay "not enough values for SPMU disable\n");
624*e65e175bSOded Gabbay return -EINVAL;
625*e65e175bSOded Gabbay }
626*e65e175bSOded Gabbay
627*e65e175bSOded Gabbay if (events_num > SPMU_MAX_COUNTERS) {
628*e65e175bSOded Gabbay dev_err(hdev->dev,
629*e65e175bSOded Gabbay "too many events values for SPMU disable\n");
630*e65e175bSOded Gabbay return -EINVAL;
631*e65e175bSOded Gabbay }
632*e65e175bSOded Gabbay
633*e65e175bSOded Gabbay WREG32(base_reg + 0xE04, 0x41013040);
634*e65e175bSOded Gabbay
635*e65e175bSOded Gabbay for (i = 0 ; i < events_num ; i++)
636*e65e175bSOded Gabbay output[i] = RREG32(base_reg + i * 8);
637*e65e175bSOded Gabbay
638*e65e175bSOded Gabbay output[overflow_idx] = RREG32(base_reg + 0xCC0);
639*e65e175bSOded Gabbay
640*e65e175bSOded Gabbay output[cycle_cnt_idx] = RREG32(base_reg + 0xFC);
641*e65e175bSOded Gabbay output[cycle_cnt_idx] <<= 32;
642*e65e175bSOded Gabbay output[cycle_cnt_idx] |= RREG32(base_reg + 0xF8);
643*e65e175bSOded Gabbay
644*e65e175bSOded Gabbay WREG32(base_reg + 0xCC0, 0);
645*e65e175bSOded Gabbay }
646*e65e175bSOded Gabbay
647*e65e175bSOded Gabbay return 0;
648*e65e175bSOded Gabbay }
649*e65e175bSOded Gabbay
goya_debug_coresight(struct hl_device * hdev,struct hl_ctx * ctx,void * data)650*e65e175bSOded Gabbay int goya_debug_coresight(struct hl_device *hdev, struct hl_ctx *ctx, void *data)
651*e65e175bSOded Gabbay {
652*e65e175bSOded Gabbay struct hl_debug_params *params = data;
653*e65e175bSOded Gabbay int rc = 0;
654*e65e175bSOded Gabbay
655*e65e175bSOded Gabbay switch (params->op) {
656*e65e175bSOded Gabbay case HL_DEBUG_OP_STM:
657*e65e175bSOded Gabbay rc = goya_config_stm(hdev, params);
658*e65e175bSOded Gabbay break;
659*e65e175bSOded Gabbay case HL_DEBUG_OP_ETF:
660*e65e175bSOded Gabbay rc = goya_config_etf(hdev, params);
661*e65e175bSOded Gabbay break;
662*e65e175bSOded Gabbay case HL_DEBUG_OP_ETR:
663*e65e175bSOded Gabbay rc = goya_config_etr(hdev, params);
664*e65e175bSOded Gabbay break;
665*e65e175bSOded Gabbay case HL_DEBUG_OP_FUNNEL:
666*e65e175bSOded Gabbay rc = goya_config_funnel(hdev, params);
667*e65e175bSOded Gabbay break;
668*e65e175bSOded Gabbay case HL_DEBUG_OP_BMON:
669*e65e175bSOded Gabbay rc = goya_config_bmon(hdev, params);
670*e65e175bSOded Gabbay break;
671*e65e175bSOded Gabbay case HL_DEBUG_OP_SPMU:
672*e65e175bSOded Gabbay rc = goya_config_spmu(hdev, params);
673*e65e175bSOded Gabbay break;
674*e65e175bSOded Gabbay case HL_DEBUG_OP_TIMESTAMP:
675*e65e175bSOded Gabbay /* Do nothing as this opcode is deprecated */
676*e65e175bSOded Gabbay break;
677*e65e175bSOded Gabbay
678*e65e175bSOded Gabbay default:
679*e65e175bSOded Gabbay dev_err(hdev->dev, "Unknown coresight id %d\n", params->op);
680*e65e175bSOded Gabbay return -EINVAL;
681*e65e175bSOded Gabbay }
682*e65e175bSOded Gabbay
683*e65e175bSOded Gabbay /* Perform read from the device to flush all configuration */
684*e65e175bSOded Gabbay RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
685*e65e175bSOded Gabbay
686*e65e175bSOded Gabbay return rc;
687*e65e175bSOded Gabbay }
688*e65e175bSOded Gabbay
goya_halt_coresight(struct hl_device * hdev,struct hl_ctx * ctx)689*e65e175bSOded Gabbay void goya_halt_coresight(struct hl_device *hdev, struct hl_ctx *ctx)
690*e65e175bSOded Gabbay {
691*e65e175bSOded Gabbay struct hl_debug_params params = {};
692*e65e175bSOded Gabbay int i, rc;
693*e65e175bSOded Gabbay
694*e65e175bSOded Gabbay for (i = GOYA_ETF_FIRST ; i <= GOYA_ETF_LAST ; i++) {
695*e65e175bSOded Gabbay params.reg_idx = i;
696*e65e175bSOded Gabbay rc = goya_config_etf(hdev, ¶ms);
697*e65e175bSOded Gabbay if (rc)
698*e65e175bSOded Gabbay dev_err(hdev->dev, "halt ETF failed, %d/%d\n", rc, i);
699*e65e175bSOded Gabbay }
700*e65e175bSOded Gabbay
701*e65e175bSOded Gabbay rc = goya_config_etr(hdev, ¶ms);
702*e65e175bSOded Gabbay if (rc)
703*e65e175bSOded Gabbay dev_err(hdev->dev, "halt ETR failed, %d\n", rc);
704*e65e175bSOded Gabbay }
705