1*2d48caa4SMike Looijmans0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 433 MHz (?) 2*2d48caa4SMike Looijmans0xf8000700 0x1210 // MIO configuration 3*2d48caa4SMike Looijmans0xf8000704 0x202 4*2d48caa4SMike Looijmans0xf8000708 0x202 5*2d48caa4SMike Looijmans0xf800070c 0x202 6*2d48caa4SMike Looijmans0xf8000710 0x202 7*2d48caa4SMike Looijmans0xf8000714 0x202 8*2d48caa4SMike Looijmans0xf8000718 0x202 9*2d48caa4SMike Looijmans0xf800071c 0x210 10*2d48caa4SMike Looijmans0xf8000720 0x202 11*2d48caa4SMike Looijmans0xf8000724 0x1210 12*2d48caa4SMike Looijmans0xf8000728 0x1210 13*2d48caa4SMike Looijmans0xf800072c 0x1210 14*2d48caa4SMike Looijmans0xf8000730 0x1210 15*2d48caa4SMike Looijmans0xf8000734 0x1210 16*2d48caa4SMike Looijmans0xf8000738 0x1211 17*2d48caa4SMike Looijmans0xf800073c 0x1200 18*2d48caa4SMike Looijmans0xf8000740 0x1210 19*2d48caa4SMike Looijmans0xf8000744 0x1210 20*2d48caa4SMike Looijmans0xf8000748 0x1210 21*2d48caa4SMike Looijmans0xf800074c 0x1210 22*2d48caa4SMike Looijmans0xf8000750 0x1210 23*2d48caa4SMike Looijmans0xf8000754 0x1210 24*2d48caa4SMike Looijmans0xf8000758 0x1210 25*2d48caa4SMike Looijmans0xf800075c 0x1210 26*2d48caa4SMike Looijmans0xf8000760 0x1201 27*2d48caa4SMike Looijmans0xf8000764 0x200 28*2d48caa4SMike Looijmans0xf8000768 0x12e1 29*2d48caa4SMike Looijmans0xf800076c 0x2e0 30*2d48caa4SMike Looijmans0xf8000770 0x304 31*2d48caa4SMike Looijmans0xf8000774 0x305 32*2d48caa4SMike Looijmans0xf8000778 0x304 33*2d48caa4SMike Looijmans0xf800077c 0x305 34*2d48caa4SMike Looijmans0xf8000780 0x304 35*2d48caa4SMike Looijmans0xf8000784 0x304 36*2d48caa4SMike Looijmans0xf8000788 0x304 37*2d48caa4SMike Looijmans0xf800078c 0x304 38*2d48caa4SMike Looijmans0xf8000790 0x305 39*2d48caa4SMike Looijmans0xf8000794 0x304 40*2d48caa4SMike Looijmans0xf8000798 0x304 41*2d48caa4SMike Looijmans0xf800079c 0x304 42*2d48caa4SMike Looijmans0xf80007a0 0x380 43*2d48caa4SMike Looijmans0xf80007a4 0x380 44*2d48caa4SMike Looijmans0xf80007a8 0x380 45*2d48caa4SMike Looijmans0xf80007ac 0x380 46*2d48caa4SMike Looijmans0xf80007b0 0x380 47*2d48caa4SMike Looijmans0xf80007b4 0x380 48*2d48caa4SMike Looijmans0xf80007b8 0x1261 49*2d48caa4SMike Looijmans0xf80007bc 0x1260 50*2d48caa4SMike Looijmans0xf80007c0 0x1261 51*2d48caa4SMike Looijmans0xf80007c4 0x1261 52*2d48caa4SMike Looijmans0xf80007c8 0x1240 53*2d48caa4SMike Looijmans0xf80007cc 0x1240 54*2d48caa4SMike Looijmans0xf80007d0 0x1240 55*2d48caa4SMike Looijmans0xf80007d4 0x1240 56*2d48caa4SMike Looijmans0xf8000830 0x180037 57*2d48caa4SMike Looijmans0xf8000834 0x3a0039 58*2d48caa4SMike Looijmans0xF800014C 0x00000621 // LQSPI_CLK_CTRL - ARMPLL/6 (200 MHz) 59*2d48caa4SMike Looijmans0xE000D000 0x800238C1 // QSPI config - divide-by-2 60*2d48caa4SMike Looijmans0xE000D038 0x00000020 // QSPI loopback - internal, 0 delay 61*2d48caa4SMike Looijmans0xE000D0A0 0x82FF04EB // LQSPI_CFG - QIOREAD mode, Numonyx/Micron 62