1a3355a23SLinus WalleijST-Ericsson Ux500 boards
2a3355a23SLinus Walleij------------------------
3a3355a23SLinus Walleij
4a3355a23SLinus WalleijRequired properties (in root node) one of these:
5a3355a23SLinus Walleij	compatible = "st-ericsson,mop500" (legacy)
6a3355a23SLinus Walleij	compatible = "st-ericsson,u8500"
7a3355a23SLinus Walleij
8a3355a23SLinus WalleijRequired node (under root node):
9a3355a23SLinus Walleij
10a3355a23SLinus Walleijsoc: represents the system-on-chip and contains the chip
11a3355a23SLinus Walleijperipherals
12a3355a23SLinus Walleij
13a3355a23SLinus WalleijRequired property of soc node, one of these:
14a3355a23SLinus Walleij	compatible = "stericsson,db8500"
15a3355a23SLinus Walleij
16a3355a23SLinus WalleijRequired subnodes under soc node:
17a3355a23SLinus Walleij
18a3355a23SLinus Walleijbackupram: (used for CPU spin tables and for storing data
19a3355a23SLinus Walleijduring retention, system won't boot without this):
20a3355a23SLinus Walleij	compatible = "ste,dbx500-backupram"
21a3355a23SLinus Walleij
22a3355a23SLinus Walleijscu:
23*2e684660SGeert Uytterhoeven	see binding for arm/arm,scu.yaml
24a3355a23SLinus Walleij
25a3355a23SLinus Walleijinterrupt-controller:
26ba180093SJon Hunter	see binding for interrupt-controller/arm,gic.txt
27a3355a23SLinus Walleij
28a3355a23SLinus Walleijtimer:
2950e02e9aSGeert Uytterhoeven	see binding for timer/arm,twd-timer.yaml
30a3355a23SLinus Walleij
31a3355a23SLinus Walleijclocks:
32a3355a23SLinus Walleij	see binding for clocks/ux500.txt
33a3355a23SLinus Walleij
34a3355a23SLinus WalleijExample:
35a3355a23SLinus Walleij
36a3355a23SLinus Walleij/dts-v1/;
37a3355a23SLinus Walleij
38a3355a23SLinus Walleij/ {
39a3355a23SLinus Walleij        model = "ST-Ericsson HREF (pre-v60) and ST UIB";
40a3355a23SLinus Walleij        compatible = "st-ericsson,mop500", "st-ericsson,u8500";
41a3355a23SLinus Walleij
42a3355a23SLinus Walleij        soc {
43a3355a23SLinus Walleij		#address-cells = <1>;
44a3355a23SLinus Walleij		#size-cells = <1>;
45a3355a23SLinus Walleij		compatible = "stericsson,db8500";
46a3355a23SLinus Walleij		interrupt-parent = <&intc>;
47a3355a23SLinus Walleij		ranges;
48a3355a23SLinus Walleij
49a3355a23SLinus Walleij		backupram@80150000 {
50a3355a23SLinus Walleij			compatible = "ste,dbx500-backupram";
51a3355a23SLinus Walleij			reg = <0x80150000 0x2000>;
52a3355a23SLinus Walleij		};
53a3355a23SLinus Walleij
54a3355a23SLinus Walleij		intc: interrupt-controller@a0411000 {
55a3355a23SLinus Walleij			compatible = "arm,cortex-a9-gic";
56a3355a23SLinus Walleij			#interrupt-cells = <3>;
57a3355a23SLinus Walleij			#address-cells = <1>;
58a3355a23SLinus Walleij			interrupt-controller;
59a3355a23SLinus Walleij			reg = <0xa0411000 0x1000>,
60a3355a23SLinus Walleij			      <0xa0410100 0x100>;
61a3355a23SLinus Walleij		};
62a3355a23SLinus Walleij
6366d77325SGeert Uytterhoeven		scu@a0410000 {
64a3355a23SLinus Walleij			compatible = "arm,cortex-a9-scu";
65a3355a23SLinus Walleij			reg = <0xa0410000 0x100>;
66a3355a23SLinus Walleij		};
67a3355a23SLinus Walleij
68a3355a23SLinus Walleij		timer@a0410600 {
69a3355a23SLinus Walleij			compatible = "arm,cortex-a9-twd-timer";
70a3355a23SLinus Walleij			reg = <0xa0410600 0x20>;
71a3355a23SLinus Walleij			interrupts = <1 13 0x304>; /* IRQ level high per-CPU */
72a3355a23SLinus Walleij			clocks = <&smp_twd_clk>;
73a3355a23SLinus Walleij		};
74a3355a23SLinus Walleij
75a3355a23SLinus Walleij		clocks {
76a3355a23SLinus Walleij			compatible = "stericsson,u8500-clks";
77a3355a23SLinus Walleij
78a3355a23SLinus Walleij			smp_twd_clk: smp-twd-clock {
79a3355a23SLinus Walleij				#clock-cells = <0>;
80a3355a23SLinus Walleij			};
81a3355a23SLinus Walleij		};
82a3355a23SLinus Walleij        };
83a3355a23SLinus Walleij};
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