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/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dpq3-esdhc-0.dtsi2 * PQ3 eSDHC device tree stub [ controller @ offset 0x2e000 ]
37 reg = <0x2e000 0x1000>;
38 interrupts = <72 0x2 0 0>;
40 clock-frequency = <0>;
/openbmc/linux/arch/arm64/boot/dts/realtek/
H A Drtd1619-mjolnir.dts17 reg = <0x2e000 0x7ffd2000>; /* boot ROM to 2 GiB */
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dti,icss-iep.yaml43 reg = <0x2e000 0x1000>;
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dfsl-esdhc.txt46 reg = <0x2e000 0x1000>;
47 interrupts = <42 0x8>;
50 clock-frequency = <0>;
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap5-l4-abe.dtsi1 &l4_abe { /* 0x40100000 */
3 reg = <0x40100000 0x400>,
4 <0x40100400 0x400>;
10 ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
11 <0x49000000 0x49000000 0x100000>;
12 segment@0 { /* 0x40100000 */
18 <0x00000000 0x00000000 0x000400>, /* ap 0 */
19 <0x00000400 0x00000400 0x000400>, /* ap 1 */
20 <0x00022000 0x00022000 0x001000>, /* ap 2 */
21 <0x00023000 0x00023000 0x001000>, /* ap 3 */
[all …]
H A Domap4-l4-abe.dtsi1 &l4_abe { /* 0x40100000 */
3 reg = <0x40100000 0x400>,
4 <0x40100400 0x400>;
10 ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
11 <0x49000000 0x49000000 0x100000>;
12 segment@0 { /* 0x40100000 */
18 <0x00000000 0x00000000 0x000400>, /* ap 0 */
19 <0x00000400 0x00000400 0x000400>, /* ap 1 */
20 <0x00022000 0x00022000 0x001000>, /* ap 2 */
21 <0x00023000 0x00023000 0x001000>, /* ap 3 */
[all …]
H A Ddm814x.dtsi31 #size-cells = <0>;
32 cpu@0 {
35 reg = <0>;
65 reg = <0x47400000 0x1000>;
73 reg = <0x47401300 0x100>;
76 #phy-cells = <0>;
81 reg = <0x47401400 0x400
82 0x47401000 0x200>;
94 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
95 &cppi41dma 2 0 &cppi41dma 3 0
[all …]
H A Ddra7-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
16 segment@0 { /* 0x4a000000 */
20 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8953-motorola-potter.dts18 qcom,msm-id = <293 0>;
19 qcom,board-id = <0x46 0x83a0>;
28 reg = <0 0x90001000 0 (2220 * 1920 * 3)>;
51 pinctrl-0 = <&gpio_key_default>;
62 reg = <0x0 0x84300000 0x0 0x2000000>;
67 reg = <0x0 0x90001000 0x0 (1080 * 1920 * 3)>;
72 reg = <0x0 0xaefd2000 0x0 0x2e000>;
77 reg = <0x0 0xeefe4000 0x0 0x1c000>;
83 reg = <0x0 0xef000000 0x0 0x80000>;
84 console-size = <0x40000>;
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dmpc8377_wlan.dts28 #size-cells = <0>;
30 PowerPC,8377@0 {
32 reg = <0x0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
45 reg = <0x00000000 0x20000000>; // 512MB at 0
52 reg = <0xe0005000 0x1000>;
53 interrupts = <77 0x8>;
55 ranges = <0x0 0x0 0xfc000000 0x04000000>;
[all …]
H A Dmpc8379_rdb.dts25 #size-cells = <0>;
27 PowerPC,8379@0 {
29 reg = <0x0>;
34 timebase-frequency = <0>;
35 bus-frequency = <0>;
36 clock-frequency = <0>;
42 reg = <0x00000000 0x10000000>; // 256MB at 0
49 reg = <0xe0005000 0x1000>;
50 interrupts = <77 0x8>;
56 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
H A Dmpc8377_rdb.dts27 #size-cells = <0>;
29 PowerPC,8377@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
44 reg = <0x00000000 0x10000000>; // 256MB at 0
51 reg = <0xe0005000 0x1000>;
52 interrupts = <77 0x8>;
58 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
H A Dmpc8378_rdb.dts27 #size-cells = <0>;
29 PowerPC,8378@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
44 reg = <0x00000000 0x10000000>; // 256MB at 0
51 reg = <0xe0005000 0x1000>;
52 interrupts = <77 0x8>;
58 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_9_0_sm8550.h12 .max_mixer_blendstages = 0xb,
24 .base = 0, .len = 0x494,
27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x4330, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x6330, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x8330, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0xa330, .bit_off = 0 },
31 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x24330, .bit_off = 0 },
32 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x26330, .bit_off = 0 },
33 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x28330, .bit_off = 0 },
34 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2a330, .bit_off = 0 },
[all …]
/openbmc/linux/drivers/gpu/drm/lima/
H A Dlima_device.c52 LIMA_IP_DESC(pmu, false, false, 0x02000, 0x02000, pmu, "pmu"),
53 LIMA_IP_DESC(l2_cache0, true, true, 0x01000, 0x10000, l2_cache, NULL),
54 LIMA_IP_DESC(l2_cache1, false, true, -1, 0x01000, l2_cache, NULL),
55 LIMA_IP_DESC(l2_cache2, false, false, -1, 0x11000, l2_cache, NULL),
56 LIMA_IP_DESC(gp, true, true, 0x00000, 0x00000, gp, "gp"),
57 LIMA_IP_DESC(pp0, true, true, 0x08000, 0x08000, pp, "pp0"),
58 LIMA_IP_DESC(pp1, false, false, 0x0A000, 0x0A000, pp, "pp1"),
59 LIMA_IP_DESC(pp2, false, false, 0x0C000, 0x0C000, pp, "pp2"),
60 LIMA_IP_DESC(pp3, false, false, 0x0E000, 0x0E000, pp, "pp3"),
61 LIMA_IP_DESC(pp4, false, false, -1, 0x28000, pp, "pp4"),
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dimmap_83xx.h36 u8 res0[0x04];
38 u8 res1[0x14];
40 u8 res2[0x20];
42 u8 res3[0x10];
44 u8 res4[0x10];
46 u8 res5[0x50];
50 u8 res6[0x04];
54 u8 res7[0x04];
55 u32 sidcr0; /* System I/O Delay Configuration Register 0 */
60 u8 res8[0xC];
[all …]
H A Dimmap_85xx.h28 #define CCSRAR_C 0x80000000 /* Commit */
37 u8 res3[0xbd4];
44 u8 res35[0x204];
57 u32 lawbar0; /* Local Access Window 0 Base Addr */
59 u32 lawar0; /* Local Access Window 0 Attrs */
117 #define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */
118 #define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */
177 u32 csmode[4]; /* 0x2c: sSPI CS0/1/2/3 mode */
178 u8 res2[4048]; /* fill up to 0x1000 */
191 u32 potar0; /* PCIX Outbound Transaction Addr 0 */
[all …]
/openbmc/linux/drivers/clk/qcom/
H A Dgcc-ipq4019.c112 .reg = 0x2e020,
120 .reg = 0x2f020,
171 return 0; in clk_cpu_div_set_rate()
214 { 384000000, P_XO, 0xd, 0, 0 },
215 { 413000000, P_XO, 0xc, 0, 0 },
216 { 448000000, P_XO, 0xb, 0, 0 },
217 { 488000000, P_XO, 0xa, 0, 0 },
218 { 512000000, P_XO, 0x9, 0, 0 },
219 { 537000000, P_XO, 0x8, 0, 0 },
220 { 565000000, P_XO, 0x7, 0, 0 },
[all …]
H A Dgcc-sm8450.c40 .offset = 0x0,
43 .enable_reg = 0x62018,
44 .enable_mask = BIT(0),
57 { 0x1, 2 },
62 .offset = 0x0,
79 .offset = 0x4000,
82 .enable_reg = 0x62018,
96 .offset = 0x9000,
99 .enable_reg = 0x62018,
113 { P_BI_TCXO, 0 },
[all …]
H A Dgcc-msm8916.c45 .l_reg = 0x21004,
46 .m_reg = 0x21008,
47 .n_reg = 0x2100c,
48 .config_reg = 0x21010,
49 .mode_reg = 0x21000,
50 .status_reg = 0x2101c,
63 .enable_reg = 0x45000,
64 .enable_mask = BIT(0),
76 .l_reg = 0x20004,
77 .m_reg = 0x20008,
[all …]
H A Dgcc-msm8996.c49 .offset = 0x00000,
52 .enable_reg = 0x52000,
53 .enable_mask = BIT(0),
79 .offset = 0x00000,
94 .enable_reg = 0x5200c,
95 .enable_mask = BIT(0),
111 .enable_reg = 0x5200c,
126 .offset = 0x77000,
129 .enable_reg = 0x52000,
143 .offset = 0x77000,
[all …]
H A Dgcc-msm8998.c27 #define GCC_MMSS_MISC 0x0902C
28 #define GCC_GPU_MISC 0x71028
31 { 250000000, 2000000000, 0 },
36 .offset = 0x0,
41 .enable_reg = 0x52000,
42 .enable_mask = BIT(0),
55 .offset = 0x0,
68 .offset = 0x0,
81 .offset = 0x0,
94 .offset = 0x0,
[all …]
H A Dgcc-ipq5018.c61 .offset = 0x21000,
64 .enable_reg = 0x0b000,
65 .enable_mask = BIT(0),
76 .offset = 0x4a000,
79 .enable_reg = 0x0b000,
91 .offset = 0x24000,
94 .enable_reg = 0x0b000,
106 .offset = 0x25000,
109 .enable_reg = 0x0b000,
121 .offset = 0x21000,
[all …]
H A Dgcc-ipq5332.c51 .offset = 0x20000,
54 .enable_reg = 0xb000,
55 .enable_mask = BIT(0),
78 .offset = 0x20000,
91 .offset = 0x21000,
94 .enable_reg = 0xb000,
106 .offset = 0x21000,
119 .offset = 0x22000,
122 .enable_reg = 0xb000,
145 .offset = 0x22000,
[all …]
/openbmc/linux/drivers/gpu/drm/i915/
H A Dintel_uncore.c66 uncore->debug->unclaimed_mmio_check = 0; in mmio_debug_suspend()
115 if (id >= 0 && id < FW_DOMAIN_ID_COUNT) in intel_uncore_forcewake_domain_to_str()
137 fw_clear(d, 0xefff); in fw_domain_reset()
139 fw_clear(d, 0xffff); in fw_domain_reset()
167 return __wait_for_ack(d, ack, 0); in wait_ack_clear()
183 if (fw_ack(d) == ~0) in fw_domain_wait_ack_clear()
185 "%s: MMIO unreliable (forcewake register returns 0xFFFFFFFF)!\n", in fw_domain_wait_ack_clear()
196 ACK_CLEAR = 0,
205 const u32 value = type == ACK_SET ? ack_bit : 0; in fw_domain_wait_ack_with_fallback()
238 "%s had to use fallback to %s ack, 0x%x (passes %u)\n", in fw_domain_wait_ack_with_fallback()
[all …]

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