Lines Matching +full:0 +full:x2e000
61 .offset = 0x21000,
64 .enable_reg = 0x0b000,
65 .enable_mask = BIT(0),
76 .offset = 0x4a000,
79 .enable_reg = 0x0b000,
91 .offset = 0x24000,
94 .enable_reg = 0x0b000,
106 .offset = 0x25000,
109 .enable_reg = 0x0b000,
121 .offset = 0x21000,
135 .offset = 0x4a000,
149 .offset = 0x24000,
163 .offset = 0x25000,
198 { P_XO, 0 },
209 { P_XO, 0 },
220 { P_XO, 0 },
232 { P_XO, 0 },
244 { P_XO, 0 },
257 { P_XO, 0 },
270 { P_XO, 0 },
282 { P_XO, 0 },
295 { P_XO, 0 },
309 { P_XO, 0 },
323 { P_XO, 0 },
330 { P_XO, 0 },
345 { P_XO, 0 },
361 { P_XO, 0 },
377 { P_XO, 0 },
393 { P_XO, 0 },
406 { P_PCIE20_PHY0_PIPE, 0 },
416 { P_PCIE20_PHY1_PIPE, 0 },
426 { P_USB3PHY_0_PIPE, 0 },
431 F(24000000, P_XO, 1, 0, 0),
432 F(100000000, P_GPLL0, 8, 0, 0),
437 .cmd_rcgr = 0x1f008,
450 F(50000000, P_GPLL0, 16, 0, 0),
455 .cmd_rcgr = 0x0200c,
468 .cmd_rcgr = 0x03000,
481 .cmd_rcgr = 0x04000,
495 F(4800000, P_XO, 5, 0, 0),
498 F(24000000, P_XO, 1, 0, 0),
499 F(50000000, P_GPLL0, 16, 0, 0),
504 .cmd_rcgr = 0x02024,
518 .cmd_rcgr = 0x03014,
532 .cmd_rcgr = 0x04014,
549 F(24000000, P_XO, 1, 0, 0),
563 .cmd_rcgr = 0x02044,
577 .cmd_rcgr = 0x03034,
591 F(160000000, P_GPLL0, 5, 0, 0),
596 .cmd_rcgr = 0x16004,
609 F(2500000, P_GEPHY_TX, 5, 0, 0),
610 F(24000000, P_XO, 1, 0, 0),
611 F(25000000, P_GEPHY_TX, 5, 0, 0),
612 F(125000000, P_GEPHY_TX, 1, 0, 0),
617 .cmd_rcgr = 0x68020,
630 .reg = 0x68420,
631 .shift = 0,
647 .cmd_rcgr = 0x68028,
660 .reg = 0x68424,
661 .shift = 0,
677 F(2500000, P_UNIPHY_RX, 12.5, 0, 0),
678 F(24000000, P_XO, 1, 0, 0),
679 F(25000000, P_UNIPHY_RX, 2.5, 0, 0),
680 F(125000000, P_UNIPHY_RX, 2.5, 0, 0),
681 F(125000000, P_UNIPHY_RX, 1, 0, 0),
682 F(312500000, P_UNIPHY_RX, 1, 0, 0),
687 .cmd_rcgr = 0x68030,
700 .reg = 0x68430,
701 .shift = 0,
717 F(2500000, P_UNIPHY_TX, 12.5, 0, 0),
718 F(24000000, P_XO, 1, 0, 0),
719 F(25000000, P_UNIPHY_TX, 2.5, 0, 0),
720 F(125000000, P_UNIPHY_TX, 2.5, 0, 0),
721 F(125000000, P_UNIPHY_TX, 1, 0, 0),
722 F(312500000, P_UNIPHY_TX, 1, 0, 0),
727 .cmd_rcgr = 0x68038,
740 .reg = 0x68434,
741 .shift = 0,
757 F(240000000, P_GPLL4, 5, 0, 0),
762 .cmd_rcgr = 0x68080,
775 F(200000000, P_GPLL0, 4, 0, 0),
780 .cmd_rcgr = 0x08004,
794 .cmd_rcgr = 0x09004,
808 .cmd_rcgr = 0x0a004,
822 F(133333334, P_GPLL0, 6, 0, 0),
827 .cmd_rcgr = 0x2e028,
840 F(66666667, P_GPLL0, 12, 0, 0),
845 .cmd_rcgr = 0x2e040,
858 F(2000000, P_XO, 12, 0, 0),
863 .cmd_rcgr = 0x75020,
877 F(240000000, P_GPLL4, 5, 0, 0),
882 .cmd_rcgr = 0x75050,
895 .cmd_rcgr = 0x76020,
909 .cmd_rcgr = 0x76050,
922 .reg = 0x7501c,
938 .reg = 0x7601c,
953 F(100000000, P_GPLL0, 8, 0, 0),
958 .cmd_rcgr = 0x27000,
985 F(240000000, P_GPLL4, 5, 0, 0),
990 .cmd_rcgr = 0x2900c,
1003 F(200000000, P_GPLL0, 4, 0, 0),
1008 .cmd_rcgr = 0x2902c,
1021 F(266666667, P_GPLL0, 3, 0, 0),
1026 .cmd_rcgr = 0x29048,
1039 F(600000000, P_GPLL4, 2, 0, 0),
1044 .cmd_rcgr = 0x29064,
1098 F(24000000, P_XO, 1, 0, 0),
1099 F(100000000, P_GPLL0, 8, 0, 0),
1100 F(200000000, P_GPLL0, 4, 0, 0),
1101 F(320000000, P_GPLL0, 2.5, 0, 0),
1106 .cmd_rcgr = 0x57010,
1121 F(24000000, P_XO, 1, 0, 0),
1123 F(96000000, P_GPLL2, 12, 0, 0),
1125 F(192000000, P_GPLL2, 6, 0, 0),
1126 F(200000000, P_GPLL0, 4, 0, 0),
1131 .cmd_rcgr = 0x42004,
1145 F(266666667, P_GPLL0, 3, 0, 0),
1150 .cmd_rcgr = 0x26004,
1177 F(400000000, P_GPLL0, 2, 0, 0),
1182 .cmd_rcgr = 0x68088,
1196 F(850000000, P_UBI32_PLL, 1, 0, 0),
1197 F(1000000000, P_UBI32_PLL, 1, 0, 0),
1202 .cmd_rcgr = 0x68100,
1216 .cmd_rcgr = 0x3e05c,
1235 .cmd_rcgr = 0x3e090,
1249 .cmd_rcgr = 0x3e00c,
1268 .cmd_rcgr = 0x3e020,
1282 .reg = 0x3e048,
1298 F(400000000, P_GPLL0, 2, 0, 0),
1303 .cmd_rcgr = 0x59120,
1316 F(133333333, P_GPLL0, 6, 0, 0),
1321 .cmd_rcgr = 0x59020,
1334 .halt_reg = 0x30000,
1336 .enable_reg = 0x30000,
1348 .halt_reg = 0x30018,
1350 .enable_reg = 0x30018,
1363 .halt_reg = 0x30030,
1365 .enable_reg = 0x30030,
1366 .enable_mask = BIT(0),
1380 .halt_reg = 0x1f020,
1382 .enable_reg = 0x1f020,
1383 .enable_mask = BIT(0),
1397 .halt_reg = 0x01008,
1400 .enable_reg = 0x0b004,
1415 .halt_reg = 0x02008,
1417 .enable_reg = 0x02008,
1418 .enable_mask = BIT(0),
1432 .halt_reg = 0x02004,
1434 .enable_reg = 0x02004,
1435 .enable_mask = BIT(0),
1449 .halt_reg = 0x03010,
1451 .enable_reg = 0x03010,
1452 .enable_mask = BIT(0),
1466 .halt_reg = 0x0300c,
1468 .enable_reg = 0x0300c,
1469 .enable_mask = BIT(0),
1483 .halt_reg = 0x04010,
1485 .enable_reg = 0x04010,
1486 .enable_mask = BIT(0),
1500 .halt_reg = 0x0400c,
1502 .enable_reg = 0x0400c,
1503 .enable_mask = BIT(0),
1517 .halt_reg = 0x0203c,
1519 .enable_reg = 0x0203c,
1520 .enable_mask = BIT(0),
1534 .halt_reg = 0x0302c,
1536 .enable_reg = 0x0302c,
1537 .enable_mask = BIT(0),
1551 .halt_reg = 0x1c004,
1553 .enable_reg = 0x1c004,
1554 .enable_mask = BIT(0),
1563 .halt_reg = 0x56308,
1565 .enable_reg = 0x56308,
1566 .enable_mask = BIT(0),
1580 .halt_reg = 0x5630c,
1582 .enable_reg = 0x5630c,
1583 .enable_mask = BIT(0),
1597 .halt_reg = 0x16024,
1600 .enable_reg = 0x0b004,
1601 .enable_mask = BIT(0),
1615 .halt_reg = 0x16020,
1618 .enable_reg = 0x0b004,
1633 .halt_reg = 0x1601c,
1636 .enable_reg = 0x0b004,
1651 .halt_reg = 0x77004,
1653 .enable_reg = 0x77004,
1654 .enable_mask = BIT(0),
1668 .halt_reg = 0x56010,
1671 .enable_reg = 0x56010,
1672 .enable_mask = BIT(0),
1686 .halt_reg = 0x56014,
1689 .enable_reg = 0x56014,
1690 .enable_mask = BIT(0),
1704 .halt_reg = 0x68304,
1706 .enable_reg = 0x68304,
1707 .enable_mask = BIT(0),
1721 .halt_reg = 0x68300,
1723 .enable_reg = 0x68300,
1724 .enable_mask = BIT(0),
1738 .halt_reg = 0x68240,
1740 .enable_reg = 0x68240,
1741 .enable_mask = BIT(0),
1755 .halt_reg = 0x68190,
1759 .enable_reg = 0x68190,
1760 .enable_mask = BIT(0),
1774 .halt_reg = 0x68244,
1776 .enable_reg = 0x68244,
1777 .enable_mask = BIT(0),
1791 .halt_reg = 0x68324,
1793 .enable_reg = 0x68324,
1794 .enable_mask = BIT(0),
1808 .halt_reg = 0x68320,
1810 .enable_reg = 0x68320,
1811 .enable_mask = BIT(0),
1825 .halt_reg = 0x68248,
1827 .enable_reg = 0x68248,
1828 .enable_mask = BIT(0),
1842 .halt_reg = 0x68310,
1844 .enable_reg = 0x68310,
1845 .enable_mask = BIT(0),
1859 .halt_reg = 0x6824c,
1861 .enable_reg = 0x6824c,
1862 .enable_mask = BIT(0),
1876 .halt_reg = 0x08000,
1878 .enable_reg = 0x08000,
1879 .enable_mask = BIT(0),
1893 .halt_reg = 0x09000,
1895 .enable_reg = 0x09000,
1896 .enable_mask = BIT(0),
1910 .halt_reg = 0x0a000,
1912 .enable_reg = 0x0a000,
1913 .enable_mask = BIT(0),
1927 .halt_reg = 0x2e048,
1930 .enable_reg = 0x2e048,
1931 .enable_mask = BIT(0),
1945 .halt_reg = 0x2e04c,
1947 .enable_reg = 0x2e04c,
1948 .enable_mask = BIT(0),
1962 .halt_reg = 0x58004,
1964 .enable_reg = 0x58004,
1965 .enable_mask = BIT(0),
1979 .halt_reg = 0x58014,
1981 .enable_reg = 0x58014,
1982 .enable_mask = BIT(0),
1996 .halt_reg = 0x75010,
1998 .enable_reg = 0x75010,
1999 .enable_mask = BIT(0),
2013 .halt_reg = 0x75014,
2015 .enable_reg = 0x75014,
2016 .enable_mask = BIT(0),
2030 .halt_reg = 0x75008,
2032 .enable_reg = 0x75008,
2033 .enable_mask = BIT(0),
2047 .halt_reg = 0x75048,
2049 .enable_reg = 0x75048,
2050 .enable_mask = BIT(0),
2064 .halt_reg = 0x7500c,
2066 .enable_reg = 0x7500c,
2067 .enable_mask = BIT(0),
2081 .halt_reg = 0x75018,
2085 .enable_reg = 0x75018,
2086 .enable_mask = BIT(0),
2100 .halt_reg = 0x76010,
2102 .enable_reg = 0x76010,
2103 .enable_mask = BIT(0),
2117 .halt_reg = 0x76014,
2119 .enable_reg = 0x76014,
2120 .enable_mask = BIT(0),
2134 .halt_reg = 0x76008,
2136 .enable_reg = 0x76008,
2137 .enable_mask = BIT(0),
2151 .halt_reg = 0x76048,
2153 .enable_reg = 0x76048,
2154 .enable_mask = BIT(0),
2168 .halt_reg = 0x7600c,
2170 .enable_reg = 0x7600c,
2171 .enable_mask = BIT(0),
2185 .halt_reg = 0x76018,
2189 .enable_reg = 0x76018,
2190 .enable_mask = BIT(0),
2204 .halt_reg = 0x13004,
2207 .enable_reg = 0x0b004,
2222 .halt_reg = 0x59138,
2224 .enable_reg = 0x59138,
2225 .enable_mask = BIT(0),
2239 .halt_reg = 0x5914c,
2241 .enable_reg = 0x5914c,
2242 .enable_mask = BIT(0),
2256 .halt_reg = 0x5913c,
2258 .enable_reg = 0x5913c,
2259 .enable_mask = BIT(0),
2273 .halt_reg = 0x59150,
2275 .enable_reg = 0x59150,
2276 .enable_mask = BIT(0),
2290 .halt_reg = 0x59154,
2292 .enable_reg = 0x59154,
2293 .enable_mask = BIT(0),
2307 .halt_reg = 0x59148,
2309 .enable_reg = 0x59148,
2310 .enable_mask = BIT(0),
2324 .halt_reg = 0x59144,
2326 .enable_reg = 0x59144,
2327 .enable_mask = BIT(0),
2341 .halt_reg = 0x59140,
2343 .enable_reg = 0x59140,
2344 .enable_mask = BIT(0),
2358 .halt_reg = 0x59128,
2360 .enable_reg = 0x59128,
2361 .enable_mask = BIT(0),
2375 .halt_reg = 0x29024,
2377 .enable_reg = 0x29024,
2378 .enable_mask = BIT(0),
2392 .halt_reg = 0x29084,
2394 .enable_reg = 0x29084,
2395 .enable_mask = BIT(0),
2409 .halt_reg = 0x29008,
2411 .enable_reg = 0x29008,
2412 .enable_mask = BIT(0),
2426 .halt_reg = 0x29004,
2428 .enable_reg = 0x29004,
2429 .enable_mask = BIT(0),
2443 .halt_reg = 0x29028,
2445 .enable_reg = 0x29028,
2446 .enable_mask = BIT(0),
2460 .halt_reg = 0x29020,
2462 .enable_reg = 0x29020,
2463 .enable_mask = BIT(0),
2477 .halt_reg = 0x29044,
2479 .enable_reg = 0x29044,
2480 .enable_mask = BIT(0),
2494 .halt_reg = 0x29060,
2496 .enable_reg = 0x29060,
2497 .enable_mask = BIT(0),
2511 .halt_reg = 0x2908c,
2513 .enable_reg = 0x2908c,
2514 .enable_mask = BIT(0),
2528 .halt_reg = 0x57024,
2530 .enable_reg = 0x57024,
2531 .enable_mask = BIT(0),
2545 .halt_reg = 0x57020,
2547 .enable_reg = 0x57020,
2548 .enable_mask = BIT(0),
2562 .halt_reg = 0x5701c,
2564 .enable_reg = 0x5701c,
2565 .enable_mask = BIT(0),
2579 .halt_reg = 0x4201c,
2581 .enable_reg = 0x4201c,
2582 .enable_mask = BIT(0),
2596 .halt_reg = 0x42018,
2598 .enable_reg = 0x42018,
2599 .enable_mask = BIT(0),
2613 .halt_reg = 0x260a0,
2615 .enable_reg = 0x260a0,
2616 .enable_mask = BIT(0),
2630 .halt_reg = 0x26084,
2632 .enable_reg = 0x26084,
2633 .enable_mask = BIT(0),
2647 .halt_reg = 0x260a4,
2649 .enable_reg = 0x260a4,
2650 .enable_mask = BIT(0),
2664 .halt_reg = 0x26088,
2666 .enable_reg = 0x26088,
2667 .enable_mask = BIT(0),
2681 .halt_reg = 0x26074,
2683 .enable_reg = 0x26074,
2684 .enable_mask = BIT(0),
2698 .halt_reg = 0x26078,
2700 .enable_reg = 0x26078,
2701 .enable_mask = BIT(0),
2715 .halt_reg = 0x26094,
2717 .enable_reg = 0x26094,
2718 .enable_mask = BIT(0),
2732 .halt_reg = 0x26048,
2734 .enable_reg = 0x26048,
2735 .enable_mask = BIT(0),
2749 .halt_reg = 0x2604c,
2751 .enable_reg = 0x2604c,
2752 .enable_mask = BIT(0),
2766 .halt_reg = 0x26024,
2768 .enable_reg = 0x26024,
2769 .enable_mask = BIT(0),
2783 .halt_reg = 0x26040,
2785 .enable_reg = 0x26040,
2786 .enable_mask = BIT(0),
2800 .halt_reg = 0x26034,
2802 .enable_reg = 0x26034,
2803 .enable_mask = BIT(0),
2817 .halt_reg = 0x68200,
2820 .enable_reg = 0x68200,
2821 .enable_mask = BIT(0),
2835 .halt_reg = 0x68160,
2838 .enable_reg = 0x68160,
2839 .enable_mask = BIT(0),
2853 .halt_reg = 0x68214,
2856 .enable_reg = 0x68214,
2857 .enable_mask = BIT(0),
2871 .halt_reg = 0x68210,
2874 .enable_reg = 0x68210,
2875 .enable_mask = BIT(0),
2889 .halt_reg = 0x68204,
2892 .enable_reg = 0x68204,
2893 .enable_mask = BIT(0),
2907 .halt_reg = 0x68208,
2910 .enable_reg = 0x68208,
2911 .enable_mask = BIT(0),
2925 .halt_reg = 0x56108,
2927 .enable_reg = 0x56108,
2928 .enable_mask = BIT(0),
2942 .halt_reg = 0x56110,
2944 .enable_reg = 0x56110,
2945 .enable_mask = BIT(0),
2959 .halt_reg = 0x56114,
2961 .enable_reg = 0x56114,
2962 .enable_mask = BIT(0),
2976 .halt_reg = 0x5610c,
2978 .enable_reg = 0x5610c,
2979 .enable_mask = BIT(0),
2993 .halt_reg = 0x3e044,
2995 .enable_reg = 0x3e044,
2996 .enable_mask = BIT(0),
3010 .halt_reg = 0x3e04c,
3013 .enable_reg = 0x3e04c,
3014 .enable_mask = BIT(0),
3028 .halt_reg = 0x3e050,
3030 .enable_reg = 0x3e050,
3031 .enable_mask = BIT(0),
3045 .halt_reg = 0x3e000,
3047 .enable_reg = 0x3e000,
3048 .enable_mask = BIT(0),
3062 .halt_reg = 0x3e008,
3064 .enable_reg = 0x3e008,
3065 .enable_mask = BIT(0),
3079 .halt_reg = 0x3e080,
3081 .enable_reg = 0x3e080,
3082 .enable_mask = BIT(0),
3096 .halt_reg = 0x3e004,
3098 .enable_reg = 0x3e004,
3099 .enable_mask = BIT(0),
3113 .halt_reg = 0x3e040,
3116 .enable_reg = 0x3e040,
3117 .enable_mask = BIT(0),
3131 .halt_reg = 0x59064,
3133 .enable_reg = 0x59064,
3134 .enable_mask = BIT(0),
3148 .halt_reg = 0x59034,
3150 .enable_reg = 0x59034,
3151 .enable_mask = BIT(0),
3165 .halt_reg = 0x5903c,
3167 .enable_reg = 0x5903c,
3168 .enable_mask = BIT(0),
3182 .halt_reg = 0x59068,
3184 .enable_reg = 0x59068,
3185 .enable_mask = BIT(0),
3199 .halt_reg = 0x59050,
3201 .enable_reg = 0x59050,
3202 .enable_mask = BIT(0),
3216 .halt_reg = 0x59040,
3218 .enable_reg = 0x59040,
3219 .enable_mask = BIT(0),
3233 .halt_reg = 0x59054,
3235 .enable_reg = 0x59054,
3236 .enable_mask = BIT(0),
3250 .halt_reg = 0x59044,
3252 .enable_reg = 0x59044,
3253 .enable_mask = BIT(0),
3267 .halt_reg = 0x59060,
3269 .enable_reg = 0x59060,
3270 .enable_mask = BIT(0),
3284 .halt_reg = 0x5905c,
3286 .enable_reg = 0x5905c,
3287 .enable_mask = BIT(0),
3301 .halt_reg = 0x59058,
3303 .enable_reg = 0x59058,
3304 .enable_mask = BIT(0),
3318 .halt_reg = 0x59048,
3320 .enable_reg = 0x59048,
3321 .enable_mask = BIT(0),
3335 .halt_reg = 0x59038,
3337 .enable_reg = 0x59038,
3338 .enable_mask = BIT(0),
3361 .l = 0x29,
3362 .alpha = 0xaaaaaaaa,
3363 .alpha_hi = 0xaa,
3364 .config_ctl_val = 0x4001075b,
3365 .main_output_mask = BIT(0),
3368 .vco_val = 0x1,
3370 .test_ctl_val = 0x0,
3371 .test_ctl_hi_val = 0x0,
3551 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
3552 [GCC_BLSP1_BCR] = { 0x01000, 0 },
3553 [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
3554 [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
3555 [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
3556 [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
3557 [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
3558 [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
3559 [GCC_BTSS_BCR] = { 0x1c000, 0 },
3560 [GCC_CMN_BLK_BCR] = { 0x56300, 0 },
3561 [GCC_CMN_LDO_BCR] = { 0x33000, 0 },
3562 [GCC_CE_BCR] = { 0x33014, 0 },
3563 [GCC_CRYPTO_BCR] = { 0x16000, 0 },
3564 [GCC_DCC_BCR] = { 0x77000, 0 },
3565 [GCC_DCD_BCR] = { 0x2a000, 0 },
3566 [GCC_DDRSS_BCR] = { 0x1e000, 0 },
3567 [GCC_EDPD_BCR] = { 0x3a000, 0 },
3568 [GCC_GEPHY_BCR] = { 0x56000, 0 },
3569 [GCC_GEPHY_MDC_SW_ARES] = { 0x56004, 0 },
3570 [GCC_GEPHY_DSP_HW_ARES] = { 0x56004, 1 },
3571 [GCC_GEPHY_RX_ARES] = { 0x56004, 2 },
3572 [GCC_GEPHY_TX_ARES] = { 0x56004, 3 },
3573 [GCC_GMAC0_BCR] = { 0x19000, 0 },
3574 [GCC_GMAC0_CFG_ARES] = { 0x68428, 0 },
3575 [GCC_GMAC0_SYS_ARES] = { 0x68428, 1 },
3576 [GCC_GMAC1_BCR] = { 0x19100, 0 },
3577 [GCC_GMAC1_CFG_ARES] = { 0x68438, 0 },
3578 [GCC_GMAC1_SYS_ARES] = { 0x68438, 1 },
3579 [GCC_IMEM_BCR] = { 0x0e000, 0 },
3580 [GCC_LPASS_BCR] = { 0x2e000, 0 },
3581 [GCC_MDIO0_BCR] = { 0x58000, 0 },
3582 [GCC_MDIO1_BCR] = { 0x58010, 0 },
3583 [GCC_MPM_BCR] = { 0x2c000, 0 },
3584 [GCC_PCIE0_BCR] = { 0x75004, 0 },
3585 [GCC_PCIE0_LINK_DOWN_BCR] = { 0x750a8, 0 },
3586 [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
3587 [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
3588 [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
3589 [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
3590 [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
3591 [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
3592 [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
3593 [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
3594 [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
3595 [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
3596 [GCC_PCIE1_BCR] = { 0x76004, 0 },
3597 [GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
3598 [GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
3599 [GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
3600 [GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
3601 [GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
3602 [GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
3603 [GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },
3604 [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
3605 [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
3606 [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
3607 [GCC_PCIE1_AXI_SLAVE_STICKY_ARES] = { 0x76040, 7 },
3608 [GCC_PCNOC_BCR] = { 0x27018, 0 },
3609 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
3610 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
3611 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
3612 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
3613 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
3614 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
3615 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
3616 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
3617 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
3618 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
3619 [GCC_PCNOC_BUS_TIMEOUT10_BCR] = { 0x48050, 0 },
3620 [GCC_PCNOC_BUS_TIMEOUT11_BCR] = { 0x48058, 0 },
3621 [GCC_PRNG_BCR] = { 0x13000, 0 },
3622 [GCC_Q6SS_DBG_ARES] = { 0x59110, 0 },
3623 [GCC_Q6_AHB_S_ARES] = { 0x59110, 1 },
3624 [GCC_Q6_AHB_ARES] = { 0x59110, 2 },
3625 [GCC_Q6_AXIM2_ARES] = { 0x59110, 3 },
3626 [GCC_Q6_AXIM_ARES] = { 0x59110, 4 },
3627 [GCC_Q6_AXIS_ARES] = { 0x59158, 0 },
3628 [GCC_QDSS_BCR] = { 0x29000, 0 },
3629 [GCC_QPIC_BCR] = { 0x57018, 0 },
3630 [GCC_QUSB2_0_PHY_BCR] = { 0x41030, 0 },
3631 [GCC_SDCC1_BCR] = { 0x42000, 0 },
3632 [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
3633 [GCC_SPDM_BCR] = { 0x2f000, 0 },
3634 [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
3635 [GCC_TCSR_BCR] = { 0x28000, 0 },
3636 [GCC_TLMM_BCR] = { 0x34000, 0 },
3637 [GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
3638 [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
3639 [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
3640 [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
3641 [GCC_UBI0_UTCM_ARES] = { 0x68010, 6 },
3642 [GCC_UBI0_CORE_ARES] = { 0x68010, 7 },
3643 [GCC_UBI32_BCR] = { 0x19064, 0 },
3644 [GCC_UNIPHY_BCR] = { 0x56100, 0 },
3645 [GCC_UNIPHY_AHB_ARES] = { 0x56104, 0 },
3646 [GCC_UNIPHY_SYS_ARES] = { 0x56104, 1 },
3647 [GCC_UNIPHY_RX_ARES] = { 0x56104, 4 },
3648 [GCC_UNIPHY_TX_ARES] = { 0x56104, 5 },
3649 [GCC_UNIPHY_SOFT_RESET] = {0x56104, 0 },
3650 [GCC_USB0_BCR] = { 0x3e070, 0 },
3651 [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
3652 [GCC_WCSS_BCR] = { 0x18000, 0 },
3653 [GCC_WCSS_DBG_ARES] = { 0x59008, 0 },
3654 [GCC_WCSS_ECAHB_ARES] = { 0x59008, 1 },
3655 [GCC_WCSS_ACMT_ARES] = { 0x59008, 2 },
3656 [GCC_WCSS_DBG_BDG_ARES] = { 0x59008, 3 },
3657 [GCC_WCSS_AHB_S_ARES] = { 0x59008, 4 },
3658 [GCC_WCSS_AXI_M_ARES] = { 0x59008, 5 },
3659 [GCC_WCSS_AXI_S_ARES] = { 0x59008, 6 },
3660 [GCC_WCSS_Q6_BCR] = { 0x18004, 0 },
3661 [GCC_WCSSAON_RESET] = { 0x59010, 0},
3662 [GCC_GEPHY_MISC_ARES] = { 0x56004, 0 },
3675 .max_register = 0x7fffc,