Lines Matching +full:0 +full:x2e000
51 .offset = 0x20000,
54 .enable_reg = 0xb000,
55 .enable_mask = BIT(0),
78 .offset = 0x20000,
91 .offset = 0x21000,
94 .enable_reg = 0xb000,
106 .offset = 0x21000,
119 .offset = 0x22000,
122 .enable_reg = 0xb000,
145 .offset = 0x22000,
158 { P_XO, 0 },
162 { P_XO, 0 },
174 { P_XO, 0 },
184 { P_XO, 0 },
196 { P_XO, 0 },
210 { P_XO, 0 },
224 { P_XO, 0 },
238 { P_XO, 0 },
254 { P_XO, 0 },
266 { P_XO, 0 },
288 { P_XO, 0 },
302 { P_XO, 0 },
314 { P_XO, 0 },
328 F(24000000, P_XO, 1, 0, 0),
329 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
334 .cmd_rcgr = 0x1c004,
335 .mnd_width = 0,
348 F(480000000, P_GPLL4_OUT_AUX, 2.5, 0, 0),
349 F(533333333, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
355 F(4800000, P_XO, 5, 0, 0),
356 F(9600000, P_XO, 2.5, 0, 0),
358 F(24000000, P_XO, 1, 0, 0),
360 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
365 .cmd_rcgr = 0x2004,
379 .cmd_rcgr = 0x3004,
393 .cmd_rcgr = 0x4004,
410 F(24000000, P_XO, 1, 0, 0),
420 F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
425 .cmd_rcgr = 0x202c,
439 .cmd_rcgr = 0x302c,
453 .cmd_rcgr = 0x402c,
467 F(24000000, P_XO, 1, 0, 0),
468 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
473 .cmd_rcgr = 0x8004,
487 .cmd_rcgr = 0x9004,
501 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
506 .cmd_rcgr = 0x27004,
507 .mnd_width = 0,
520 F(24000000, P_XO, 1, 0, 0),
525 .cmd_rcgr = 0x17088,
526 .mnd_width = 0,
539 F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0),
544 .cmd_rcgr = 0x29018,
545 .mnd_width = 0,
558 .cmd_rcgr = 0x2907c,
571 .halt_reg = 0x2907c,
573 .enable_reg = 0x2907c,
587 .cmd_rcgr = 0x2a004,
588 .mnd_width = 0,
601 .cmd_rcgr = 0x2a078,
614 .halt_reg = 0x2a078,
616 .enable_reg = 0x2a078,
630 F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0),
635 .cmd_rcgr = 0x28018,
636 .mnd_width = 0,
649 .cmd_rcgr = 0x28084,
650 .mnd_width = 0,
663 .cmd_rcgr = 0x28078,
664 .mnd_width = 0,
677 .halt_reg = 0x28078,
679 .enable_reg = 0x28078,
693 F(2000000, P_XO, 12, 0, 0),
698 .cmd_rcgr = 0x28004,
712 .reg = 0x28064,
726 .reg = 0x29064,
740 .reg = 0x2a064,
754 F(24000000, P_XO, 1, 0, 0),
755 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
756 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
761 .cmd_rcgr = 0x31004,
762 .mnd_width = 0,
775 .cmd_rcgr = 0x25004,
776 .mnd_width = 0,
789 F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0),
794 .cmd_rcgr = 0x2d004,
795 .mnd_width = 0,
808 F(600000000, P_GPLL4_OUT_MAIN, 2, 0, 0),
813 .cmd_rcgr = 0x2d01c,
814 .mnd_width = 0,
888 F(24000000, P_XO, 1, 0, 0),
889 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
890 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
891 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
896 .cmd_rcgr = 0x32004,
897 .mnd_width = 0,
912 F(24000000, P_XO, 1, 0, 0),
914 F(96000000, P_GPLL2_OUT_MAIN, 12, 0, 0),
915 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
916 F(192000000, P_GPLL2_OUT_MAIN, 6, 0, 0),
917 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
922 .cmd_rcgr = 0x33004,
936 F(32000, P_SLEEP_CLK, 1, 0, 0),
941 .cmd_rcgr = 0x3400c,
942 .mnd_width = 0,
955 F(24000000, P_XO, 1, 0, 0),
956 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
957 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
958 F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0),
963 .cmd_rcgr = 0x2e004,
964 .mnd_width = 0,
990 .cmd_rcgr = 0x16004,
991 .mnd_width = 0,
1004 .cmd_rcgr = 0x2c018,
1023 .cmd_rcgr = 0x2c07c,
1037 .cmd_rcgr = 0x2c004,
1056 .cmd_rcgr = 0x2c02c,
1070 .reg = 0x2c074,
1084 .cmd_rcgr = 0x25030,
1085 .mnd_width = 0,
1098 .cmd_rcgr = 0x34004,
1099 .mnd_width = 0,
1125 .reg = 0x2d028,
1126 .shift = 0,
1139 .reg = 0x2c040,
1140 .shift = 0,
1154 .halt_reg = 0x1c00c,
1157 .enable_reg = 0x1c00c,
1158 .enable_mask = BIT(0),
1172 .halt_reg = 0x34024,
1175 .enable_reg = 0x34024,
1176 .enable_mask = BIT(0),
1190 .halt_reg = 0x1008,
1193 .enable_reg = 0xb004,
1208 .halt_reg = 0x2024,
1211 .enable_reg = 0x2024,
1212 .enable_mask = BIT(0),
1226 .halt_reg = 0x2020,
1229 .enable_reg = 0x2020,
1230 .enable_mask = BIT(0),
1244 .halt_reg = 0x3024,
1247 .enable_reg = 0x3024,
1248 .enable_mask = BIT(0),
1262 .halt_reg = 0x3020,
1265 .enable_reg = 0x3020,
1266 .enable_mask = BIT(0),
1280 .halt_reg = 0x4024,
1283 .enable_reg = 0x4024,
1284 .enable_mask = BIT(0),
1298 .halt_reg = 0x4020,
1301 .enable_reg = 0x4020,
1302 .enable_mask = BIT(0),
1316 .halt_reg = 0x1010,
1319 .enable_reg = 0xb004,
1334 .halt_reg = 0x2040,
1337 .enable_reg = 0x2040,
1338 .enable_mask = BIT(0),
1352 .halt_reg = 0x3040,
1355 .enable_reg = 0x3040,
1356 .enable_mask = BIT(0),
1370 .halt_reg = 0x4054,
1373 .enable_reg = 0x4054,
1374 .enable_mask = BIT(0),
1388 .halt_reg = 0x25074,
1391 .enable_reg = 0x25074,
1392 .enable_mask = BIT(0),
1406 .halt_reg = 0x25068,
1409 .enable_reg = 0x25068,
1410 .enable_mask = BIT(0),
1424 .halt_reg = 0x25070,
1427 .enable_reg = 0x25070,
1428 .enable_mask = BIT(0),
1442 .halt_reg = 0x3a004,
1445 .enable_reg = 0x3a004,
1446 .enable_mask = BIT(0),
1460 .halt_reg = 0x3a00c,
1463 .enable_reg = 0x3a00c,
1464 .enable_mask = BIT(0),
1478 .halt_reg = 0x3a008,
1481 .enable_reg = 0x3a008,
1482 .enable_mask = BIT(0),
1496 .halt_reg = 0x8018,
1499 .enable_reg = 0x8018,
1500 .enable_mask = BIT(0),
1514 .halt_reg = 0x9018,
1517 .enable_reg = 0x9018,
1518 .enable_mask = BIT(0),
1532 .halt_reg = 0x27018,
1535 .enable_reg = 0x27018,
1536 .enable_mask = BIT(0),
1550 .halt_reg = 0x27014,
1553 .enable_reg = 0x27014,
1554 .enable_mask = BIT(0),
1568 .halt_reg = 0x12004,
1571 .enable_reg = 0x12004,
1572 .enable_mask = BIT(0),
1586 .halt_reg = 0x1200c,
1589 .enable_reg = 0x1200c,
1590 .enable_mask = BIT(0),
1604 .halt_reg = 0x17018,
1607 .enable_reg = 0x17018,
1608 .enable_mask = BIT(0),
1622 .halt_reg = 0x17034,
1625 .enable_reg = 0x17034,
1626 .enable_mask = BIT(0),
1640 .halt_reg = 0x1702c,
1643 .enable_reg = 0x1702c,
1644 .enable_mask = BIT(0),
1658 .halt_reg = 0x17014,
1661 .enable_reg = 0x17014,
1662 .enable_mask = BIT(0),
1676 .halt_reg = 0x17030,
1679 .enable_reg = 0x17030,
1680 .enable_mask = BIT(0),
1694 .halt_reg = 0x1701c,
1697 .enable_reg = 0x1701c,
1698 .enable_mask = BIT(0),
1712 .halt_reg = 0x1707c,
1715 .enable_reg = 0x1707c,
1716 .enable_mask = BIT(0),
1730 .halt_reg = 0x17028,
1733 .enable_reg = 0x17028,
1734 .enable_mask = BIT(0),
1748 .halt_reg = 0x17020,
1751 .enable_reg = 0x17020,
1752 .enable_mask = BIT(0),
1766 .halt_reg = 0x17074,
1769 .enable_reg = 0x17074,
1770 .enable_mask = BIT(0),
1784 .halt_reg = 0x29030,
1787 .enable_reg = 0x29030,
1788 .enable_mask = BIT(0),
1802 .halt_reg = 0x29070,
1805 .enable_reg = 0x29070,
1806 .enable_mask = BIT(0),
1820 .halt_reg = 0x29038,
1823 .enable_reg = 0x29038,
1824 .enable_mask = BIT(0),
1838 .halt_reg = 0x29048,
1841 .enable_reg = 0x29048,
1842 .enable_mask = BIT(0),
1856 .halt_reg = 0x29040,
1859 .enable_reg = 0x29040,
1860 .enable_mask = BIT(0),
1874 .halt_reg = 0x29068,
1877 .enable_reg = 0x29068,
1878 .enable_mask = BIT(0),
1892 .halt_reg = 0x2a00c,
1895 .enable_reg = 0x2a00c,
1896 .enable_mask = BIT(0),
1910 .halt_reg = 0x2a070,
1913 .enable_reg = 0x2a070,
1914 .enable_mask = BIT(0),
1928 .halt_reg = 0x2a014,
1931 .enable_reg = 0x2a014,
1932 .enable_mask = BIT(0),
1946 .halt_reg = 0x2a024,
1949 .enable_reg = 0x2a024,
1950 .enable_mask = BIT(0),
1964 .halt_reg = 0x2a01c,
1967 .enable_reg = 0x2a01c,
1968 .enable_mask = BIT(0),
1982 .halt_reg = 0x2a068,
1985 .enable_reg = 0x2a068,
1986 .enable_mask = BIT(0),
2000 .halt_reg = 0x29078,
2003 .enable_reg = 0x29078,
2004 .enable_mask = BIT(0),
2018 .halt_reg = 0x28030,
2021 .enable_reg = 0x28030,
2022 .enable_mask = BIT(0),
2036 .halt_reg = 0x28070,
2039 .enable_reg = 0x28070,
2040 .enable_mask = BIT(0),
2054 .halt_reg = 0x28038,
2057 .enable_reg = 0x28038,
2058 .enable_mask = BIT(0),
2072 .halt_reg = 0x28048,
2075 .enable_reg = 0x28048,
2076 .enable_mask = BIT(0),
2090 .halt_reg = 0x28040,
2093 .enable_reg = 0x28040,
2094 .enable_mask = BIT(0),
2108 .halt_reg = 0x28080,
2111 .enable_reg = 0x28080,
2112 .enable_mask = BIT(0),
2126 .halt_reg = 0x28068,
2129 .enable_reg = 0x28068,
2130 .enable_mask = BIT(0),
2144 .halt_reg = 0x31024,
2147 .enable_reg = 0x31024,
2148 .enable_mask = BIT(0),
2162 .halt_reg = 0x31020,
2165 .enable_reg = 0x31020,
2166 .enable_mask = BIT(0),
2180 .halt_reg = 0x13024,
2183 .enable_reg = 0xb004,
2198 .halt_reg = 0x25014,
2201 .enable_reg = 0x25014,
2202 .enable_mask = BIT(0),
2216 .halt_reg = 0x25018,
2219 .enable_reg = 0x25018,
2220 .enable_mask = BIT(0),
2234 .halt_reg = 0x2500c,
2237 .enable_reg = 0x2500c,
2238 .enable_mask = BIT(0),
2252 .halt_reg = 0x25010,
2255 .enable_reg = 0x25010,
2256 .enable_mask = BIT(0),
2270 .halt_reg = 0x25020,
2273 .enable_reg = 0x25020,
2274 .enable_mask = BIT(0),
2288 .halt_reg = 0x2501c,
2291 .enable_reg = 0x2501c,
2292 .enable_mask = BIT(0),
2306 .halt_reg = 0x25024,
2309 .enable_reg = 0x25024,
2310 .enable_mask = BIT(0),
2324 .halt_reg = 0x250a0,
2327 .enable_reg = 0x250a0,
2328 .enable_mask = BIT(0),
2342 .halt_reg = 0x2d038,
2345 .enable_reg = 0x2d038,
2346 .enable_mask = BIT(0),
2360 .halt_reg = 0x2d06c,
2363 .enable_reg = 0x2d06c,
2364 .enable_mask = BIT(0),
2378 .halt_reg = 0x2d068,
2381 .enable_reg = 0x2d068,
2382 .enable_mask = BIT(0),
2396 .halt_reg = 0x2d05c,
2399 .enable_reg = 0xb004,
2414 .halt_reg = 0x2d064,
2417 .enable_reg = 0x2d064,
2418 .enable_mask = BIT(0),
2445 .halt_reg = 0x2d070,
2448 .enable_reg = 0x2d070,
2449 .enable_mask = BIT(0),
2463 .halt_reg = 0x32010,
2466 .enable_reg = 0x32010,
2467 .enable_mask = BIT(0),
2481 .halt_reg = 0x32014,
2484 .enable_reg = 0x32014,
2485 .enable_mask = BIT(0),
2499 .halt_reg = 0x3200c,
2502 .enable_reg = 0x3200c,
2503 .enable_mask = BIT(0),
2517 .halt_reg = 0x3201c,
2520 .enable_reg = 0x3201c,
2521 .enable_mask = BIT(0),
2535 .halt_reg = 0x33034,
2538 .enable_reg = 0x33034,
2539 .enable_mask = BIT(0),
2553 .halt_reg = 0x3302c,
2556 .enable_reg = 0x3302c,
2557 .enable_mask = BIT(0),
2571 .halt_reg = 0x2e028,
2574 .enable_reg = 0x2e028,
2575 .enable_mask = BIT(0),
2589 .halt_reg = 0x17090,
2592 .enable_reg = 0x17090,
2593 .enable_mask = BIT(0),
2607 .halt_reg = 0x17084,
2610 .enable_reg = 0x17084,
2611 .enable_mask = BIT(0),
2625 .halt_reg = 0x2e050,
2628 .enable_reg = 0x2e050,
2629 .enable_mask = BIT(0),
2643 .halt_reg = 0x2e0ac,
2646 .enable_reg = 0x2e0ac,
2647 .enable_mask = BIT(0),
2661 .halt_reg = 0x2e080,
2664 .enable_reg = 0x2e080,
2665 .enable_mask = BIT(0),
2679 .halt_reg = 0x2e04c,
2682 .enable_reg = 0x2e04c,
2683 .enable_mask = BIT(0),
2697 .halt_reg = 0x2e07c,
2700 .enable_reg = 0x2e07c,
2701 .enable_mask = BIT(0),
2715 .halt_reg = 0x2e048,
2718 .enable_reg = 0x2e048,
2719 .enable_mask = BIT(0),
2733 .halt_reg = 0x2e058,
2736 .enable_reg = 0x2e058,
2737 .enable_mask = BIT(0),
2751 .halt_reg = 0x2e038,
2754 .enable_reg = 0x2e038,
2755 .enable_mask = BIT(0),
2769 .halt_reg = 0x2e030,
2772 .enable_reg = 0x2e030,
2773 .enable_mask = BIT(0),
2787 .halt_reg = 0x16010,
2790 .enable_reg = 0x16010,
2791 .enable_mask = BIT(0),
2805 .halt_reg = 0x1600c,
2808 .enable_reg = 0x1600c,
2809 .enable_mask = BIT(0),
2823 .halt_reg = 0x1601c,
2826 .enable_reg = 0x1601c,
2827 .enable_mask = BIT(0),
2841 .halt_reg = 0x16018,
2844 .enable_reg = 0x16018,
2845 .enable_mask = BIT(0),
2859 .halt_reg = 0x2c050,
2862 .enable_reg = 0x2c050,
2863 .enable_mask = BIT(0),
2877 .halt_reg = 0x30004,
2880 .enable_reg = 0x30004,
2881 .enable_mask = BIT(0),
2895 .halt_reg = 0x2c090,
2898 .enable_reg = 0x2c090,
2899 .enable_mask = BIT(0),
2913 .halt_reg = 0x2c048,
2916 .enable_reg = 0x2c048,
2917 .enable_mask = BIT(0),
2931 .halt_reg = 0x2c054,
2933 .enable_reg = 0x2c054,
2934 .enable_mask = BIT(0),
2948 .halt_reg = 0x2c05c,
2951 .enable_reg = 0x2c05c,
2952 .enable_mask = BIT(0),
2966 .halt_reg = 0x2c078,
2969 .enable_reg = 0x2c078,
2970 .enable_mask = BIT(0),
2984 .halt_reg = 0x2c058,
2987 .enable_reg = 0x2c058,
2988 .enable_mask = BIT(0),
3002 .halt_reg = 0x2505c,
3005 .enable_reg = 0x2505c,
3006 .enable_mask = BIT(0),
3020 .halt_reg = 0x25060,
3023 .enable_reg = 0x25060,
3024 .enable_mask = BIT(0),
3038 .halt_reg = 0x25048,
3041 .enable_reg = 0x25048,
3042 .enable_mask = BIT(0),
3056 .halt_reg = 0x25038,
3059 .enable_reg = 0x25038,
3060 .enable_mask = BIT(0),
3074 .halt_reg = 0x2504c,
3077 .enable_reg = 0x2504c,
3078 .enable_mask = BIT(0),
3092 .halt_reg = 0x2503c,
3095 .enable_reg = 0x2503c,
3096 .enable_mask = BIT(0),
3110 .halt_reg = 0x25050,
3113 .enable_reg = 0x25050,
3114 .enable_mask = BIT(0),
3128 .halt_reg = 0x25040,
3131 .enable_reg = 0x25040,
3132 .enable_mask = BIT(0),
3146 .halt_reg = 0x25058,
3149 .enable_reg = 0x25058,
3150 .enable_mask = BIT(0),
3164 .halt_reg = 0x2e0b0,
3167 .enable_reg = 0x2e0b0,
3168 .enable_mask = BIT(0),
3182 .halt_reg = 0x2e0b4,
3185 .enable_reg = 0x2e0b4,
3186 .enable_mask = BIT(0),
3200 .halt_reg = 0x34018,
3203 .enable_reg = 0x34018,
3204 .enable_mask = BIT(0),
3218 .halt_reg = 0x3401c,
3221 .enable_reg = 0x3401c,
3222 .enable_mask = BIT(0),
3236 .halt_reg = 0x34020,
3239 .enable_reg = 0x34020,
3240 .enable_mask = BIT(0),
3254 .halt_reg = 0x17080,
3257 .enable_reg = 0x17080,
3258 .enable_mask = BIT(0),
3272 .reg = 0x2e010,
3273 .shift = 0,
3457 [GCC_ADSS_BCR] = { 0x1c000 },
3458 [GCC_ADSS_PWM_CLK_ARES] = { 0x1c00c, 2 },
3459 [GCC_AHB_CLK_ARES] = { 0x34024, 2 },
3460 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000 },
3461 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES] = { 0x3800c, 2 },
3462 [GCC_APSS_AHB_CLK_ARES] = { 0x24018, 2 },
3463 [GCC_APSS_AXI_CLK_ARES] = { 0x2401c, 2 },
3464 [GCC_BLSP1_AHB_CLK_ARES] = { 0x1008, 2 },
3465 [GCC_BLSP1_BCR] = { 0x1000 },
3466 [GCC_BLSP1_QUP1_BCR] = { 0x2000 },
3467 [GCC_BLSP1_QUP1_I2C_APPS_CLK_ARES] = { 0x2024, 2 },
3468 [GCC_BLSP1_QUP1_SPI_APPS_CLK_ARES] = { 0x2020, 2 },
3469 [GCC_BLSP1_QUP2_BCR] = { 0x3000 },
3470 [GCC_BLSP1_QUP2_I2C_APPS_CLK_ARES] = { 0x3024, 2 },
3471 [GCC_BLSP1_QUP2_SPI_APPS_CLK_ARES] = { 0x3020, 2 },
3472 [GCC_BLSP1_QUP3_BCR] = { 0x4000 },
3473 [GCC_BLSP1_QUP3_I2C_APPS_CLK_ARES] = { 0x4024, 2 },
3474 [GCC_BLSP1_QUP3_SPI_APPS_CLK_ARES] = { 0x4020, 2 },
3475 [GCC_BLSP1_SLEEP_CLK_ARES] = { 0x1010, 2 },
3476 [GCC_BLSP1_UART1_APPS_CLK_ARES] = { 0x2040, 2 },
3477 [GCC_BLSP1_UART1_BCR] = { 0x2028 },
3478 [GCC_BLSP1_UART2_APPS_CLK_ARES] = { 0x3040, 2 },
3479 [GCC_BLSP1_UART2_BCR] = { 0x3028 },
3480 [GCC_BLSP1_UART3_APPS_CLK_ARES] = { 0x4054, 2 },
3481 [GCC_BLSP1_UART3_BCR] = { 0x4028 },
3482 [GCC_CE_BCR] = { 0x18008 },
3483 [GCC_CMN_BLK_BCR] = { 0x3a000 },
3484 [GCC_CMN_LDO0_BCR] = { 0x1d000 },
3485 [GCC_CMN_LDO1_BCR] = { 0x1d008 },
3486 [GCC_DCC_BCR] = { 0x35000 },
3487 [GCC_GP1_CLK_ARES] = { 0x8018, 2 },
3488 [GCC_GP2_CLK_ARES] = { 0x9018, 2 },
3489 [GCC_LPASS_BCR] = { 0x27000 },
3490 [GCC_LPASS_CORE_AXIM_CLK_ARES] = { 0x27018, 2 },
3491 [GCC_LPASS_SWAY_CLK_ARES] = { 0x27014, 2 },
3492 [GCC_MDIOM_BCR] = { 0x12000 },
3493 [GCC_MDIOS_BCR] = { 0x12008 },
3494 [GCC_NSS_BCR] = { 0x17000 },
3495 [GCC_NSS_TS_CLK_ARES] = { 0x17018, 2 },
3496 [GCC_NSSCC_CLK_ARES] = { 0x17034, 2 },
3497 [GCC_NSSCFG_CLK_ARES] = { 0x1702c, 2 },
3498 [GCC_NSSNOC_ATB_CLK_ARES] = { 0x17014, 2 },
3499 [GCC_NSSNOC_NSSCC_CLK_ARES] = { 0x17030, 2 },
3500 [GCC_NSSNOC_QOSGEN_REF_CLK_ARES] = { 0x1701c, 2 },
3501 [GCC_NSSNOC_SNOC_1_CLK_ARES] = { 0x1707c, 2 },
3502 [GCC_NSSNOC_SNOC_CLK_ARES] = { 0x17028, 2 },
3503 [GCC_NSSNOC_TIMEOUT_REF_CLK_ARES] = { 0x17020, 2 },
3504 [GCC_NSSNOC_XO_DCD_CLK_ARES] = { 0x17074, 2 },
3505 [GCC_PCIE3X1_0_AHB_CLK_ARES] = { 0x29030, 2 },
3506 [GCC_PCIE3X1_0_AUX_CLK_ARES] = { 0x29070, 2 },
3507 [GCC_PCIE3X1_0_AXI_M_CLK_ARES] = { 0x29038, 2 },
3508 [GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK_ARES] = { 0x29048, 2 },
3509 [GCC_PCIE3X1_0_AXI_S_CLK_ARES] = { 0x29040, 2 },
3510 [GCC_PCIE3X1_0_BCR] = { 0x29000 },
3511 [GCC_PCIE3X1_0_LINK_DOWN_BCR] = { 0x29054 },
3512 [GCC_PCIE3X1_0_PHY_BCR] = { 0x29060 },
3513 [GCC_PCIE3X1_0_PHY_PHY_BCR] = { 0x2905c },
3514 [GCC_PCIE3X1_1_AHB_CLK_ARES] = { 0x2a00c, 2 },
3515 [GCC_PCIE3X1_1_AUX_CLK_ARES] = { 0x2a070, 2 },
3516 [GCC_PCIE3X1_1_AXI_M_CLK_ARES] = { 0x2a014, 2 },
3517 [GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK_ARES] = { 0x2a024, 2 },
3518 [GCC_PCIE3X1_1_AXI_S_CLK_ARES] = { 0x2a01c, 2 },
3519 [GCC_PCIE3X1_1_BCR] = { 0x2a000 },
3520 [GCC_PCIE3X1_1_LINK_DOWN_BCR] = { 0x2a028 },
3521 [GCC_PCIE3X1_1_PHY_BCR] = { 0x2a030 },
3522 [GCC_PCIE3X1_1_PHY_PHY_BCR] = { 0x2a02c },
3523 [GCC_PCIE3X1_PHY_AHB_CLK_ARES] = { 0x29078, 2 },
3524 [GCC_PCIE3X2_AHB_CLK_ARES] = { 0x28030, 2 },
3525 [GCC_PCIE3X2_AUX_CLK_ARES] = { 0x28070, 2 },
3526 [GCC_PCIE3X2_AXI_M_CLK_ARES] = { 0x28038, 2 },
3527 [GCC_PCIE3X2_AXI_S_BRIDGE_CLK_ARES] = { 0x28048, 2 },
3528 [GCC_PCIE3X2_AXI_S_CLK_ARES] = { 0x28040, 2 },
3529 [GCC_PCIE3X2_BCR] = { 0x28000 },
3530 [GCC_PCIE3X2_LINK_DOWN_BCR] = { 0x28054 },
3531 [GCC_PCIE3X2_PHY_AHB_CLK_ARES] = { 0x28080, 2 },
3532 [GCC_PCIE3X2_PHY_BCR] = { 0x28060 },
3533 [GCC_PCIE3X2PHY_PHY_BCR] = { 0x2805c },
3534 [GCC_PCNOC_BCR] = { 0x31000 },
3535 [GCC_PCNOC_LPASS_CLK_ARES] = { 0x31020, 2 },
3536 [GCC_PRNG_AHB_CLK_ARES] = { 0x13024, 2 },
3537 [GCC_PRNG_BCR] = { 0x13020 },
3538 [GCC_Q6_AHB_CLK_ARES] = { 0x25014, 2 },
3539 [GCC_Q6_AHB_S_CLK_ARES] = { 0x25018, 2 },
3540 [GCC_Q6_AXIM_CLK_ARES] = { 0x2500c, 2 },
3541 [GCC_Q6_AXIS_CLK_ARES] = { 0x25010, 2 },
3542 [GCC_Q6_TSCTR_1TO2_CLK_ARES] = { 0x25020, 2 },
3543 [GCC_Q6SS_ATBM_CLK_ARES] = { 0x2501c, 2 },
3544 [GCC_Q6SS_PCLKDBG_CLK_ARES] = { 0x25024, 2 },
3545 [GCC_Q6SS_TRIG_CLK_ARES] = { 0x250a0, 2 },
3546 [GCC_QDSS_APB2JTAG_CLK_ARES] = { 0x2d060, 2 },
3547 [GCC_QDSS_AT_CLK_ARES] = { 0x2d038, 2 },
3548 [GCC_QDSS_BCR] = { 0x2d000 },
3549 [GCC_QDSS_CFG_AHB_CLK_ARES] = { 0x2d06c, 2 },
3550 [GCC_QDSS_DAP_AHB_CLK_ARES] = { 0x2d068, 2 },
3551 [GCC_QDSS_DAP_CLK_ARES] = { 0x2d05c, 2 },
3552 [GCC_QDSS_ETR_USB_CLK_ARES] = { 0x2d064, 2 },
3553 [GCC_QDSS_EUD_AT_CLK_ARES] = { 0x2d070, 2 },
3554 [GCC_QDSS_STM_CLK_ARES] = { 0x2d040, 2 },
3555 [GCC_QDSS_TRACECLKIN_CLK_ARES] = { 0x2d044, 2 },
3556 [GCC_QDSS_TS_CLK_ARES] = { 0x2d078, 2 },
3557 [GCC_QDSS_TSCTR_DIV16_CLK_ARES] = { 0x2d058, 2 },
3558 [GCC_QDSS_TSCTR_DIV2_CLK_ARES] = { 0x2d048, 2 },
3559 [GCC_QDSS_TSCTR_DIV3_CLK_ARES] = { 0x2d04c, 2 },
3560 [GCC_QDSS_TSCTR_DIV4_CLK_ARES] = { 0x2d050, 2 },
3561 [GCC_QDSS_TSCTR_DIV8_CLK_ARES] = { 0x2d054, 2 },
3562 [GCC_QPIC_AHB_CLK_ARES] = { 0x32010, 2 },
3563 [GCC_QPIC_CLK_ARES] = { 0x32014, 2 },
3564 [GCC_QPIC_BCR] = { 0x32000 },
3565 [GCC_QPIC_IO_MACRO_CLK_ARES] = { 0x3200c, 2 },
3566 [GCC_QPIC_SLEEP_CLK_ARES] = { 0x3201c, 2 },
3567 [GCC_QUSB2_0_PHY_BCR] = { 0x2c068 },
3568 [GCC_SDCC1_AHB_CLK_ARES] = { 0x33034, 2 },
3569 [GCC_SDCC1_APPS_CLK_ARES] = { 0x3302c, 2 },
3570 [GCC_SDCC_BCR] = { 0x33000 },
3571 [GCC_SNOC_BCR] = { 0x2e000 },
3572 [GCC_SNOC_LPASS_CFG_CLK_ARES] = { 0x2e028, 2 },
3573 [GCC_SNOC_NSSNOC_1_CLK_ARES] = { 0x17090, 2 },
3574 [GCC_SNOC_NSSNOC_CLK_ARES] = { 0x17084, 2 },
3575 [GCC_SYS_NOC_QDSS_STM_AXI_CLK_ARES] = { 0x2e034, 2 },
3576 [GCC_SYS_NOC_WCSS_AHB_CLK_ARES] = { 0x2e030, 2 },
3577 [GCC_UNIPHY0_AHB_CLK_ARES] = { 0x16010, 2 },
3578 [GCC_UNIPHY0_BCR] = { 0x16000 },
3579 [GCC_UNIPHY0_SYS_CLK_ARES] = { 0x1600c, 2 },
3580 [GCC_UNIPHY1_AHB_CLK_ARES] = { 0x1601c, 2 },
3581 [GCC_UNIPHY1_BCR] = { 0x16014 },
3582 [GCC_UNIPHY1_SYS_CLK_ARES] = { 0x16018, 2 },
3583 [GCC_USB0_AUX_CLK_ARES] = { 0x2c050, 2 },
3584 [GCC_USB0_EUD_AT_CLK_ARES] = { 0x30004, 2 },
3585 [GCC_USB0_LFPS_CLK_ARES] = { 0x2c090, 2 },
3586 [GCC_USB0_MASTER_CLK_ARES] = { 0x2c048, 2 },
3587 [GCC_USB0_MOCK_UTMI_CLK_ARES] = { 0x2c054, 2 },
3588 [GCC_USB0_PHY_BCR] = { 0x2c06c },
3589 [GCC_USB0_PHY_CFG_AHB_CLK_ARES] = { 0x2c05c, 2 },
3590 [GCC_USB0_SLEEP_CLK_ARES] = { 0x2c058, 2 },
3591 [GCC_USB3PHY_0_PHY_BCR] = { 0x2c070 },
3592 [GCC_USB_BCR] = { 0x2c000 },
3593 [GCC_WCSS_AXIM_CLK_ARES] = { 0x2505c, 2 },
3594 [GCC_WCSS_AXIS_CLK_ARES] = { 0x25060, 2 },
3595 [GCC_WCSS_BCR] = { 0x18004 },
3596 [GCC_WCSS_DBG_IFC_APB_BDG_CLK_ARES] = { 0x25048, 2 },
3597 [GCC_WCSS_DBG_IFC_APB_CLK_ARES] = { 0x25038, 2 },
3598 [GCC_WCSS_DBG_IFC_ATB_BDG_CLK_ARES] = { 0x2504c, 2 },
3599 [GCC_WCSS_DBG_IFC_ATB_CLK_ARES] = { 0x2503c, 2 },
3600 [GCC_WCSS_DBG_IFC_NTS_BDG_CLK_ARES] = { 0x25050, 2 },
3601 [GCC_WCSS_DBG_IFC_NTS_CLK_ARES] = { 0x25040, 2 },
3602 [GCC_WCSS_ECAHB_CLK_ARES] = { 0x25058, 2 },
3603 [GCC_WCSS_MST_ASYNC_BDG_CLK_ARES] = { 0x2e0b0, 2 },
3604 [GCC_WCSS_Q6_BCR] = { 0x18000 },
3605 [GCC_WCSS_SLV_ASYNC_BDG_CLK_ARES] = { 0x2e0b4, 2 },
3606 [GCC_XO_CLK_ARES] = { 0x34018, 2 },
3607 [GCC_XO_DIV4_CLK_ARES] = { 0x3401c, 2 },
3608 [GCC_Q6SS_DBG_ARES] = { 0x25094 },
3609 [GCC_WCSS_DBG_BDG_ARES] = { 0x25098, 0 },
3610 [GCC_WCSS_DBG_ARES] = { 0x25098, 1 },
3611 [GCC_WCSS_AXI_S_ARES] = { 0x25098, 2 },
3612 [GCC_WCSS_AXI_M_ARES] = { 0x25098, 3 },
3613 [GCC_WCSSAON_ARES] = { 0x2509C },
3614 [GCC_PCIE3X2_PIPE_ARES] = { 0x28058, 0 },
3615 [GCC_PCIE3X2_CORE_STICKY_ARES] = { 0x28058, 1 },
3616 [GCC_PCIE3X2_AXI_S_STICKY_ARES] = { 0x28058, 2 },
3617 [GCC_PCIE3X2_AXI_M_STICKY_ARES] = { 0x28058, 3 },
3618 [GCC_PCIE3X1_0_PIPE_ARES] = { 0x29058, 0 },
3619 [GCC_PCIE3X1_0_CORE_STICKY_ARES] = { 0x29058, 1 },
3620 [GCC_PCIE3X1_0_AXI_S_STICKY_ARES] = { 0x29058, 2 },
3621 [GCC_PCIE3X1_0_AXI_M_STICKY_ARES] = { 0x29058, 3 },
3622 [GCC_PCIE3X1_1_PIPE_ARES] = { 0x2a058, 0 },
3623 [GCC_PCIE3X1_1_CORE_STICKY_ARES] = { 0x2a058, 1 },
3624 [GCC_PCIE3X1_1_AXI_S_STICKY_ARES] = { 0x2a058, 2 },
3625 [GCC_PCIE3X1_1_AXI_M_STICKY_ARES] = { 0x2a058, 3 },
3626 [GCC_IM_SLEEP_CLK_ARES] = { 0x34020, 2 },
3627 [GCC_NSSNOC_PCNOC_1_CLK_ARES] = { 0x17080, 2 },
3628 [GCC_UNIPHY0_XPCS_ARES] = { 0x16050 },
3629 [GCC_UNIPHY1_XPCS_ARES] = { 0x16060 },
3636 .max_register = 0x3f024,