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/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-usb2-mph-0.dtsi2 * QorIQ USB Host device tree stub [ controller @ offset 0x210000 ]
37 reg = <0x210000 0x1000>;
39 #size-cells = <0>;
40 interrupts = <44 0x2 0 0>;
H A Dqonverge-usb2-dr-0.dtsi2 * QorIQ Qonverge USB Host device tree stub [ controller @ offset 0x210000 ]
37 reg = <0x210000 0x1000>;
39 #size-cells = <0>;
40 interrupts = <44 0x2 0 0>;
/openbmc/linux/drivers/rtc/
H A Drtc-gamecube.c12 * This device sits on a bus named EXI (which is similar to SPI), channel 0,
40 #define EXICSR 0
45 #define EXICSR_DEV 0x380
46 #define EXICSR_DEV1 0x100
47 #define EXICSR_CLK 0x070
48 #define EXICSR_CLK_1MHZ 0x000
49 #define EXICSR_CLK_2MHZ 0x010
50 #define EXICSR_CLK_4MHZ 0x020
51 #define EXICSR_CLK_8MHZ 0x030
52 #define EXICSR_CLK_16MHZ 0x040
[all …]
/openbmc/u-boot/include/net/pfe_eth/pfe/
H A Dcbus.h22 #define EMAC1_BASE_ADDR (CBUS_BASE_ADDR + 0x200000)
23 #define EGPI1_BASE_ADDR (CBUS_BASE_ADDR + 0x210000)
24 #define EMAC2_BASE_ADDR (CBUS_BASE_ADDR + 0x220000)
25 #define EGPI2_BASE_ADDR (CBUS_BASE_ADDR + 0x230000)
26 #define BMU1_BASE_ADDR (CBUS_BASE_ADDR + 0x240000)
27 #define BMU2_BASE_ADDR (CBUS_BASE_ADDR + 0x250000)
28 #define ARB_BASE_ADDR (CBUS_BASE_ADDR + 0x260000)
29 #define DDR_CONFIG_BASE_ADDR (CBUS_BASE_ADDR + 0x270000)
30 #define HIF_BASE_ADDR (CBUS_BASE_ADDR + 0x280000)
31 #define HGPI_BASE_ADDR (CBUS_BASE_ADDR + 0x290000)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dnvidia,tegra186-gpc-dma.yaml78 reg = <0x2600000 0x210000>;
115 dma-channel-mask = <0xfffffffe>;
/openbmc/linux/arch/arm64/boot/dts/marvell/
H A Darmada-3720-db.dts27 memory@0 {
29 reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
55 gpios-states = <0>;
56 states = <1800000 0x1
57 3300000 0x0>;
72 /* Gigabit module on CON19(V2.0)/CON21(V1.4) */
75 pinctrl-0 = <&rgmii_pins>;
81 /* Gigabit module on CON18(V2.0)/CON20(V1.4) */
90 pinctrl-0 = <&i2c1_pins>;
98 reg = <0x22>;
[all …]
H A Darmada-ap80x.dtsi41 reg = <0x0 0x4000000 0x0 0x200000>;
46 reg = <0 0x4400000 0 0x1000000>;
62 ranges = <0x0 0x0 0xf0000000 0x1000000>;
66 reg = <0x100000 0x100000>;
90 reg = <0x210000 0x10000>,
91 <0x220000 0x20000>,
92 <0x240000 0x20000>,
93 <0x260000 0x20000>;
98 reg = <0x280000 0x1000>;
105 reg = <0x290000 0x1000>;
[all …]
/openbmc/qemu/include/hw/arm/
H A Draspi_platform.h67 #define MSYNC_OFFSET 0x0000 /* Multicore Sync Block */
68 #define CCPT_OFFSET 0x1000 /* Compact Camera Port 2 TX */
69 #define INTE_OFFSET 0x2000 /* VC Interrupt controller */
70 #define ST_OFFSET 0x3000 /* System Timer */
71 #define TXP_OFFSET 0x4000 /* Transposer */
72 #define JPEG_OFFSET 0x5000
73 #define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */
74 #define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */
75 #define ARBA_OFFSET 0x9000
76 #define BRDG_OFFSET 0xa000 /* RPiVid ASB for BCM2838 (BCM2711) */
[all …]
/openbmc/linux/drivers/net/ethernet/cavium/thunder/
H A Dnic_reg.h13 #define NIC_PF_CFG (0x0000)
14 #define NIC_PF_STATUS (0x0010)
15 #define NIC_PF_INTR_TIMER_CFG (0x0030)
16 #define NIC_PF_BIST_STATUS (0x0040)
17 #define NIC_PF_SOFT_RESET (0x0050)
18 #define NIC_PF_TCP_TIMER (0x0060)
19 #define NIC_PF_BP_CFG (0x0080)
20 #define NIC_PF_RRM_CFG (0x0088)
21 #define NIC_PF_CQM_CFG (0x00A0)
22 #define NIC_PF_CNM_CF (0x00A8)
[all …]
/openbmc/u-boot/arch/mips/dts/
H A Dmscc,luton.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
30 #clock-cells = <0>;
35 #clock-cells = <0>;
43 ranges = <0 0x60000000 0x10200000>;
46 pinctrl-0 = <&uart_pins>;
50 reg = <0x10100000 0x20>;
60 reg = <0x70068 0x68>;
63 gpio-ranges = <&gpio 0 0 32>;
[all …]
/openbmc/u-boot/include/configs/
H A Dpm9261.h56 #define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
58 #define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
60 /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
68 #define CONFIG_SYS_SDRC_TR_VAL1 0x13C
86 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
88 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
89 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
90 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
91 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
92 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a-kontron-sl28.dts85 reg = <0x5>;
95 nvmem-cells = <&base_mac_address 0>;
118 flash@0 {
122 reg = <0>;
132 partition@0 {
133 reg = <0x000000 0x010000>;
139 reg = <0x010000 0x1d0000>;
145 reg = <0x200000 0x010000>;
150 reg = <0x210000 0x1d0000>;
155 reg = <0x3e0000 0x020000>;
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dconfig.h13 #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
20 #define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
25 #define CONFIG_SYS_PAGE_SIZE 0x10000
31 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
32 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
33 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
48 #define GICD_BASE 0x06000000
49 #define GICR_BASE 0x06100000
52 #define SMMU_BASE 0x05000000 /* GR0 Base */
69 #define CCI_MN_BASE 0x04000000
[all …]
/openbmc/linux/arch/arm64/boot/dts/arm/
H A Drtsm_ve-motherboard.dtsi13 #clock-cells = <0>;
20 #clock-cells = <0>;
27 #clock-cells = <0>;
49 #clock-cells = <0>;
55 arm,vexpress-sysreg,func = <5 0>;
60 arm,vexpress-sysreg,func = <7 0>;
65 arm,vexpress-sysreg,func = <8 0>;
70 arm,vexpress-sysreg,func = <9 0>;
75 arm,vexpress-sysreg,func = <11 0>;
83 ranges = <0 0x8000000 0 0x8000000 0x18000000>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Darmada-ap806.dtsi73 reg = <0x0 0x4000000 0x0 0x200000>;
89 ranges = <0x0 0x0 0xf0000000 0x1000000>;
99 reg = <0x210000 0x10000>,
100 <0x220000 0x20000>,
101 <0x240000 0x20000>,
102 <0x260000 0x20000>;
107 reg = <0x280000 0x1000>;
114 reg = <0x290000 0x1000>;
121 reg = <0x2a0000 0x1000>;
128 reg = <0x2b0000 0x1000>;
[all …]
H A Dam33xx.dtsi46 #size-cells = <0>;
47 cpu@0 {
50 reg = <0>;
73 opp-supported-hw = <0x06 0x0010>;
80 opp-supported-hw = <0x01 0x00FF>;
87 opp-supported-hw = <0x06 0x0020>;
94 opp-supported-hw = <0x01 0xFFFF>;
100 opp-supported-hw = <0x06 0x0040>;
106 opp-supported-hw = <0x01 0xFFFF>;
112 opp-supported-hw = <0x06 0x0080>;
[all …]
H A Dam4372.dtsi33 #size-cells = <0>;
34 cpu: cpu@0 {
37 reg = <0>;
50 reg = <0x48241000 0x1000>,
51 <0x48240100 0x0100>;
59 reg = <0x48281000 0x1000>;
65 reg = <0x48242000 0x1000>;
76 reg = <0x44000000 0x400000
77 0x44800000 0x400000>;
85 ranges = <0 0x44c00000 0x287000>;
[all …]
/openbmc/linux/arch/mips/include/asm/sn/sn0/
H A Dhubmd.h29 #define MD_BASE 0x200000
30 #define MD_BASE_PERF 0x210000
31 #define MD_BASE_JUNK 0x220000
33 #define MD_IO_PROTECT 0x200000 /* MD and core register protection */
34 #define MD_IO_PROT_OVRRD 0x200008 /* Clear my bit in MD_IO_PROTECT */
35 #define MD_HSPEC_PROTECT 0x200010 /* BDDIR, LBOOT, RBOOT protection */
36 #define MD_MEMORY_CONFIG 0x200018 /* Memory/Directory DIMM control */
37 #define MD_REFRESH_CONTROL 0x200020 /* Memory/Directory refresh ctrl */
38 #define MD_FANDOP_CAC_STAT 0x200028 /* Fetch-and-op cache status */
39 #define MD_MIG_DIFF_THRESH 0x200030 /* Page migr. count diff thresh. */
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dsama5d2.dtsi29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
41 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
46 reg = <0x740000 0x1000>;
62 reg = <0x73c000 0x1000>;
78 reg = <0x20000000 0x20000000>;
84 #clock-cells = <0>;
85 clock-frequency = <0>;
90 #clock-cells = <0>;
[all …]
/openbmc/u-boot/drivers/video/meson/
H A Dmeson_vpu_init.c14 #define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
15 #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
16 #define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 offset in data sheet */
28 0x15561500, 0x14561600, 0x13561700, 0x12561800,
29 0x11551a00, 0x11541b00, 0x10541c00, 0x0f541d00,
30 0x0f531e00, 0x0e531f00, 0x0d522100, 0x0c522200,
31 0x0b522300, 0x0b512400, 0x0a502600, 0x0a4f2700,
32 0x094e2900, 0x084e2a00, 0x084d2b00, 0x074c2c01,
33 0x074b2d01, 0x064a2f01, 0x06493001, 0x05483201,
34 0x05473301, 0x05463401, 0x04453601, 0x04433702,
[all …]
/openbmc/linux/drivers/net/wireless/intel/ipw2x00/
H A Dipw2100.c176 static int debug = 0;
177 static int network_mode = 0;
178 static int channel = 0;
179 static int associate = 0;
180 static int disable = 0;
193 MODULE_PARM_DESC(mode, "network mode (0=BSS,1=IBSS,2=Monitor)");
196 MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
207 } while (0)
209 #define IPW_DEBUG(level, message...) do {} while (0)
335 IPW_DEBUG_IO("r: 0x%08X => 0x%08X\n", reg, *val); in read_register()
[all …]
/openbmc/linux/tools/testing/selftests/kvm/aarch64/
H A Dvgic_init.c23 #define GICR_TYPER 0x8
57 TEST_ASSERT(val == want, "%s; want '0x%x', got '0x%x'", msg, want, val); in v3_redist_reg_get()
63 GUEST_SYNC(0); in guest_code()
72 return __vcpu_run(vcpu) ? -errno : 0; in run_vcpu()
114 .size = 0x10000,
115 .alignment = 0x10000,
120 .size = NR_VCPUS * 0x20000,
121 .alignment = 0x10000,
126 .size = 0x1000,
127 .alignment = 0x1000,
[all …]
/openbmc/linux/drivers/phy/microchip/
H A Dsparx5_serdes.c31 #define SPX5_SERDES_QUIET_MODE_VAL 0x01ef4e0c
34 SPX5_SD10G28_CMU_MAIN = 0,
353 .cfg_en_adv = 0,
355 .cfg_en_dly = 0,
356 .cfg_tap_adv_3_0 = 0,
358 .cfg_tap_dly_4_0 = 0,
359 .cfg_eq_c_force_3_0 = 0xf,
368 .cfg_tap_adv_3_0 = 0,
370 .cfg_tap_dly_4_0 = 0x10,
371 .cfg_eq_c_force_3_0 = 0xf,
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dcik.c82 .max_level = 0,
143 return 0; in cik_query_video_codecs()
205 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); in cik_uvd_ctx_rreg()
216 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); in cik_uvd_ctx_wreg()
245 0xc200, 0xe0ffffff, 0xe0000000
250 0x31dc, 0xffffffff, 0x00000800,
251 0x31dd, 0xffffffff, 0x00000800,
252 0x31e6, 0xffffffff, 0x00007fbf,
253 0x31e7, 0xffffffff, 0x00007faf
258 0xcd5, 0x00000333, 0x00000333,
[all …]
/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra186.dtsi20 reg = <0x0 0x00100000 0x0 0xf000>,
21 <0x0 0x0010f000 0x0 0x1000>;
27 reg = <0x0 0x2200000 0x0 0x10000>,
28 <0x0 0x2210000 0x0 0x10000>;
44 reg = <0x0 0x02490000 0x0 0x10000>;
71 snps,burst-map = <0x7>;
78 reg = <0x0 0x2600000 0x0 0x210000>;
116 dma-channel-mask = <0xfffffffe>;
129 ranges = <0x02900000 0x0 0x02900000 0x200000>;
134 reg = <0x02900800 0x800>;
[all …]

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