1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2cf4c3448SCalvin Johnson /* 3cf4c3448SCalvin Johnson * Copyright 2015-2016 Freescale Semiconductor, Inc. 4cf4c3448SCalvin Johnson * Copyright 2017 NXP 5cf4c3448SCalvin Johnson */ 6cf4c3448SCalvin Johnson 7cf4c3448SCalvin Johnson #ifndef _CBUS_H_ 8cf4c3448SCalvin Johnson #define _CBUS_H_ 9cf4c3448SCalvin Johnson 10cf4c3448SCalvin Johnson #include "cbus/emac.h" 11cf4c3448SCalvin Johnson #include "cbus/gpi.h" 12cf4c3448SCalvin Johnson #include "cbus/bmu.h" 13cf4c3448SCalvin Johnson #include "cbus/hif.h" 14cf4c3448SCalvin Johnson #include "cbus/tmu_csr.h" 15cf4c3448SCalvin Johnson #include "cbus/class_csr.h" 16cf4c3448SCalvin Johnson #include "cbus/hif_nocpy.h" 17cf4c3448SCalvin Johnson #include "cbus/util_csr.h" 18cf4c3448SCalvin Johnson 19cf4c3448SCalvin Johnson #define CBUS_BASE_ADDR ((void *)CONFIG_SYS_FSL_PFE_ADDR) 20cf4c3448SCalvin Johnson 21cf4c3448SCalvin Johnson /* PFE Control and Status Register Desciption */ 22cf4c3448SCalvin Johnson #define EMAC1_BASE_ADDR (CBUS_BASE_ADDR + 0x200000) 23cf4c3448SCalvin Johnson #define EGPI1_BASE_ADDR (CBUS_BASE_ADDR + 0x210000) 24cf4c3448SCalvin Johnson #define EMAC2_BASE_ADDR (CBUS_BASE_ADDR + 0x220000) 25cf4c3448SCalvin Johnson #define EGPI2_BASE_ADDR (CBUS_BASE_ADDR + 0x230000) 26cf4c3448SCalvin Johnson #define BMU1_BASE_ADDR (CBUS_BASE_ADDR + 0x240000) 27cf4c3448SCalvin Johnson #define BMU2_BASE_ADDR (CBUS_BASE_ADDR + 0x250000) 28cf4c3448SCalvin Johnson #define ARB_BASE_ADDR (CBUS_BASE_ADDR + 0x260000) 29cf4c3448SCalvin Johnson #define DDR_CONFIG_BASE_ADDR (CBUS_BASE_ADDR + 0x270000) 30cf4c3448SCalvin Johnson #define HIF_BASE_ADDR (CBUS_BASE_ADDR + 0x280000) 31cf4c3448SCalvin Johnson #define HGPI_BASE_ADDR (CBUS_BASE_ADDR + 0x290000) 32cf4c3448SCalvin Johnson #define LMEM_BASE_ADDR (CBUS_BASE_ADDR + 0x300000) 33cf4c3448SCalvin Johnson #define LMEM_SIZE 0x10000 34cf4c3448SCalvin Johnson #define LMEM_END (LMEM_BASE_ADDR + LMEM_SIZE) 35cf4c3448SCalvin Johnson #define TMU_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x310000) 36cf4c3448SCalvin Johnson #define CLASS_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x320000) 37cf4c3448SCalvin Johnson #define HIF_NOCPY_BASE_ADDR (CBUS_BASE_ADDR + 0x350000) 38cf4c3448SCalvin Johnson #define UTIL_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x360000) 39cf4c3448SCalvin Johnson #define CBUS_GPT_BASE_ADDR (CBUS_BASE_ADDR + 0x370000) 40cf4c3448SCalvin Johnson 41cf4c3448SCalvin Johnson /* 42cf4c3448SCalvin Johnson * defgroup XXX_MEM_ACCESS_ADDR PE memory access through CSR 43cf4c3448SCalvin Johnson * XXX_MEM_ACCESS_ADDR register bit definitions. 44cf4c3448SCalvin Johnson */ 45cf4c3448SCalvin Johnson /* Internal Memory Write. */ 46cf4c3448SCalvin Johnson #define PE_MEM_ACCESS_WRITE BIT(31) 47cf4c3448SCalvin Johnson /* Internal Memory Read. */ 48cf4c3448SCalvin Johnson #define PE_MEM_ACCESS_READ (0 << 31) 49cf4c3448SCalvin Johnson 50cf4c3448SCalvin Johnson #define PE_MEM_ACCESS_IMEM BIT(15) 51cf4c3448SCalvin Johnson #define PE_MEM_ACCESS_DMEM BIT(16) 52cf4c3448SCalvin Johnson 53cf4c3448SCalvin Johnson /* Byte Enables of the Internal memory access. These are interpred in BE */ 54cf4c3448SCalvin Johnson #define PE_MEM_ACCESS_BYTE_ENABLE(offset, size) (((((1 << (size)) - 1) << (4 \ 55cf4c3448SCalvin Johnson - (offset) - (size)))\ 56cf4c3448SCalvin Johnson & 0xf) << 24) 57cf4c3448SCalvin Johnson 58cf4c3448SCalvin Johnson /* PFE cores states */ 59cf4c3448SCalvin Johnson #define CORE_DISABLE 0x00000000 60cf4c3448SCalvin Johnson #define CORE_ENABLE 0x00000001 61cf4c3448SCalvin Johnson #define CORE_SW_RESET 0x00000002 62cf4c3448SCalvin Johnson 63cf4c3448SCalvin Johnson /* LMEM defines */ 64cf4c3448SCalvin Johnson #define LMEM_HDR_SIZE 0x0010 65cf4c3448SCalvin Johnson #define LMEM_BUF_SIZE_LN2 0x7 66cf4c3448SCalvin Johnson #define LMEM_BUF_SIZE BIT(LMEM_BUF_SIZE_LN2) 67cf4c3448SCalvin Johnson 68cf4c3448SCalvin Johnson /* DDR defines */ 69cf4c3448SCalvin Johnson #define DDR_HDR_SIZE 0x0100 70cf4c3448SCalvin Johnson #define DDR_BUF_SIZE_LN2 0xb 71cf4c3448SCalvin Johnson #define DDR_BUF_SIZE BIT(DDR_BUF_SIZE_LN2) 72cf4c3448SCalvin Johnson 73cf4c3448SCalvin Johnson /* Clock generation through PLL */ 74cf4c3448SCalvin Johnson #define PLL_CLK_EN 1 75cf4c3448SCalvin Johnson 76cf4c3448SCalvin Johnson #endif /* _CBUS_H_ */ 77