Lines Matching +full:0 +full:x210000

22 #define EMAC1_BASE_ADDR		(CBUS_BASE_ADDR + 0x200000)
23 #define EGPI1_BASE_ADDR		(CBUS_BASE_ADDR + 0x210000)
24 #define EMAC2_BASE_ADDR		(CBUS_BASE_ADDR + 0x220000)
25 #define EGPI2_BASE_ADDR		(CBUS_BASE_ADDR + 0x230000)
26 #define BMU1_BASE_ADDR		(CBUS_BASE_ADDR + 0x240000)
27 #define BMU2_BASE_ADDR		(CBUS_BASE_ADDR + 0x250000)
28 #define ARB_BASE_ADDR		(CBUS_BASE_ADDR + 0x260000)
29 #define DDR_CONFIG_BASE_ADDR	(CBUS_BASE_ADDR + 0x270000)
30 #define HIF_BASE_ADDR		(CBUS_BASE_ADDR + 0x280000)
31 #define HGPI_BASE_ADDR		(CBUS_BASE_ADDR + 0x290000)
32 #define LMEM_BASE_ADDR		(CBUS_BASE_ADDR + 0x300000)
33 #define LMEM_SIZE		0x10000
35 #define TMU_CSR_BASE_ADDR	(CBUS_BASE_ADDR + 0x310000)
36 #define CLASS_CSR_BASE_ADDR	(CBUS_BASE_ADDR + 0x320000)
37 #define HIF_NOCPY_BASE_ADDR	(CBUS_BASE_ADDR + 0x350000)
38 #define UTIL_CSR_BASE_ADDR	(CBUS_BASE_ADDR + 0x360000)
39 #define CBUS_GPT_BASE_ADDR	(CBUS_BASE_ADDR + 0x370000)
48 #define PE_MEM_ACCESS_READ		(0 << 31)
56 							& 0xf) << 24)
59 #define CORE_DISABLE	0x00000000
60 #define CORE_ENABLE	0x00000001
61 #define CORE_SW_RESET	0x00000002
64 #define LMEM_HDR_SIZE		0x0010
65 #define LMEM_BUF_SIZE_LN2	0x7
69 #define DDR_HDR_SIZE		0x0100
70 #define DDR_BUF_SIZE_LN2	0xb