11335483aSStefan Roese/* 21335483aSStefan Roese * Copyright (C) 2016 Marvell Technology Group Ltd. 31335483aSStefan Roese * 41335483aSStefan Roese * This file is dual-licensed: you can use it either under the terms 51335483aSStefan Roese * of the GPLv2 or the X11 license, at your option. Note that this dual 61335483aSStefan Roese * licensing only applies to this file, and not this project as a 71335483aSStefan Roese * whole. 81335483aSStefan Roese * 91335483aSStefan Roese * a) This library is free software; you can redistribute it and/or 101335483aSStefan Roese * modify it under the terms of the GNU General Public License as 111335483aSStefan Roese * published by the Free Software Foundation; either version 2 of the 121335483aSStefan Roese * License, or (at your option) any later version. 131335483aSStefan Roese * 141335483aSStefan Roese * This library is distributed in the hope that it will be useful, 151335483aSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 161335483aSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 171335483aSStefan Roese * GNU General Public License for more details. 181335483aSStefan Roese * 191335483aSStefan Roese * Or, alternatively, 201335483aSStefan Roese * 211335483aSStefan Roese * b) Permission is hereby granted, free of charge, to any person 221335483aSStefan Roese * obtaining a copy of this software and associated documentation 231335483aSStefan Roese * files (the "Software"), to deal in the Software without 241335483aSStefan Roese * restriction, including without limitation the rights to use, 251335483aSStefan Roese * copy, modify, merge, publish, distribute, sublicense, and/or 261335483aSStefan Roese * sell copies of the Software, and to permit persons to whom the 271335483aSStefan Roese * Software is furnished to do so, subject to the following 281335483aSStefan Roese * conditions: 291335483aSStefan Roese * 301335483aSStefan Roese * The above copyright notice and this permission notice shall be 311335483aSStefan Roese * included in all copies or substantial portions of the Software. 321335483aSStefan Roese * 331335483aSStefan Roese * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 341335483aSStefan Roese * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 351335483aSStefan Roese * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 361335483aSStefan Roese * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 371335483aSStefan Roese * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 381335483aSStefan Roese * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 391335483aSStefan Roese * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 401335483aSStefan Roese * OTHER DEALINGS IN THE SOFTWARE. 411335483aSStefan Roese */ 421335483aSStefan Roese 431335483aSStefan Roese/* 441335483aSStefan Roese * Device Tree file for Marvell Armada AP806. 451335483aSStefan Roese */ 461335483aSStefan Roese 471335483aSStefan Roese#include <dt-bindings/interrupt-controller/arm-gic.h> 481335483aSStefan Roese 491335483aSStefan Roese/dts-v1/; 501335483aSStefan Roese 511335483aSStefan Roese/ { 521335483aSStefan Roese model = "Marvell Armada AP806"; 531335483aSStefan Roese compatible = "marvell,armada-ap806"; 541335483aSStefan Roese #address-cells = <2>; 551335483aSStefan Roese #size-cells = <2>; 561335483aSStefan Roese 571335483aSStefan Roese aliases { 581335483aSStefan Roese serial0 = &uart0; 591335483aSStefan Roese serial1 = &uart1; 601335483aSStefan Roese }; 611335483aSStefan Roese 621335483aSStefan Roese psci { 631335483aSStefan Roese compatible = "arm,psci-0.2"; 641335483aSStefan Roese method = "smc"; 651335483aSStefan Roese }; 661335483aSStefan Roese 67*cf63dad0SHeinrich Schuchardt reserved-memory { 68*cf63dad0SHeinrich Schuchardt #address-cells = <2>; 69*cf63dad0SHeinrich Schuchardt #size-cells = <2>; 70*cf63dad0SHeinrich Schuchardt ranges; 71*cf63dad0SHeinrich Schuchardt 72*cf63dad0SHeinrich Schuchardt psci-area@4000000 { 73*cf63dad0SHeinrich Schuchardt reg = <0x0 0x4000000 0x0 0x200000>; 74*cf63dad0SHeinrich Schuchardt no-map; 75*cf63dad0SHeinrich Schuchardt }; 76*cf63dad0SHeinrich Schuchardt }; 77*cf63dad0SHeinrich Schuchardt 781335483aSStefan Roese ap806 { 791335483aSStefan Roese #address-cells = <2>; 801335483aSStefan Roese #size-cells = <2>; 811335483aSStefan Roese compatible = "simple-bus"; 821335483aSStefan Roese interrupt-parent = <&gic>; 831335483aSStefan Roese ranges; 841335483aSStefan Roese 851335483aSStefan Roese config-space { 861335483aSStefan Roese #address-cells = <1>; 871335483aSStefan Roese #size-cells = <1>; 881335483aSStefan Roese compatible = "simple-bus"; 891335483aSStefan Roese ranges = <0x0 0x0 0xf0000000 0x1000000>; 901335483aSStefan Roese 911335483aSStefan Roese gic: interrupt-controller@210000 { 921335483aSStefan Roese compatible = "arm,gic-400"; 931335483aSStefan Roese #interrupt-cells = <3>; 941335483aSStefan Roese #address-cells = <1>; 951335483aSStefan Roese #size-cells = <1>; 961335483aSStefan Roese ranges; 971335483aSStefan Roese interrupt-controller; 981335483aSStefan Roese interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 991335483aSStefan Roese reg = <0x210000 0x10000>, 1001335483aSStefan Roese <0x220000 0x20000>, 1011335483aSStefan Roese <0x240000 0x20000>, 1021335483aSStefan Roese <0x260000 0x20000>; 1031335483aSStefan Roese 1041335483aSStefan Roese gic_v2m0: v2m@280000 { 1051335483aSStefan Roese compatible = "arm,gic-v2m-frame"; 1061335483aSStefan Roese msi-controller; 1071335483aSStefan Roese reg = <0x280000 0x1000>; 1081335483aSStefan Roese arm,msi-base-spi = <160>; 1091335483aSStefan Roese arm,msi-num-spis = <32>; 1101335483aSStefan Roese }; 1111335483aSStefan Roese gic_v2m1: v2m@290000 { 1121335483aSStefan Roese compatible = "arm,gic-v2m-frame"; 1131335483aSStefan Roese msi-controller; 1141335483aSStefan Roese reg = <0x290000 0x1000>; 1151335483aSStefan Roese arm,msi-base-spi = <192>; 1161335483aSStefan Roese arm,msi-num-spis = <32>; 1171335483aSStefan Roese }; 1181335483aSStefan Roese gic_v2m2: v2m@2a0000 { 1191335483aSStefan Roese compatible = "arm,gic-v2m-frame"; 1201335483aSStefan Roese msi-controller; 1211335483aSStefan Roese reg = <0x2a0000 0x1000>; 1221335483aSStefan Roese arm,msi-base-spi = <224>; 1231335483aSStefan Roese arm,msi-num-spis = <32>; 1241335483aSStefan Roese }; 1251335483aSStefan Roese gic_v2m3: v2m@2b0000 { 1261335483aSStefan Roese compatible = "arm,gic-v2m-frame"; 1271335483aSStefan Roese msi-controller; 1281335483aSStefan Roese reg = <0x2b0000 0x1000>; 1291335483aSStefan Roese arm,msi-base-spi = <256>; 1301335483aSStefan Roese arm,msi-num-spis = <32>; 1311335483aSStefan Roese }; 1321335483aSStefan Roese }; 1331335483aSStefan Roese 1341335483aSStefan Roese timer { 1351335483aSStefan Roese compatible = "arm,armv8-timer"; 1361335483aSStefan Roese interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, 1371335483aSStefan Roese <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, 1381335483aSStefan Roese <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, 1391335483aSStefan Roese <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 1401335483aSStefan Roese }; 1411335483aSStefan Roese 1421335483aSStefan Roese odmi: odmi@300000 { 1431335483aSStefan Roese compatible = "marvell,odmi-controller"; 1441335483aSStefan Roese interrupt-controller; 1451335483aSStefan Roese msi-controller; 1461335483aSStefan Roese marvell,odmi-frames = <4>; 1471335483aSStefan Roese reg = <0x300000 0x4000>, 1481335483aSStefan Roese <0x304000 0x4000>, 1491335483aSStefan Roese <0x308000 0x4000>, 1501335483aSStefan Roese <0x30C000 0x4000>; 1511335483aSStefan Roese marvell,spi-base = <128>, <136>, <144>, <152>; 1521335483aSStefan Roese }; 1531335483aSStefan Roese 154f99386c5SKonstantin Porotchkin ap_pinctl: ap-pinctl@6F4000 { 155f246648dSEvan Wang compatible = "marvell,ap806-pinctrl"; 156f99386c5SKonstantin Porotchkin bank-name ="apn-806"; 157f99386c5SKonstantin Porotchkin reg = <0x6F4000 0x10>; 158f99386c5SKonstantin Porotchkin pin-count = <20>; 159f99386c5SKonstantin Porotchkin max-func = <3>; 160f99386c5SKonstantin Porotchkin 161f99386c5SKonstantin Porotchkin ap_i2c0_pins: i2c-pins-0 { 162f99386c5SKonstantin Porotchkin marvell,pins = < 4 5 >; 163f99386c5SKonstantin Porotchkin marvell,function = <3>; 164f99386c5SKonstantin Porotchkin }; 165f99386c5SKonstantin Porotchkin ap_emmc_pins: emmc-pins-0 { 166f99386c5SKonstantin Porotchkin marvell,pins = < 0 1 2 3 4 5 6 7 167f99386c5SKonstantin Porotchkin 8 9 10 >; 168f99386c5SKonstantin Porotchkin marvell,function = <1>; 169f99386c5SKonstantin Porotchkin }; 170f99386c5SKonstantin Porotchkin }; 171f99386c5SKonstantin Porotchkin 1729eb34681SKonstantin Porotchkin ap_gpio0: gpio@6F5040 { 1739eb34681SKonstantin Porotchkin compatible = "marvell,orion-gpio"; 1749eb34681SKonstantin Porotchkin reg = <0x6F5040 0x40>; 1759eb34681SKonstantin Porotchkin ngpios = <20>; 1769eb34681SKonstantin Porotchkin gpio-controller; 1779eb34681SKonstantin Porotchkin #gpio-cells = <2>; 1789eb34681SKonstantin Porotchkin }; 1799eb34681SKonstantin Porotchkin 1801335483aSStefan Roese xor@400000 { 1811335483aSStefan Roese compatible = "marvell,mv-xor-v2"; 1821335483aSStefan Roese reg = <0x400000 0x1000>, 1831335483aSStefan Roese <0x410000 0x1000>; 1841335483aSStefan Roese msi-parent = <&gic_v2m0>; 1851335483aSStefan Roese dma-coherent; 1861335483aSStefan Roese }; 1871335483aSStefan Roese 1881335483aSStefan Roese xor@420000 { 1891335483aSStefan Roese compatible = "marvell,mv-xor-v2"; 1901335483aSStefan Roese reg = <0x420000 0x1000>, 1911335483aSStefan Roese <0x430000 0x1000>; 1921335483aSStefan Roese msi-parent = <&gic_v2m0>; 1931335483aSStefan Roese dma-coherent; 1941335483aSStefan Roese }; 1951335483aSStefan Roese 1961335483aSStefan Roese xor@440000 { 1971335483aSStefan Roese compatible = "marvell,mv-xor-v2"; 1981335483aSStefan Roese reg = <0x440000 0x1000>, 1991335483aSStefan Roese <0x450000 0x1000>; 2001335483aSStefan Roese msi-parent = <&gic_v2m0>; 2011335483aSStefan Roese dma-coherent; 2021335483aSStefan Roese }; 2031335483aSStefan Roese 2041335483aSStefan Roese xor@460000 { 2051335483aSStefan Roese compatible = "marvell,mv-xor-v2"; 2061335483aSStefan Roese reg = <0x460000 0x1000>, 2071335483aSStefan Roese <0x470000 0x1000>; 2081335483aSStefan Roese msi-parent = <&gic_v2m0>; 2091335483aSStefan Roese dma-coherent; 2101335483aSStefan Roese }; 2111335483aSStefan Roese 2121335483aSStefan Roese spi0: spi@510600 { 2131335483aSStefan Roese compatible = "marvell,armada-380-spi"; 2141335483aSStefan Roese reg = <0x510600 0x50>; 2151335483aSStefan Roese #address-cells = <1>; 2161335483aSStefan Roese #size-cells = <0>; 2171335483aSStefan Roese cell-index = <0>; 2181335483aSStefan Roese interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 2191335483aSStefan Roese clocks = <&ap_syscon 3>; 2201335483aSStefan Roese status = "disabled"; 2211335483aSStefan Roese }; 2221335483aSStefan Roese 2231335483aSStefan Roese i2c0: i2c@511000 { 2241335483aSStefan Roese compatible = "marvell,mv78230-i2c"; 2251335483aSStefan Roese reg = <0x511000 0x20>; 2261335483aSStefan Roese #address-cells = <1>; 2271335483aSStefan Roese #size-cells = <0>; 2281335483aSStefan Roese interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 2291335483aSStefan Roese timeout-ms = <1000>; 2301335483aSStefan Roese clocks = <&ap_syscon 3>; 2311335483aSStefan Roese status = "disabled"; 2321335483aSStefan Roese }; 2331335483aSStefan Roese 2341335483aSStefan Roese uart0: serial@512000 { 2351335483aSStefan Roese compatible = "snps,dw-apb-uart"; 2361335483aSStefan Roese reg = <0x512000 0x100>; 2371335483aSStefan Roese reg-shift = <2>; 2381335483aSStefan Roese interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 2391335483aSStefan Roese reg-io-width = <1>; 2401335483aSStefan Roese clocks = <&ap_syscon 3>; 2411335483aSStefan Roese status = "disabled"; 242b5fbf5aaSStefan Roese clock-frequency = <200000000>; 2431335483aSStefan Roese }; 2441335483aSStefan Roese 2451335483aSStefan Roese uart1: serial@512100 { 2461335483aSStefan Roese compatible = "snps,dw-apb-uart"; 2471335483aSStefan Roese reg = <0x512100 0x100>; 2481335483aSStefan Roese reg-shift = <2>; 2491335483aSStefan Roese interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 2501335483aSStefan Roese reg-io-width = <1>; 2511335483aSStefan Roese clocks = <&ap_syscon 3>; 2521335483aSStefan Roese status = "disabled"; 2531335483aSStefan Roese 2541335483aSStefan Roese }; 2551335483aSStefan Roese 256b14b0b1eSStefan Roese ap_sdhci0: sdhci@6e0000 { 257b14b0b1eSStefan Roese compatible = "marvell,armada-8k-sdhci"; 258b14b0b1eSStefan Roese reg = <0x6e0000 0x300>; 259b14b0b1eSStefan Roese interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 260b14b0b1eSStefan Roese dma-coherent; 261b14b0b1eSStefan Roese status = "disabled"; 262b14b0b1eSStefan Roese }; 263b14b0b1eSStefan Roese 2641335483aSStefan Roese ap_syscon: system-controller@6f4000 { 2651335483aSStefan Roese compatible = "marvell,ap806-system-controller", 2661335483aSStefan Roese "syscon"; 2671335483aSStefan Roese #clock-cells = <1>; 2681335483aSStefan Roese clock-output-names = "ap-cpu-cluster-0", 2691335483aSStefan Roese "ap-cpu-cluster-1", 2701335483aSStefan Roese "ap-fixed", "ap-mss"; 2711335483aSStefan Roese reg = <0x6f4000 0x1000>; 2721335483aSStefan Roese }; 2731335483aSStefan Roese }; 2741335483aSStefan Roese }; 2751335483aSStefan Roese}; 276