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Searched +full:0 +full:x2008 (Results 1 – 25 of 205) sorted by relevance

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/openbmc/linux/drivers/reset/
H A Dreset-uniphier.c19 #define UNIPHIER_RESET_ACTIVE_LOW BIT(0)
44 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
45 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (Ether, HSC, MIO) */
50 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
51 UNIPHIER_RESETX(6, 0x2000, 12), /* Ether */
52 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC, MIO, RLE) */
53 UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (Ether, SATA, USB3) */
54 UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
55 UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
56 UNIPHIER_RESETX(28, 0x2000, 18), /* SATA0 */
[all …]
/openbmc/qemu/hw/usb/
H A Dquirks-pl2303-ids.h11 #define BENQ_VENDOR_ID 0x04a5
12 #define BENQ_PRODUCT_ID_S81 0x4027
14 #define PL2303_VENDOR_ID 0x067b
15 #define PL2303_PRODUCT_ID 0x2303
16 #define PL2303_PRODUCT_ID_RSAQ2 0x04bb
17 #define PL2303_PRODUCT_ID_DCU11 0x1234
18 #define PL2303_PRODUCT_ID_PHAROS 0xaaa0
19 #define PL2303_PRODUCT_ID_RSAQ3 0xaaa2
20 #define PL2303_PRODUCT_ID_ALDIGA 0x0611
21 #define PL2303_PRODUCT_ID_MMX 0x0612
[all …]
/openbmc/linux/drivers/usb/serial/
H A Dpl2303.h6 #define BENQ_VENDOR_ID 0x04a5
7 #define BENQ_PRODUCT_ID_S81 0x4027
9 #define PL2303_VENDOR_ID 0x067b
10 #define PL2303_PRODUCT_ID 0x2303
11 #define PL2303_PRODUCT_ID_TB 0x2304
12 #define PL2303_PRODUCT_ID_GC 0x23a3
13 #define PL2303_PRODUCT_ID_GB 0x23b3
14 #define PL2303_PRODUCT_ID_GT 0x23c3
15 #define PL2303_PRODUCT_ID_GL 0x23d3
16 #define PL2303_PRODUCT_ID_GE 0x23e3
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/
H A Dsc64-regs.h12 #define SC_BASE_ADDR 0x61840000
14 #define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
15 #define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
16 #define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)
17 #define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010)
18 #define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014)
19 #define SC_RSTCTRL7 (SC_BASE_ADDR | 0x2018)
21 #define SC_CLKCTRL (SC_BASE_ADDR | 0x2100)
22 #define SC_CLKCTRL3 (SC_BASE_ADDR | 0x2108)
23 #define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c)
[all …]
/openbmc/u-boot/arch/mips/include/asm/
H A Dcm.h11 #define GCR_BASE 0x0008
12 #define GCR_BASE_UPPER 0x000c
13 #define GCR_REV 0x0030
14 #define GCR_L2_CONFIG 0x0130
15 #define GCR_L2_TAG_ADDR 0x0600
16 #define GCR_L2_TAG_ADDR_UPPER 0x0604
17 #define GCR_L2_TAG_STATE 0x0608
18 #define GCR_L2_TAG_STATE_UPPER 0x060c
19 #define GCR_L2_DATA 0x0610
20 #define GCR_L2_DATA_UPPER 0x0614
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
/openbmc/linux/sound/soc/codecs/
H A Drt5514.h15 #define RT5514_DEVICE_ID 0x10ec5514
17 #define RT5514_RESET 0x2000
18 #define RT5514_PWR_ANA1 0x2004
19 #define RT5514_PWR_ANA2 0x2008
20 #define RT5514_I2S_CTRL1 0x2010
21 #define RT5514_I2S_CTRL2 0x2014
22 #define RT5514_VAD_CTRL6 0x2030
23 #define RT5514_EXT_VAD_CTRL 0x206c
24 #define RT5514_DIG_IO_CTRL 0x2070
25 #define RT5514_PAD_CTRL1 0x2080
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sm6115-dpu.yaml63 reg = <0x05e01000 0x8f000>,
64 <0x05eb0000 0x2008>;
79 interrupts = <0>;
83 #size-cells = <0>;
85 port@0 {
86 reg = <0>;
H A Dqcom,qcm2290-dpu.yaml61 reg = <0x05e01000 0x8f000>,
62 <0x05eb0000 0x2008>;
76 interrupts = <0>;
80 #size-cells = <0>;
82 port@0 {
83 reg = <0>;
H A Dqcom,sc7280-dpu.yaml63 reg = <0x0ae01000 0x8f000>,
64 <0x0aeb0000 0x2008>;
82 interrupts = <0>;
88 #size-cells = <0>;
90 port@0 {
91 reg = <0>;
H A Dqcom,sm8150-dpu.yaml54 reg = <0x0ae01000 0x8f000>,
55 <0x0aeb0000 0x2008>;
71 interrupts = <0>;
75 #size-cells = <0>;
77 port@0 {
78 reg = <0>;
H A Dqcom,sdm845-dpu.yaml61 reg = <0x0ae01000 0x8f000>,
62 <0x0aeb0000 0x2008>;
73 interrupts = <0>;
79 #size-cells = <0>;
81 port@0 {
82 reg = <0>;
H A Dqcom,msm8998-dpu.yaml64 reg = <0x0c901000 0x8f000>,
65 <0x0c9a8e00 0xf0>,
66 <0x0c9b0000 0x2008>,
67 <0x0c9b8000 0x1040>;
78 interrupts = <0>;
84 #size-cells = <0>;
86 port@0 {
87 reg = <0>;
H A Dqcom,sm8250-dpu.yaml61 reg = <0x0ae01000 0x8f000>,
62 <0x0aeb0000 0x2008>;
78 interrupts = <0>;
82 #size-cells = <0>;
84 port@0 {
85 reg = <0>;
H A Dqcom,sc7180-dpu.yaml87 reg = <0x0ae01000 0x8f000>,
88 <0x0aeb0000 0x2008>;
102 interrupts = <0>;
108 #size-cells = <0>;
110 port@0 {
111 reg = <0>;
H A Dqcom,sm8550-dpu.yaml64 reg = <0x0ae01000 0x8f000>,
65 <0x0aeb0000 0x2008>;
88 interrupts = <0>;
92 #size-cells = <0>;
94 port@0 {
95 reg = <0>;
H A Dqcom,sc8280xp-dpu.yaml61 reg = <0x0ae01000 0x8f000>,
62 <0x0aeb0000 0x2008>;
87 interrupts = <0>;
91 #size-cells = <0>;
93 port@0 {
94 reg = <0>;
H A Dqcom,sm8350-dpu.yaml58 reg = <0x0ae01000 0x8f000>,
59 <0x0aeb0000 0x2008>;
82 interrupts = <0>;
86 #size-cells = <0>;
88 port@0 {
89 reg = <0>;
H A Dqcom,sm8450-dpu.yaml65 reg = <0x0ae01000 0x8f000>,
66 <0x0aeb0000 0x2008>;
89 interrupts = <0>;
93 #size-cells = <0>;
95 port@0 {
96 reg = <0>;
/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
H A Dclk-fsd.c23 /* Register Offset definitions for CMU_CMU (0x11c10000) */
24 #define PLL_LOCKTIME_PLL_SHARED0 0x0
25 #define PLL_LOCKTIME_PLL_SHARED1 0x4
26 #define PLL_LOCKTIME_PLL_SHARED2 0x8
27 #define PLL_LOCKTIME_PLL_SHARED3 0xc
28 #define PLL_CON0_PLL_SHARED0 0x100
29 #define PLL_CON0_PLL_SHARED1 0x120
30 #define PLL_CON0_PLL_SHARED2 0x140
31 #define PLL_CON0_PLL_SHARED3 0x160
32 #define MUX_CMU_CIS0_CLKMUX 0x1000
[all …]
/openbmc/u-boot/arch/sh/include/asm/
H A Dcpu_sh7785.h12 #define CCR_CACHE_INIT 0x0000090b
15 #define TRA 0xFF000020
16 #define EXPEVT 0xFF000024
17 #define INTEVT 0xFF000028
20 #define CCR 0xFF00001C
21 #define QACR0 0xFF000038
22 #define QACR1 0xFF00003C
23 #define RAMCR 0xFF000074
27 #define WDTST 0xFFCC0000
28 #define WDTCSR 0xFFCC0004
[all …]
/openbmc/u-boot/include/
H A Dmsc01.h14 #define MSC01_BIU_IP1BAS1L_OFS 0x0208
15 #define MSC01_BIU_IP1MSK1L_OFS 0x0218
16 #define MSC01_BIU_IP1BAS2L_OFS 0x0248
17 #define MSC01_BIU_IP1MSK2L_OFS 0x0258
18 #define MSC01_BIU_IP2BAS1L_OFS 0x0288
19 #define MSC01_BIU_IP2MSK1L_OFS 0x0298
20 #define MSC01_BIU_IP2BAS2L_OFS 0x02c8
21 #define MSC01_BIU_IP2MSK2L_OFS 0x02d8
22 #define MSC01_BIU_IP3BAS1L_OFS 0x0308
23 #define MSC01_BIU_IP3MSK1L_OFS 0x0318
[all …]
/openbmc/linux/sound/soc/amd/acp/
H A Dchip_offset_byte.h14 #define ACPAXI2AXI_ATU_CTRL 0xC40
15 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0xC20
16 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0xC24
18 #define ACP_PGFSM_CONTROL 0x141C
19 #define ACP_PGFSM_STATUS 0x1420
20 #define ACP_SOFT_RESET 0x1000
21 #define ACP_CONTROL 0x1004
24 (adata->acp_base + adata->rsrc->irq_reg_offset + offset + (ctrl * 0x04))
26 #define ACP_EXTERNAL_INTR_ENB(adata) ACP_EXTERNAL_INTR_REG_ADDR(adata, 0x0, 0x0)
27 #define ACP_EXTERNAL_INTR_CNTL(adata, ctrl) ACP_EXTERNAL_INTR_REG_ADDR(adata, 0x4, ctrl)
[all …]
/openbmc/linux/drivers/media/platform/qcom/venus/
H A Dhfi_venus_io.h9 #define VBIF_BASE 0x80000
11 #define VBIF_AXI_HALT_CTRL0 0x208
12 #define VBIF_AXI_HALT_CTRL1 0x20c
14 #define VBIF_AXI_HALT_CTRL0_HALT_REQ BIT(0)
15 #define VBIF_AXI_HALT_CTRL1_HALT_ACK BIT(0)
18 #define CPU_BASE 0xc0000
20 #define CPU_CS_BASE (CPU_BASE + 0x12000)
21 #define CPU_IC_BASE (CPU_BASE + 0x1f000)
22 #define CPU_BASE_V6 0xa0000
24 #define CPU_IC_BASE_V6 (CPU_BASE_V6 + 0x138)
[all …]

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