/openbmc/u-boot/arch/arm/mach-exynos/include/mach/ |
H A D | clock.h | 12 unsigned char res1[0x4200]; 14 unsigned char res2[0x1fc]; 16 unsigned char res4[0xfc]; 18 unsigned char res5[0xfc]; 20 unsigned char res6[0x1fc]; 22 unsigned char res7[0x1fc]; 25 unsigned char res8[0x37f8]; 27 unsigned char res9[0x1fc]; 29 unsigned char res10[0xfc]; 31 unsigned char res11[0xfc]; [all …]
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/openbmc/linux/drivers/accel/habanalabs/include/goya/asic_reg/ |
H A D | psoc_global_conf_masks.h | 23 #define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT 0 24 #define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK 0xFFFFFFFF 27 #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT 0 28 #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK 0x1 31 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT 0 32 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK 0x1 35 #define PSOC_GLOBAL_CONF_BTM_FSM_STATE_SHIFT 0 36 #define PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK 0xF 39 #define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT 0 40 #define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_MASK 0xF [all …]
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/openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imx25-pinfunc.h | 16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000 17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000 19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000 20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000 21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000 23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000 24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000 25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000 26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000 28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000 [all …]
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/openbmc/linux/drivers/phy/qualcomm/ |
H A D | phy-qcom-qmp-pcs-v6_20.h | 10 #define QPHY_V6_20_PCS_G3S2_PRE_GAIN 0x178 11 #define QPHY_V6_20_PCS_RX_SIGDET_LVL 0x190 12 #define QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL 0x1b8 13 #define QPHY_V6_20_PCS_TX_RX_CONFIG1 0x1dc 14 #define QPHY_V6_20_PCS_TX_RX_CONFIG2 0x1e0 15 #define QPHY_V6_20_PCS_EQ_CONFIG4 0x1f8 16 #define QPHY_V6_20_PCS_EQ_CONFIG5 0x1fc
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H A D | phy-qcom-qmp-pcs-ufs-v6.h | 10 #define QPHY_V6_PCS_UFS_PHY_START 0x000 11 #define QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL 0x004 12 #define QPHY_V6_PCS_UFS_SW_RESET 0x008 13 #define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 14 #define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 15 #define QPHY_V6_PCS_UFS_PLL_CNTL 0x02c 16 #define QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 17 #define QPHY_V6_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 18 #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 19 #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 [all …]
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H A D | phy-qcom-qmp-qserdes-txrx-v6_20.h | 9 #define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX 0x30 10 #define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 11 #define QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN 0xac 12 #define QSERDES_V6_20_TX_LANE_MODE_1 0x78 13 #define QSERDES_V6_20_TX_LANE_MODE_2 0x7c 14 #define QSERDES_V6_20_TX_LANE_MODE_3 0x80 16 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2 0x08 17 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3 0x0c 18 #define QSERDES_V6_20_RX_UCDR_PI_CONTROLS 0x20 19 #define QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3 0x34 [all …]
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H A D | phy-qcom-qmp-qserdes-txrx-v4_20.h | 10 #define QSERDES_V4_20_TX_LANE_MODE_1 0x88 11 #define QSERDES_V4_20_TX_LANE_MODE_2 0x8c 12 #define QSERDES_V4_20_TX_LANE_MODE_3 0x90 13 #define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4 14 #define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0 17 #define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008 18 #define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058 19 #define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac 20 #define QSERDES_V4_20_RX_DFE_3 0x110 21 #define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134 [all …]
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H A D | phy-qcom-qmp-qserdes-txrx-v5_20.h | 10 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30 11 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 12 #define QSERDES_V5_20_TX_LANE_MODE_1 0x78 13 #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c 14 #define QSERDES_V5_20_TX_LANE_MODE_3 0x80 15 #define QSERDES_V5_20_TX_RCV_DETECT_LVL_2 0x90 16 #define QSERDES_V5_20_TX_VMODE_CTRL1 0xb0 17 #define QSERDES_V5_20_TX_PI_QEC_CTRL 0xcc 20 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008 21 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c [all …]
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H A D | phy-qcom-qmp-pcie-qhp.h | 10 #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14 11 #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20 12 #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24 13 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28 14 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c 15 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34 16 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38 17 #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54 18 #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58 19 #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c [all …]
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H A D | phy-qcom-qmp-pcs-v3.h | 10 #define QPHY_V3_PCS_SW_RESET 0x000 11 #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004 12 #define QPHY_V3_PCS_START_CONTROL 0x008 13 #define QPHY_V3_PCS_TXMGN_V0 0x00c 14 #define QPHY_V3_PCS_TXMGN_V1 0x010 15 #define QPHY_V3_PCS_TXMGN_V2 0x014 16 #define QPHY_V3_PCS_TXMGN_V3 0x018 17 #define QPHY_V3_PCS_TXMGN_V4 0x01c 18 #define QPHY_V3_PCS_TXMGN_LS 0x020 19 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024 [all …]
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/openbmc/linux/drivers/clk/hisilicon/ |
H A D | clk-hi3620.c | 66 { HI3620_OSC32K, "osc32k", NULL, 0, 32768, }, 67 { HI3620_OSC26M, "osc26m", NULL, 0, 26000000, }, 68 { HI3620_PCLK, "pclk", NULL, 0, 26000000, }, 69 { HI3620_PLL_ARM0, "armpll0", NULL, 0, 1600000000, }, 70 { HI3620_PLL_ARM1, "armpll1", NULL, 0, 1600000000, }, 71 { HI3620_PLL_PERI, "armpll2", NULL, 0, 1440000000, }, 72 { HI3620_PLL_USB, "armpll3", NULL, 0, 1440000000, }, 73 { HI3620_PLL_HDMI, "armpll4", NULL, 0, 1188000000, }, 74 { HI3620_PLL_GPU, "armpll5", NULL, 0, 1300000000, }, 79 { HI3620_RCLK_TCXO, "rclk_tcxo", "osc26m", 1, 4, 0, }, [all …]
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/openbmc/linux/include/dt-bindings/clock/ |
H A D | dm814.h | 8 #define DM814_CLKCTRL_OFFSET 0x0 12 #define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58) 15 #define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150) 16 #define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154) 17 #define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158) 18 #define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c) 19 #define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160) 20 #define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164) 21 #define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168) 22 #define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c) [all …]
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H A D | dm816.h | 8 #define DM816_CLKCTRL_OFFSET 0x0 12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58) 15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150) 16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154) 17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158) 18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c) 19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160) 20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164) 21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168) 22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170) [all …]
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/openbmc/u-boot/arch/arm/mach-at91/include/mach/ |
H A D | sama5_matrix.h | 13 u32 mcfg[16]; /* 0x00 ~ 0x3c: Master Configuration Register */ 14 u32 scfg[16]; /* 0x40 ~ 0x7c: Slave Configuration Register */ 15 u32 pras[16][2];/* 0x80 ~ 0xfc: Priority Register A/B */ 16 u32 res1[20]; /* 0x100 ~ 0x14c */ 17 u32 meier; /* 0x150: Master Error Interrupt Enable Register */ 18 u32 meidr; /* 0x154: Master Error Interrupt Disable Register */ 19 u32 meimr; /* 0x158: Master Error Interrupt Mask Register */ 20 u32 mesr; /* 0x15c: Master Error Status Register */ 21 u32 mear[16]; /* 0x160 ~ 0x19c: Master Error Address Register */ 22 u32 res2[17]; /* 0x1A0 ~ 0x1E0 */ [all …]
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/openbmc/linux/sound/soc/meson/ |
H A D | aiu.h | 18 PCLK = 0, 62 #define AIU_IEC958_BPF 0x000 63 #define AIU_958_MISC 0x010 64 #define AIU_IEC958_DCU_FF_CTRL 0x01c 65 #define AIU_958_CHSTAT_L0 0x020 66 #define AIU_958_CHSTAT_L1 0x024 67 #define AIU_958_CTRL 0x028 68 #define AIU_I2S_SOURCE_DESC 0x034 69 #define AIU_I2S_DAC_CFG 0x040 70 #define AIU_I2S_SYNC 0x044 [all …]
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/openbmc/linux/arch/sh/drivers/pci/ |
H A D | pci-sh7780.h | 13 #define PCIECR 0xFE000008 14 #define PCIECR_ENBL 0x01 17 #define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */ 18 #define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */ 20 #define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */ 23 #define SH7780_PCIIR 0x114 /* PCI Interrupt Register */ 24 #define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */ 25 #define SH7780_PCIAIR 0x11C /* Error Address Register */ 26 #define SH7780_PCICIR 0x120 /* Error Command/Data Register */ 27 #define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */ [all …]
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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
H A D | fsl,imx93-pinctrl.yaml | 76 reg = <0x30330000 0x10000>; 80 <0x48 0x1f8 0x41c 0x1 0x0 0x49>, 81 <0x4c 0x1fc 0x418 0x1 0x0 0x49>;
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/openbmc/u-boot/arch/arm/dts/ |
H A D | imx53-kp.dts | 24 pinctrl-0 = <&pinctrl_eth>; 32 pinctrl-0 = <&pinctrl_i2c2>; 43 reg = <0x8>; 49 pinctrl-0 = <&pinctrl_i2c3>; 61 pinctrl-0 = <&pinctrl_hog>; 66 MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc 67 MX53_PAD_FEC_MDC__FEC_MDC 0x4 68 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180 69 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180 70 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4 [all …]
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H A D | dra72x-mmc-iodelay.dtsi | 45 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 46 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 47 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 48 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 49 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 50 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ 56 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 57 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 58 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 59 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ [all …]
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H A D | imx53-cx9020.dts | 11 #define MX53_PAD_EIM_D26__UART2_RXD_MUX 0x144 0x48c 0x880 0x2 0x0 12 #define MX53_PAD_EIM_D27__UART2_TXD_MUX 0x148 0x490 0x000 0x2 0x0 13 #define MX53_PAD_EIM_D28__UART2_RTS 0x14c 0x494 0x87c 0x2 0x0 14 #define MX53_PAD_EIM_D29__UART2_CTS 0x150 0x498 0x000 0x2 0x0 27 pinctrl-0 = <&pinctrl_hog>; 32 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 33 MX53_PAD_GPIO_8__GPIO1_8 0x80000000 34 MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 35 MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 36 MX53_PAD_GPIO_1__GPIO1_1 0x80000000 [all …]
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/openbmc/linux/drivers/net/wireless/mediatek/mt7601u/ |
H A D | eeprom.h | 12 #define MT7601U_EE_MAX_VER 0x0d 18 MT_EE_CHIP_ID = 0x00, 19 MT_EE_VERSION_FAE = 0x02, 20 MT_EE_VERSION_EE = 0x03, 21 MT_EE_MAC_ADDR = 0x04, 22 MT_EE_NIC_CONF_0 = 0x34, 23 MT_EE_NIC_CONF_1 = 0x36, 24 MT_EE_COUNTRY_REGION = 0x39, 25 MT_EE_FREQ_OFFSET = 0x3a, 26 MT_EE_NIC_CONF_2 = 0x42, [all …]
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/openbmc/linux/arch/arm64/boot/dts/freescale/ |
H A D | imx8mn-pinfunc.h | 14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0 15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3 16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0 17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3 18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0 20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 [all …]
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/openbmc/linux/drivers/pinctrl/ |
H A D | pinctrl-pic32.h | 12 #define ANSEL_REG 0x00 13 #define TRIS_REG 0x10 14 #define PORT_REG 0x20 15 #define LAT_REG 0x30 16 #define ODCU_REG 0x40 17 #define CNPU_REG 0x50 18 #define CNPD_REG 0x60 19 #define CNCON_REG 0x70 20 #define CNEN_REG 0x80 21 #define CNSTAT_REG 0x90 [all …]
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/openbmc/linux/arch/arm/boot/dts/ti/omap/ |
H A D | dra72x-mmc-iodelay.dtsi | 37 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 38 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 39 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 40 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 41 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 42 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ 48 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 49 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 50 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 51 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-stv0991/ |
H A D | stv0991_creg.h | 11 u32 version; /* offset 0x0 */ 12 u32 hdpctl; /* offset 0x4 */ 13 u32 hdpval; /* offset 0x8 */ 14 u32 hdpgposet; /* offset 0xc */ 15 u32 hdpgpoclr; /* offset 0x10 */ 16 u32 hdpgpoval; /* offset 0x14 */ 17 u32 stm_mux; /* offset 0x18 */ 18 u32 sysctrl_1; /* offset 0x1c */ 19 u32 sysctrl_2; /* offset 0x20 */ 20 u32 sysctrl_3; /* offset 0x24 */ [all …]
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