15fc21d1bSDmitry Baryshkov /* SPDX-License-Identifier: GPL-2.0 */ 25fc21d1bSDmitry Baryshkov /* 35fc21d1bSDmitry Baryshkov * Copyright (c) 2017, The Linux Foundation. All rights reserved. 45fc21d1bSDmitry Baryshkov */ 55fc21d1bSDmitry Baryshkov 65fc21d1bSDmitry Baryshkov #ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_20_H_ 75fc21d1bSDmitry Baryshkov #define QCOM_PHY_QMP_QSERDES_TXRX_V5_20_H_ 85fc21d1bSDmitry Baryshkov 95fc21d1bSDmitry Baryshkov /* Only for QMP V5_20 PHY - TX registers */ 105fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30 115fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 125fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_TX_LANE_MODE_1 0x78 135fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c 1492bd868fSRohit Agarwal #define QSERDES_V5_20_TX_LANE_MODE_3 0x80 1592bd868fSRohit Agarwal #define QSERDES_V5_20_TX_RCV_DETECT_LVL_2 0x90 1692bd868fSRohit Agarwal #define QSERDES_V5_20_TX_VMODE_CTRL1 0xb0 1792bd868fSRohit Agarwal #define QSERDES_V5_20_TX_PI_QEC_CTRL 0xcc 185fc21d1bSDmitry Baryshkov 195fc21d1bSDmitry Baryshkov /* Only for QMP V5_20 PHY - RX registers */ 205fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008 215fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c 22*a05b6d51SMrinmay Sarkar #define QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3 0x01c 235fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_PI_CONTROLS 0x020 245fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c 255fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030 265fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c 2792bd868fSRohit Agarwal #define QSERDES_V5_20_RX_DFE_1 0x088 2892bd868fSRohit Agarwal #define QSERDES_V5_20_RX_DFE_2 0x08c 295fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_3 0x090 305fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_DAC_ENABLE1 0x0b4 3192bd868fSRohit Agarwal #define QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH1 0x0bc 3292bd868fSRohit Agarwal #define QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH2 0x0c0 335fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1 0x0c4 345fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2 0x0c8 3592bd868fSRohit Agarwal #define QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH1 0x0cc 3692bd868fSRohit Agarwal #define QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH2 0x0d0 3792bd868fSRohit Agarwal #define QSERDES_V5_20_RX_VGA_CAL_CNTRL1 0x0d4 3892bd868fSRohit Agarwal #define QSERDES_V5_20_RX_VGA_CAL_CNTRL2 0x0d8 395fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL 0x0dc 405fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_GM_CAL 0x0ec 4192bd868fSRohit Agarwal #define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL2 0x100 4292bd868fSRohit Agarwal #define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL3 0x104 435fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4 0x108 4492bd868fSRohit Agarwal #define QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x118 4592bd868fSRohit Agarwal #define QSERDES_V5_20_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x11c 4692bd868fSRohit Agarwal #define QSERDES_V5_20_RX_SIGDET_ENABLES 0x120 4792bd868fSRohit Agarwal #define QSERDES_V5_20_RX_SIGDET_CNTRL 0x124 4892bd868fSRohit Agarwal #define QSERDES_V5_20_RX_SIGDET_DEGLITCH_CNTRL 0x12c 4992bd868fSRohit Agarwal #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0 0x160 505fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1 0x164 515fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2 0x168 525fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3 0x16c 5392bd868fSRohit Agarwal #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4 0x170 545fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5 0x174 555fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6 0x178 565fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B0 0x17c 575fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B1 0x180 585fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B2 0x184 595fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B3 0x188 605fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B4 0x18c 615fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B5 0x190 625fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B6 0x194 635fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B0 0x198 645fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B1 0x19c 655fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B2 0x1a0 665fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B3 0x1a4 675fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B4 0x1a8 685fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B5 0x1ac 695fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B6 0x1b0 705fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_PHPRE_CTRL 0x1b4 7192bd868fSRohit Agarwal #define QSERDES_V5_20_RX_DFE_DAC_ENABLE2 0x1b8 7292bd868fSRohit Agarwal #define QSERDES_V5_20_RX_DFE_EN_TIMER 0x1bc 735fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x1c0 7492bd868fSRohit Agarwal #define QSERDES_V5_20_RX_DCC_CTRL1 0x1c4 755fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4 765fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3 0x1f8 775fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc 785fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3 0x200 795fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x204 805fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3 0x208 815fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3 0x210 825fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218 835fc21d1bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220 84*a05b6d51SMrinmay Sarkar #define QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32 0x238 855fc21d1bSDmitry Baryshkov 865fc21d1bSDmitry Baryshkov #endif 87