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/openbmc/linux/Documentation/devicetree/bindings/soc/aspeed/
H A Dxdma.yaml80 reg = <0x1e6e2000 0x1000>;
81 ranges = <0 0x1e6e2000 0x1000>;
87 reg = <0x560 0x4>;
94 reg = <0x1e6e7000 0x100>;
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Daspeed,ast2x00-scu.yaml45 '^p2a-control@[0-9a-f]+$':
49 '^pinctrl(@[0-9a-f]+)?$':
55 '^interrupt-controller@[0-9a-f]+$':
59 '^silicon-id@[0-9a-f]+$':
97 reg = <0x1e6e2000 0x1a8>;
103 ranges = <0x0 0x1e6e2000 0x1000>;
107 reg = <0x7c 0x4>, <0x150 0x8>;
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Daspeed,ast2400-pinctrl.yaml202 reg = <0x1e6e2000 0x1a8>;
208 ranges = <0x0 0x1e6e2000 0x1000>;
H A Daspeed,ast2500-pinctrl.yaml37 0: compatible with "aspeed,ast2500-gfx", "syscon"
231 reg = <0x1e6e2000 0x1a8>;
237 ranges = <0x0 0x1e6e2000 0x1000>;
H A Daspeed,ast2600-pinctrl.yaml514 reg = <0x1e6e2000 0xf6c>;
520 ranges = <0x0 0x1e6e2000 0x1000>;
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Daspeed,ast2xxx-scu-ic.txt15 ranges = <0 0x1e6e2000 0x1a8>;
/openbmc/u-boot/arch/arm/dts/
H A Dast2400-u-boot.dtsi9 reg = <0x1e6e2000 0x1000>;
25 reg = <0x1e6e0000 0x174
26 0x1e6e0200 0x1d4 >;
H A Dast2500-u-boot.dtsi9 reg = <0x1e6e2000 0x1000>;
25 reg = <0x1e6e0000 0x174
26 0x1e6e0200 0x1d4 >;
H A Dast2600-u-boot.dtsi9 reg = <0x1e6e2000 0x1000>;
13 uart-clk-source = <0x0>; /* uart clock source selection: 0: uxclk 1: huxclk*/
26 reg = <0x1e6e0000 0x100
27 0x1e6e0100 0x300
28 0x1e6e0400 0x200 >;
/openbmc/u-boot/arch/arm/mach-aspeed/ast2600/
H A Dutils.S11 #define AST_SCU_BASE (0x1E6E2000)
12 #define AST_SCU_HW_STRAP1 (AST_SCU_BASE + 0x500)
13 #define AST_SCU_HW_STRAP2 (AST_SCU_BASE + 0x510)
15 #define AST_FMC_BASE (0x1E620000)
16 #define AST_FMC_INT_CTRL_STAT (AST_FMC_BASE + 0x008)
17 #define AST_FMC_DMA_CTRL (AST_FMC_BASE + 0x080)
18 #define AST_FMC_DMA_FLASH_ADDR (AST_FMC_BASE + 0x084)
19 #define AST_FMC_DMA_DRAM_ADDR (AST_FMC_BASE + 0x088)
20 #define AST_FMC_DMA_LENGTH (AST_FMC_BASE + 0x08C)
30 tst r0, #0x100
[all …]
H A Dspl.c16 #define AST_BOOTMODE_SPI 0
20 #define SCU_BASE 0x1e6e2000
21 #define SCU_SMP_SEC_ENTRY (SCU_BASE + 0x1bc)
22 #define SCU_WPROT2 (SCU_BASE + 0xf04)
34 uclass_get_device(UCLASS_PINCTRL, 0, &dev); in board_init_f()
74 spl_boot_list[0] = spl_boot_device(); in board_boot_order()
82 return 0; in spl_start_uboot()
108 return 0; in board_fit_config_name_match()
122 writel(0, 0x1e620064); in spl_boot_from_uart_wdt_disable()
123 writel(0, 0x1e6f20a0); in spl_boot_from_uart_wdt_disable()
H A Dboard_common.c33 #define PHY_RESET_MASK (BIT(GRP_F + 0) | BIT(GRP_F + 2)) in reset_eth_phy()
35 u32 value = readl(0x1e780020); in reset_eth_phy()
36 u32 direction = readl(0x1e780024); in reset_eth_phy()
42 writel(direction, 0x1e780024); in reset_eth_phy()
43 writel(value, 0x1e780020); in reset_eth_phy()
44 while((readl(0x1e780020) & PHY_RESET_MASK) != 0); in reset_eth_phy()
49 writel(value, 0x1e780020); in reset_eth_phy()
50 while((readl(0x1e780020) & PHY_RESET_MASK) != PHY_RESET_MASK); in reset_eth_phy()
66 if (rev_id == 0x0501030305010303 || rev_id == 0x0501020305010203) { in board_init()
68 tmp_val = readl(0x1e60008c) & (~BIT(0)); in board_init()
[all …]
H A Dplatform.S15 * +----------------------+ 0x40
17 * +----------------------+ 0x3c
22 * +----------------------+ 0x10
24 * +----------------------+ 0x0c
26 * +----------------------+ 0x08
28 * +----------------------+ 0x04
33 #define SCU_BASE 0x1e6e2000
35 #define SCU_PROT_KEY2 (SCU_BASE + 0x010)
36 #define SCU_REV_ID (SCU_BASE + 0x014)
37 #define SCU_SYSRST_CTRL (SCU_BASE + 0x040)
[all …]
/openbmc/u-boot/cmd/aspeed/nettest/
H A Dmem_io.h4 #define MAC1_BASE 0x1e660000
5 #define MAC2_BASE 0x1e680000
6 #define MDIO0_BASE (MAC1_BASE + 0x60)
7 #define MDIO1_BASE (MAC2_BASE + 0x60)
8 #define SCU_BASE 0x1e6e2000
12 #define MAC3_BASE 0x1e670000
13 #define MAC4_BASE 0x1e690000
15 #define PMI_BASE 0x1e650000
18 #define MDIO0_BASE (PMI_BASE + 0x00)
19 #define MDIO1_BASE (PMI_BASE + 0x08)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/misc/
H A Daspeed-p2a-ctrl.txt40 reg = <0x1e6e2000 0x1a8>;
/openbmc/linux/drivers/gpu/drm/ast/
H A Dast_dp501.c34 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff); in send_ack()
35 sendack |= 0x80; in send_ack()
36 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack); in send_ack()
42 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff); in send_nack()
43 sendack &= ~0x80; in send_nack()
44 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack); in send_nack()
50 u32 retry = 0; in wait_ack()
52 waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff); in wait_ack()
53 waitack &= 0x80; in wait_ack()
66 u32 retry = 0; in wait_nack()
[all …]
H A Dast_post.c40 static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
41 static const u8 extreginfo_ast2300[] = { 0x0f, 0x04, 0x1f, 0xff };
51 for (i = 0x81; i <= 0x9f; i++) in ast_set_def_ext_reg()
52 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00); in ast_set_def_ext_reg()
59 index = 0xa0; in ast_set_def_ext_reg()
60 while (*ext_reg_info != 0xff) { in ast_set_def_ext_reg()
61 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, index, 0x00, *ext_reg_info); in ast_set_def_ext_reg()
67 /* ast_set_index_reg-mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x3); */ in ast_set_def_ext_reg()
70 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x8c, 0x00, 0x01); in ast_set_def_ext_reg()
71 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x00, 0x00); in ast_set_def_ext_reg()
[all …]
/openbmc/u-boot/board/aspeed/evb_ast2600/
H A Devb_ast2600.c8 #define SCU_BASE 0x1e6e2000
9 #define ESPI_BASE 0x1e6ee000
10 #define LPC_BASE 0x1e789000
11 #define LPC_HICR5 (LPC_BASE + 0x80)
12 #define LPC_HICR6 (LPC_BASE + 0x84)
13 #define LPC_SNPWADR (LPC_BASE + 0x90)
14 #define LPC_HICRB (LPC_BASE + 0x100)
15 #define GPIO_BASE 0x1e780000
20 #define HICR5_SEL80HGIO (0x1f << 24) /* Select 80hGIO */
21 #define SET_SEL80HGIO(x) ((x & 0x1f) << 24) /* Select 80hGIO Offset */
[all …]
/openbmc/u-boot/board/aspeed/ast2600_dcscm/
H A Dast2600_dcscm.c8 #define SCU_BASE 0x1e6e2000
9 #define ESPI_BASE 0x1e6ee000
10 #define LPC_BASE 0x1e789000
11 #define LPC_HICR5 (LPC_BASE + 0x80)
12 #define LPC_HICR6 (LPC_BASE + 0x84)
13 #define LPC_SNPWADR (LPC_BASE + 0x90)
14 #define LPC_HICRB (LPC_BASE + 0x100)
15 #define GPIO_BASE 0x1e780000
20 #define HICR5_SEL80HGIO (0x1f << 24) /* Select 80hGIO */
21 #define SET_SEL80HGIO(x) ((x & 0x1f) << 24) /* Select 80hGIO Offset */
[all …]
/openbmc/u-boot/board/aspeed/ast2600_intel/
H A Dintel.c9 #define SCU_BASE 0x1e6e2000
10 #define SCU_PINMUX4 (SCU_BASE + 0x410)
12 #define SCU_PINMUX5 (SCU_BASE + 0x414)
17 #define SCU_GPIO_PD0 (SCU_BASE + 0x610)
19 #define SCU_PINMUX27 (SCU_BASE + 0x69c)
23 #define ESPI_BASE 0x1e6ee000
24 #define ESPI_CTRL (ESPI_BASE + 0x0)
25 #define ESPI_INT_EN (ESPI_BASE + 0xc)
26 #define ESPI_CTRL2 (ESPI_BASE + 0x80)
27 #define ESPI_SYSEVT_INT_EN (ESPI_BASE + 0x94)
[all …]
/openbmc/u-boot/cmd/aspeed/
H A Dpeci.c6 #define AST_SCU (0x1e6e2000)
8 #define AST_SCU_SYSRST_CTRL (AST_SCU + 0x04)
10 #define AST_SCU_SYSRST_CLR2 (AST_SCU + 0x54)
13 #define AST_PECI (0x1e78b000)
14 #define AST_PECI_CTRL (AST_PECI + 0x00)
15 #define AST_PECI_TIMING (AST_PECI + 0x04)
16 #define AST_PECI_CMD (AST_PECI + 0x08)
17 #define AST_PECI_RW_LEN (AST_PECI + 0x0C)
18 #define AST_PECI_EXP_FCS (AST_PECI + 0x10)
19 #define AST_PECI_CAP_FCS (AST_PECI + 0x14)
[all …]
/openbmc/qemu/hw/arm/
H A Daspeed_ast2400.c26 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
29 [ASPEED_DEV_SPI_BOOT] = 0x00000000,
30 [ASPEED_DEV_IOMEM] = 0x1E600000,
31 [ASPEED_DEV_FMC] = 0x1E620000,
32 [ASPEED_DEV_SPI1] = 0x1E630000,
33 [ASPEED_DEV_EHCI1] = 0x1E6A1000,
34 [ASPEED_DEV_UHCI] = 0x1E6B0000,
35 [ASPEED_DEV_VIC] = 0x1E6C0000,
36 [ASPEED_DEV_SDMC] = 0x1E6E0000,
37 [ASPEED_DEV_SCU] = 0x1E6E2000,
[all …]
/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-g4.dtsi36 #size-cells = <0>;
38 cpu@0 {
41 reg = <0>;
47 reg = <0x40000000 0>;
57 reg = <0x1e620000 0x94>, <0x20000000 0x10000000>;
59 #size-cells = <0>;
64 flash@0 {
65 reg = < 0 >;
102 reg = <0x1e630000 0x18>, <0x30000000 0x10000000>;
104 #size-cells = <0>;
[all …]
H A Daspeed-g6.dtsi48 #size-cells = <0>;
54 reg = <0xf00>;
60 reg = <0xf01>;
78 reg = <0x1e6e0000 0x174>;
79 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
95 reg = <0x40461000 0x1000>,
96 <0x40462000 0x1000>,
97 <0x40464000 0x2000>,
98 <0x40466000 0x2000>;
103 reg = <0x1e600000 0x100>;
[all …]
H A Daspeed-g5.dtsi37 #size-cells = <0>;
39 cpu@0 {
42 reg = <0>;
48 reg = <0x80000000 0>;
58 reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
60 #size-cells = <0>;
65 flash@0 {
66 reg = < 0 >;
89 reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>;
91 #size-cells = <0>;
[all …]

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