1d6e349c7Sryan_chen#include <dt-bindings/clock/ast2600-clock.h> 221fbb558Sryan_chen#include <dt-bindings/reset/ast2600-reset.h> 3b9553986Sryan_chen 4b9553986Sryan_chen#include "ast2600.dtsi" 5b9553986Sryan_chen 6b9553986Sryan_chen/ { 7b9553986Sryan_chen scu: clock-controller@1e6e2000 { 8b9553986Sryan_chen compatible = "aspeed,ast2600-scu"; 9b9553986Sryan_chen reg = <0x1e6e2000 0x1000>; 10b9553986Sryan_chen u-boot,dm-pre-reloc; 11b9553986Sryan_chen #clock-cells = <1>; 12b9553986Sryan_chen #reset-cells = <1>; 13*b55086a6SChia-Wei, Wang uart-clk-source = <0x0>; /* uart clock source selection: 0: uxclk 1: huxclk*/ 14b9553986Sryan_chen }; 15b9553986Sryan_chen 16b9553986Sryan_chen rst: reset-controller { 17b9553986Sryan_chen u-boot,dm-pre-reloc; 18b9553986Sryan_chen compatible = "aspeed,ast2600-reset"; 19b9553986Sryan_chen aspeed,wdt = <&wdt1>; 20b9553986Sryan_chen #reset-cells = <1>; 21b9553986Sryan_chen }; 22b9553986Sryan_chen 23b9553986Sryan_chen sdrammc: sdrammc@1e6e0000 { 24b9553986Sryan_chen u-boot,dm-pre-reloc; 25772d3539SDylan Hung compatible = "aspeed,ast2600-sdrammc"; 26772d3539SDylan Hung reg = <0x1e6e0000 0x100 27b4c00679SDylan Hung 0x1e6e0100 0x300 28b4c00679SDylan Hung 0x1e6e0400 0x200 >; 29b9553986Sryan_chen #reset-cells = <1>; 30f0d895afSryan_chen clocks = <&scu ASPEED_CLK_MPLL>; 3139283ea7Sryan_chen resets = <&rst ASPEED_RESET_SDRAM>; 32b9553986Sryan_chen }; 339c20f3d5SDylan Hung 34b9553986Sryan_chen ahb { 35b9553986Sryan_chen u-boot,dm-pre-reloc; 36b9553986Sryan_chen 37b9553986Sryan_chen apb { 38b9553986Sryan_chen u-boot,dm-pre-reloc; 39b9553986Sryan_chen }; 40b9553986Sryan_chen 41b9553986Sryan_chen }; 42b9553986Sryan_chen}; 43b9553986Sryan_chen 44