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/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp-mini-nand.dts27 memory@0 {
29 reg = <0x0 0x0 0x40000000>;
47 reg = <0x0 0xff100000 0x1000>;
54 partition@0 { /* for testing purpose */
56 reg = <0x0 0x0 0x400000>;
60 reg = <0x0 0x400000 0x1400000>;
64 reg = <0x0 0x1800000 0x400000>;
68 reg = <0x0 0x1C00000 0x1400000>;
72 reg = <0x0 0x3000000 0x400000>;
76 reg = <0x0 0x3400000 0xFCC00000>;
[all …]
H A Dzynqmp-zc1751-xm017-dc3.dts37 memory@0 {
39 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
79 phy0: phy@0 { /* VSC8211 */
80 reg = <0>;
95 reg = <0x20>;
103 reg = <0x68>;
119 partition@0 { /* for testing purpose */
121 reg = <0x0 0x0 0x400000>;
125 reg = <0x0 0x400000 0x1400000>;
129 reg = <0x0 0x1800000 0x400000>;
[all …]
H A Dzynqmp-zc1751-xm016-dc2.dts38 memory@0 {
40 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
90 ti,rx-internal-delay = <0x8>;
91 ti,tx-internal-delay = <0xa>;
92 ti,fifo-depth = <0x1>;
106 reg = <0x20>;
114 reg = <0x68>;
123 partition@0 { /* for testing purpose */
125 reg = <0x0 0x0 0x400000>;
129 reg = <0x0 0x400000 0x1400000>;
[all …]
H A Ddragonboard410c.dts16 qcom,msm-id = <0xce 0x0 0xf8 0x0 0xf9 0x0 0xfa 0x0 0xf7 0x0>;
17 qcom,board-id = <0x10018 0x0>;
18 #address-cells = <0x2>;
19 #size-cells = <0x2>;
27 reg = <0 0x80000000 0 0x3da00000>;
36 reg = <0x0 0x86300000 0x0 0x100000>;
52 #address-cells = <0x1>;
53 #size-cells = <0x1>;
54 ranges = <0x0 0x0 0x0 0xffffffff>;
59 reg = <0x60000 0x8000>;
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath10k/
H A Dahb.h34 #define ATH10K_GCC_REG_BASE 0x1800000
35 #define ATH10K_GCC_REG_SIZE 0x60000
37 #define ATH10K_TCSR_REG_BASE 0x1900000
38 #define ATH10K_TCSR_REG_SIZE 0x80000
40 #define ATH10K_AHB_GCC_FEPLL_PLL_DIV 0x2f020
41 #define ATH10K_AHB_WIFI_SCRATCH_5_REG 0x4f014
43 #define ATH10K_AHB_WLAN_CORE_ID_REG 0x82030
45 #define ATH10K_AHB_TCSR_WIFI0_GLB_CFG 0x49000
46 #define ATH10K_AHB_TCSR_WIFI1_GLB_CFG 0x49004
49 #define ATH10K_AHB_TCSR_WCSS0_HALTREQ 0x52000
[all …]
/openbmc/u-boot/include/configs/
H A Dstih410-b2260.h13 #define PHYS_SDRAM_1 0x40000000
15 #define PHYS_SDRAM_1_SIZE 0x3E000000
26 func(MMC, mmc, 0) \
27 func(USB, usb, 0) \
32 "kernel_addr_r=0x40000000\0" \
33 "fdtfile=stih410-b2260.dtb\0" \
34 "fdt_addr_r=0x47000000\0" \
35 "scriptaddr=0x50000000\0" \
36 "pxefile_addr_r=0x50100000\0" \
37 "fdt_high=0xffffffffffffffff\0" \
[all …]
H A Dvexpress_common.h20 #define V2M_PA_CS0 0x40000000
21 #define V2M_PA_CS1 0x44000000
22 #define V2M_PA_CS2 0x48000000
23 #define V2M_PA_CS3 0x4c000000
24 #define V2M_PA_CS7 0x10000000
27 #define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(0))
31 #define V2M_BASE 0x60000000
34 #define V2M_PA_CS0 0x08000000
35 #define V2M_PA_CS1 0x0c000000
36 #define V2M_PA_CS2 0x14000000
[all …]
H A Dthunderx_88xx.h15 #define MEM_BASE 0x00500000
20 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
23 #define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
26 #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
39 #define GICD_BASE (0x801000000000)
40 #define GICR_BASE (0x801000002000)
41 #define CONFIG_SYS_SERIAL0 0x87e024000000
42 #define CONFIG_SYS_SERIAL1 0x87e025000000
52 #define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */
56 #define UBOOT_IMG_HEAD_SIZE 0x40
[all …]
H A Dclearfog.h41 #define CONFIG_SYS_MMC_ENV_DEV 0
42 #define CONFIG_ENV_SECT_SIZE 0x200
43 #define CONFIG_ENV_SIZE 0x10000
46 * boot image starts @ LBA-0.
50 #define CONFIG_ENV_OFFSET 0xf0000
71 "fdt_high=0x10000000\0" \
72 "initrd_high=0x10000000\0"
78 #define CONFIG_SPL_TEXT_BASE 0x40000030
79 #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
81 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
[all …]
H A Dturris_omnia.h71 "fdt_high=0x10000000\0" \
72 "initrd_high=0x10000000\0"
76 #define CONFIG_SPL_TEXT_BASE 0x40000030
77 #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
79 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
86 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
92 # define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
101 # define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
115 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
121 #define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
[all …]
H A Dhelios4.h56 #define CONFIG_SYS_MMC_ENV_DEV 0
57 #define CONFIG_ENV_SECT_SIZE 0x200
58 #define CONFIG_ENV_SIZE 0x2000
69 "fdt_high=0x10000000\0" \
70 "initrd_high=0x10000000\0"
92 #define CONFIG_SPL_TEXT_BASE 0x40000030
93 #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
95 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
102 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
110 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x30000
[all …]
H A Dxilinx_zynqmp.h19 #define GICD_BASE 0xF9010000
20 #define GICC_BASE 0xF9020000
23 # define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
26 #define CONFIG_SYS_MEMTEST_START 0
37 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x2000000)
64 #define CONFIG_SYS_LOAD_ADDR 0x8000000
67 #define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x1800000
75 "system.dtb ram $fdt_addr $fdt_size\0" \
76 "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
77 "thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
[all …]
H A Dvexpress_aemv8a.h23 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
25 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
31 #define V2M_PA_CS0 0x00000000
32 #define V2M_PA_CS1 0x14000000
33 #define V2M_PA_CS2 0x18000000
34 #define V2M_PA_CS3 0x1c000000
35 #define V2M_PA_CS4 0x0c000000
36 #define V2M_PA_CS5 0x10000000
43 #define V2M_BASE 0x80000000
52 #define V2M_UART0 0x7ff80000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,gcc-ipq4019.yaml46 reg = <0x1800000 0x60000>;
H A Dqcom,gcc-msm8976.yaml65 reg = <0x1800000 0x80000>;
70 <&dsi0_phy 0>,
72 <&dsi1_phy 0>;
/openbmc/linux/arch/arm/mach-versatile/
H A Dintegrator-hardware.h14 #define IO_BASE 0xF0000000 // VA of IO
15 #define IO_SIZE 0x0B000000 // How much?
19 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
25 #define INTEGRATOR_BOOT_ROM_LO 0x00000000
26 #define INTEGRATOR_BOOT_ROM_HI 0x20000000
40 #define INTEGRATOR_SSRAM_BASE 0x00000000
41 #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
44 #define INTEGRATOR_FLASH_BASE 0x24000000
47 #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
53 #define INTEGRATOR_SDRAM_BASE 0x00040000
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood-topkick.dts13 reg = <0x00000000 0x10000000>;
34 pinctrl-0 = <&pmx_sw_left &pmx_sw_right
103 pinctrl-0 = <&pmx_sdio>;
125 pinctrl-0 = <&pmx_led_disk_yellow &pmx_led_sys_red
156 #size-cells = <0>;
157 pinctrl-0 = <&pmx_sata0_pwr_enable>;
169 gpio = <&gpio1 4 0>;
177 partition@0 {
179 reg = <0x0000000 0x180000>;
184 reg = <0x0180000 0x20000>;
[all …]
H A Dkirkwood-netgear_readynas_duo_v2.dts19 reg = <0x00000000 0x10000000>;
78 #clock-cells = <0>;
88 reg = <0x32>;
93 reg = <0x3e>;
95 fan_gear_mode = <0>;
97 pwm_polarity = <0>;
113 pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_activity
147 pinctrl-0 = <&pmx_button_power &pmx_button_backup
172 pinctrl-0 = <&pmx_poweroff>;
180 #size-cells = <0>;
[all …]
H A Dkirkwood-netgear_readynas_nv+_v2.dts19 reg = <0x00000000 0x10000000>;
83 #clock-cells = <0>;
93 reg = <0x32>;
98 reg = <0x3e>;
100 fan_gear_mode = <0>;
102 pwm_polarity = <0>;
132 pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_backup
171 pinctrl-0 = <&pmx_button_power &pmx_button_backup
196 pinctrl-0 = <&pmx_poweroff>;
204 #size-cells = <0>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmscc,vsc7514-switch.yaml38 "^port@[0-9a-f]+$":
55 "^port@[0-9a-f]+$":
142 reg = <0x1010000 0x10000>,
143 <0x1030000 0x10000>,
144 <0x1080000 0x100>,
145 <0x10e0000 0x10000>,
146 <0x11e0000 0x100>,
147 <0x11f0000 0x100>,
148 <0x1200000 0x100>,
149 <0x1210000 0x100>,
[all …]
/openbmc/linux/arch/mips/boot/dts/mscc/
H A Docelot.dtsi11 #size-cells = <0>;
13 cpu@0 {
17 reg = <0>;
26 #address-cells = <0>;
34 #clock-cells = <0>;
40 #clock-cells = <0>;
50 ranges = <0 0x70000000 0x2000000>;
54 cpu_ctrl: syscon@0 {
56 reg = <0x0 0x2c>;
61 reg = <0x70 0x70>;
[all …]
/openbmc/u-boot/arch/mips/dts/
H A Dmscc,ocelot.dtsi13 #size-cells = <0>;
15 cpu@0 {
19 reg = <0>;
27 cpuintc: interrupt-controller@0 {
28 #address-cells = <0>;
36 #clock-cells = <0>;
42 #clock-cells = <0>;
48 #clock-cells = <0>;
56 ranges = <0 0x70000000 0x2000000>;
60 cpu_ctrl: syscon@0 {
[all …]
/openbmc/qemu/hw/arm/
H A Dbcm2838_peripherals.c15 #define CLOCK_ISP_OFFSET 0xc11000
16 #define CLOCK_ISP_SIZE 0x100
19 #define BCM2838_VC_PERI_LOW_BASE 0x7c000000
22 #define BCM2835_SDHC_CAPAREG 0x52134b4
76 "bcm2838-peripherals", &s->peri_low_mr, 0, in bcm2838_peripherals_realize()
95 0)); in bcm2838_peripherals_realize()
103 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc2), 0, in bcm2838_peripherals_realize()
104 qdev_get_gpio_in(mmc_irq_orgate, 0)); in bcm2838_peripherals_realize()
106 sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->sdhci), 0, in bcm2838_peripherals_realize()
110 qdev_connect_gpio_out(mmc_irq_orgate, 0, in bcm2838_peripherals_realize()
[all …]
/openbmc/qemu/hw/ppc/
H A Dppc440_bamboo.c41 #define KERNEL_ADDR 0x1000000
42 #define FDT_ADDR 0x1800000
43 #define RAMDISK_ADDR 0x1900000
45 #define PPC440EP_PCI_CONFIG 0xeec00000
46 #define PPC440EP_PCI_INTACK 0xeed00000
47 #define PPC440EP_PCI_SPECIAL 0xeed00000
48 #define PPC440EP_PCI_REGS 0xef400000
49 #define PPC440EP_PCI_IO 0xe8000000
50 #define PPC440EP_PCI_IOLEN 0x00010000
60 uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(machine->ram_size) }; in bamboo_load_device_tree()
[all …]
/openbmc/linux/drivers/media/dvb-frontends/
H A Ddrxd_map_firm.h18 #define HI_COMM_EXEC__A 0x400000
19 #define HI_COMM_MB__A 0x400002
20 #define HI_CT_REG_COMM_STATE__A 0x410001
21 #define HI_RA_RAM_SRV_RES__A 0x420031
22 #define HI_RA_RAM_SRV_CMD__A 0x420032
23 #define HI_RA_RAM_SRV_CMD_RESET 0x2
24 #define HI_RA_RAM_SRV_CMD_CONFIG 0x3
25 #define HI_RA_RAM_SRV_CMD_EXECUTE 0x6
26 #define HI_RA_RAM_SRV_RST_KEY__A 0x420033
27 #define HI_RA_RAM_SRV_RST_KEY_ACT 0x3973
[all …]

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