1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2746f985aSSergey Temerkhanov /** 3746f985aSSergey Temerkhanov * (C) Copyright 2014, Cavium Inc. 4746f985aSSergey Temerkhanov **/ 5746f985aSSergey Temerkhanov 6746f985aSSergey Temerkhanov #ifndef __THUNDERX_88XX_H__ 7746f985aSSergey Temerkhanov #define __THUNDERX_88XX_H__ 8746f985aSSergey Temerkhanov 9746f985aSSergey Temerkhanov #define CONFIG_REMAKE_ELF 10746f985aSSergey Temerkhanov 11746f985aSSergey Temerkhanov #define CONFIG_THUNDERX 12746f985aSSergey Temerkhanov 13746f985aSSergey Temerkhanov #define CONFIG_SYS_64BIT 14746f985aSSergey Temerkhanov 15746f985aSSergey Temerkhanov #define MEM_BASE 0x00500000 16746f985aSSergey Temerkhanov 17900f88f3SSergey Temerkhanov #define CONFIG_SYS_LOWMEM_BASE MEM_BASE 18900f88f3SSergey Temerkhanov 19746f985aSSergey Temerkhanov /* Link Definitions */ 20746f985aSSergey Temerkhanov #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) 21746f985aSSergey Temerkhanov 22746f985aSSergey Temerkhanov /* SMP Spin Table Definitions */ 23746f985aSSergey Temerkhanov #define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) 24746f985aSSergey Temerkhanov 25746f985aSSergey Temerkhanov /* Generic Timer Definitions */ 26746f985aSSergey Temerkhanov #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ 27746f985aSSergey Temerkhanov 28746f985aSSergey Temerkhanov #define CONFIG_SYS_MEMTEST_START MEM_BASE 29746f985aSSergey Temerkhanov #define CONFIG_SYS_MEMTEST_END (MEM_BASE + PHYS_SDRAM_1_SIZE) 30746f985aSSergey Temerkhanov 31746f985aSSergey Temerkhanov /* Size of malloc() pool */ 32746f985aSSergey Temerkhanov #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 33746f985aSSergey Temerkhanov 34746f985aSSergey Temerkhanov /* PL011 Serial Configuration */ 35746f985aSSergey Temerkhanov 36746f985aSSergey Temerkhanov #define CONFIG_PL011_CLOCK 24000000 37746f985aSSergey Temerkhanov 38746f985aSSergey Temerkhanov /* Generic Interrupt Controller Definitions */ 39746f985aSSergey Temerkhanov #define GICD_BASE (0x801000000000) 40746f985aSSergey Temerkhanov #define GICR_BASE (0x801000002000) 41746f985aSSergey Temerkhanov #define CONFIG_SYS_SERIAL0 0x87e024000000 42746f985aSSergey Temerkhanov #define CONFIG_SYS_SERIAL1 0x87e025000000 43746f985aSSergey Temerkhanov 44746f985aSSergey Temerkhanov /* BOOTP options */ 45746f985aSSergey Temerkhanov #define CONFIG_BOOTP_BOOTFILESIZE 46746f985aSSergey Temerkhanov 47746f985aSSergey Temerkhanov /* Miscellaneous configurable options */ 48746f985aSSergey Temerkhanov #define CONFIG_SYS_LOAD_ADDR (MEM_BASE) 49746f985aSSergey Temerkhanov 50746f985aSSergey Temerkhanov /* Physical Memory Map */ 51746f985aSSergey Temerkhanov #define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */ 52746f985aSSergey Temerkhanov #define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */ 53746f985aSSergey Temerkhanov #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 54746f985aSSergey Temerkhanov 55746f985aSSergey Temerkhanov /* Initial environment variables */ 56746f985aSSergey Temerkhanov #define UBOOT_IMG_HEAD_SIZE 0x40 57746f985aSSergey Temerkhanov /* C80000 - 0x40 */ 58746f985aSSergey Temerkhanov #define CONFIG_EXTRA_ENV_SETTINGS \ 59746f985aSSergey Temerkhanov "kernel_addr=08007ffc0\0" \ 60746f985aSSergey Temerkhanov "fdt_addr=0x94C00000\0" \ 61746f985aSSergey Temerkhanov "fdt_high=0x9fffffff\0" 62746f985aSSergey Temerkhanov 63746f985aSSergey Temerkhanov /* Do not preserve environment */ 64746f985aSSergey Temerkhanov #define CONFIG_ENV_SIZE 0x1000 65746f985aSSergey Temerkhanov 66746f985aSSergey Temerkhanov /* Monitor Command Prompt */ 67746f985aSSergey Temerkhanov #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 68746f985aSSergey Temerkhanov #define CONFIG_SYS_MAXARGS 64 /* max command args */ 69746f985aSSergey Temerkhanov #define CONFIG_NO_RELOCATION 1 70746f985aSSergey Temerkhanov #define PLL_REF_CLK 50000000 /* 50 MHz */ 71746f985aSSergey Temerkhanov #define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK) 72746f985aSSergey Temerkhanov 73746f985aSSergey Temerkhanov #endif /* __THUNDERX_88XX_H__ */ 74