xref: /openbmc/linux/drivers/net/wireless/ath/ath10k/ahb.h (revision f0553ca9)
1f0553ca9SKalle Valo /* SPDX-License-Identifier: ISC */
20b523cedSRaja Mani /*
30b523cedSRaja Mani  * Copyright (c) 2016 Qualcomm Atheros, Inc. All rights reserved.
40b523cedSRaja Mani  * Copyright (c) 2015 The Linux Foundation. All rights reserved.
50b523cedSRaja Mani  */
60b523cedSRaja Mani 
70b523cedSRaja Mani #ifndef _AHB_H_
80b523cedSRaja Mani #define _AHB_H_
90b523cedSRaja Mani 
100b523cedSRaja Mani #include <linux/platform_device.h>
110b523cedSRaja Mani 
127f8e79cdSRaja Mani struct ath10k_ahb {
137f8e79cdSRaja Mani 	struct platform_device *pdev;
147f8e79cdSRaja Mani 	void __iomem *mem;
15704dc4e3SRaja Mani 	unsigned long mem_len;
167f8e79cdSRaja Mani 	void __iomem *gcc_mem;
177f8e79cdSRaja Mani 	void __iomem *tcsr_mem;
188beff219SRaja Mani 
191c44fcb9SRaja Mani 	int irq;
201c44fcb9SRaja Mani 
218beff219SRaja Mani 	struct clk *cmd_clk;
228beff219SRaja Mani 	struct clk *ref_clk;
238beff219SRaja Mani 	struct clk *rtc_clk;
2414854bfdSRaja Mani 
2514854bfdSRaja Mani 	struct reset_control *core_cold_rst;
2614854bfdSRaja Mani 	struct reset_control *radio_cold_rst;
2714854bfdSRaja Mani 	struct reset_control *radio_warm_rst;
2814854bfdSRaja Mani 	struct reset_control *radio_srif_rst;
2914854bfdSRaja Mani 	struct reset_control *cpu_init_rst;
307f8e79cdSRaja Mani };
317f8e79cdSRaja Mani 
320b523cedSRaja Mani #ifdef CONFIG_ATH10K_AHB
330b523cedSRaja Mani 
34704dc4e3SRaja Mani #define ATH10K_GCC_REG_BASE                  0x1800000
35704dc4e3SRaja Mani #define ATH10K_GCC_REG_SIZE                  0x60000
36704dc4e3SRaja Mani 
37704dc4e3SRaja Mani #define ATH10K_TCSR_REG_BASE                 0x1900000
38704dc4e3SRaja Mani #define ATH10K_TCSR_REG_SIZE                 0x80000
39704dc4e3SRaja Mani 
400d87c920SRaja Mani #define ATH10K_AHB_GCC_FEPLL_PLL_DIV         0x2f020
410d87c920SRaja Mani #define ATH10K_AHB_WIFI_SCRATCH_5_REG        0x4f014
420d87c920SRaja Mani 
43133df0f8SRaja Mani #define ATH10K_AHB_WLAN_CORE_ID_REG          0x82030
44133df0f8SRaja Mani 
45133df0f8SRaja Mani #define ATH10K_AHB_TCSR_WIFI0_GLB_CFG        0x49000
46133df0f8SRaja Mani #define ATH10K_AHB_TCSR_WIFI1_GLB_CFG        0x49004
47133df0f8SRaja Mani #define TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK  BIT(25)
48133df0f8SRaja Mani 
49133df0f8SRaja Mani #define ATH10K_AHB_TCSR_WCSS0_HALTREQ        0x52000
50133df0f8SRaja Mani #define ATH10K_AHB_TCSR_WCSS1_HALTREQ        0x52010
51133df0f8SRaja Mani #define ATH10K_AHB_TCSR_WCSS0_HALTACK        0x52004
52133df0f8SRaja Mani #define ATH10K_AHB_TCSR_WCSS1_HALTACK        0x52014
53133df0f8SRaja Mani 
54133df0f8SRaja Mani #define ATH10K_AHB_AXI_BUS_HALT_TIMEOUT      10 /* msec */
55133df0f8SRaja Mani #define AHB_AXI_BUS_HALT_REQ                 1
56133df0f8SRaja Mani #define AHB_AXI_BUS_HALT_ACK                 1
57133df0f8SRaja Mani 
580d87c920SRaja Mani #define ATH10K_AHB_CORE_CTRL_CPU_INTR_MASK   1
590d87c920SRaja Mani 
600b523cedSRaja Mani int ath10k_ahb_init(void);
610b523cedSRaja Mani void ath10k_ahb_exit(void);
620b523cedSRaja Mani 
630b523cedSRaja Mani #else /* CONFIG_ATH10K_AHB */
640b523cedSRaja Mani 
ath10k_ahb_init(void)650b523cedSRaja Mani static inline int ath10k_ahb_init(void)
660b523cedSRaja Mani {
670b523cedSRaja Mani 	return 0;
680b523cedSRaja Mani }
690b523cedSRaja Mani 
ath10k_ahb_exit(void)700b523cedSRaja Mani static inline void ath10k_ahb_exit(void)
710b523cedSRaja Mani {
720b523cedSRaja Mani }
730b523cedSRaja Mani 
740b523cedSRaja Mani #endif /* CONFIG_ATH10K_AHB */
750b523cedSRaja Mani 
760b523cedSRaja Mani #endif /* _AHB_H_ */
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