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/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dmediatek,vcodec-subdev-decoder.yaml92 '^video-codec@[0-9a-f]+$':
209 ranges = <0 0x16000000 0x16000000 0 0x40000>;
217 ranges = <0 0 0 0x16000000 0 0x40000>;
218 reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */
221 reg = <0 0x10000 0 0x800>;
222 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
244 reg = <0 0x25000 0 0x1000>;
245 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
/openbmc/u-boot/arch/mips/dts/
H A Dimg,boston.dts19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0>;
29 memory@0 {
31 reg = <0x00000000 0x10000000>;
51 reg = <0x10000000 0x2000000>;
60 ranges = <0x02000000 0 0x40000000
61 0x40000000 0 0x40000000>;
63 interrupt-map-mask = <0 0 0 7>;
64 interrupt-map = <0 0 0 1 &pci0_intc 0>,
[all …]
H A Djz4780.dtsi11 #address-cells = <0>;
19 reg = <0x10001000 0x50>;
30 #clock-cells = <0>;
35 #clock-cells = <0>;
41 reg = <0x10000000 0x100>;
51 reg = <0x13450000 0x1000>;
61 reg = <0x13460000 0x1000>;
71 reg = <0x10030000 0x100>;
85 reg = <0x10031000 0x100>;
99 reg = <0x10032000 0x100>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/mediatek/
H A Dmediatek,vdecsys.txt27 reg = <0 0x16000000 0 0x1000>;
H A Dmediatek,mt8195-clock.yaml68 reg = <0x10720000 0x1000>;
75 reg = <0x11d03000 0x1000>;
82 reg = <0x11e05000 0x1000>;
89 reg = <0x13fbf000 0x1000>;
96 reg = <0x14e00000 0x1000>;
103 reg = <0x14e02000 0x1000>;
110 reg = <0x14e03000 0x1000>;
117 reg = <0x15000000 0x1000>;
124 reg = <0x15110000 0x1000>;
131 reg = <0x15130000 0x1000>;
[all …]
/openbmc/linux/arch/mips/boot/dts/img/
H A Dboston.dts24 #size-cells = <0>;
26 cpu@0 {
29 reg = <0>;
34 memory@0 {
36 reg = <0x00000000 0x10000000>;
42 reg = <0x10000000 0x2000000>;
51 ranges = <0x02000000 0 0x40000000
52 0x40000000 0 0x40000000>;
54 bus-range = <0x00 0xff>;
56 interrupt-map-mask = <0 0 0 7>;
[all …]
/openbmc/linux/drivers/input/serio/
H A Di8042-snirm.h26 #define I8042_COMMAND_REG (kbd_iobase + 0x64UL)
27 #define I8042_DATA_REG (kbd_iobase + 0x60UL)
31 return readb(kbd_iobase + 0x60UL); in i8042_read_data()
36 return readb(kbd_iobase + 0x64UL); in i8042_read_status()
41 writeb(val, kbd_iobase + 0x60UL); in i8042_write_data()
46 writeb(val, kbd_iobase + 0x64UL); in i8042_write_command()
52 kbd_iobase = ioremap(0x16000000, 4); in i8042_platform_init()
56 kbd_iobase = ioremap(0x14000000, 4); in i8042_platform_init()
63 return 0; in i8042_platform_init()
/openbmc/qemu/include/hw/pci-host/
H A Dls7a.h16 #define VIRT_PCI_MEM_BASE 0x40000000UL
17 #define VIRT_PCI_MEM_SIZE 0x40000000UL
18 #define VIRT_PCI_IO_OFFSET 0x4000
19 #define VIRT_PCI_CFG_BASE 0x20000000
20 #define VIRT_PCI_CFG_SIZE 0x08000000
21 #define VIRT_PCI_IO_BASE 0x18004000UL
22 #define VIRT_PCI_IO_SIZE 0xC000
24 #define VIRT_PCH_REG_BASE 0x10000000UL
26 #define VIRT_PCH_MSI_ADDR_LOW 0x2FF00000UL
27 #define VIRT_PCH_REG_SIZE 0x400
[all …]
/openbmc/linux/Documentation/devicetree/bindings/crypto/
H A Dstarfive,jh7110-crypto.yaml61 reg = <0x16000000 0x4000>;
67 <&dma 0 2>;
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dmediatek,mt6795-clock.yaml51 reg = <0 0x13000000 0 0x1000>;
57 reg = <0 0x16000000 0 0x1000>;
63 reg = <0 0x18000000 0 0x1000>;
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dingenic,nemc.yaml14 pattern: "^memory-controller@[0-9a-f]+$"
40 ".*@[0-9]+$":
60 reg = <0x13410000 0x10000>;
63 ranges = <1 0 0x1b000000 0x1000000>,
64 <2 0 0x1a000000 0x1000000>,
65 <3 0 0x19000000 0x1000000>,
66 <4 0 0x18000000 0x1000000>,
67 <5 0 0x17000000 0x1000000>,
68 <6 0 0x16000000 0x1000000>;
77 pinctrl-0 = <&pins_nemc_cs6>;
[all …]
/openbmc/linux/arch/mips/include/asm/txx9/
H A Drbtx4927.h32 #define RBTX4927_PCIMEM 0x08000000
33 #define RBTX4927_PCIMEM_SIZE 0x08000000
34 #define RBTX4927_PCIIO 0x16000000
35 #define RBTX4927_PCIIO_SIZE 0x01000000
37 #define RBTX4927_LED_ADDR (IO_BASE + TXX9_CE(2) + 0x00001000)
38 #define RBTX4927_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000)
39 #define RBTX4927_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006)
40 #define RBTX4927_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000)
41 #define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000)
42 #define RBTX4927_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f002)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dingenic,nand.yaml66 reg = <0x13410000 0x10000>;
69 ranges = <1 0 0x1b000000 0x1000000>,
70 <2 0 0x1a000000 0x1000000>,
71 <3 0 0x19000000 0x1000000>,
72 <4 0 0x18000000 0x1000000>,
73 <5 0 0x17000000 0x1000000>,
74 <6 0 0x16000000 0x1000000>;
80 reg = <1 0 0x1000000>;
83 #size-cells = <0>;
94 pinctrl-0 = <&pins_nemc>;
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dintegrator.dtsi12 reg = <0x0 0x0>;
17 reg = <0x10000000 0x200>;
18 ranges = <0x0 0x10000000 0x200>;
23 led@c,0 {
25 reg = <0x0c 0x04>;
26 offset = <0x0c>;
27 mask = <0x01>;
36 reg = <0x12000000 0x100>;
40 reg = <0x13000000 0x100>;
46 reg = <0x13000100 0x100>;
[all …]
/openbmc/linux/arch/sh/boards/mach-se/7343/
H A Dsetup.c32 .offset = 0x00000000,
54 [0] = {
55 .start = 0x00000000,
56 .end = 0x01ffffff,
73 [0] = {
75 .mapbase = 0x16000000,
82 .mapbase = 0x17000000,
104 [0] = {
105 .start = 0x11800000,
106 .end = 0x11800001,
[all …]
/openbmc/u-boot/board/armltd/integrator/
H A Dintegrator.c31 .base = 0x16000000,
37 .clock = 0, /* Not used for PL010 */
55 #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
73 gd->bd->bi_boot_params = 0x00000100; in board_init()
77 cm_remap(); /* remaps writeable memory to 0x00000000 */ in board_init()
102 writel(0, EBI_BASE + EBI_LOCK_REG); in board_init()
113 return 0; in board_init()
119 return (0); in misc_init_r()
123 * The Integrator remaps the Flash memory to 0x00000000 and executes U-Boot
129 #define REMAPPED_FLASH_SZ 0x40000
[all …]
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8167.dtsi22 reg = <0 0x10000000 0 0x1000>;
28 reg = <0 0x10001000 0 0x1000>;
34 reg = <0 0x10018000 0 0x710>;
40 reg = <0 0x10006000 0 0x1000>;
45 #size-cells = <0>;
53 #power-domain-cells = <0>;
62 #power-domain-cells = <0>;
69 #power-domain-cells = <0>;
78 #size-cells = <0>;
85 #size-cells = <0>;
[all …]
H A Dmt6779.dtsi26 #size-cells = <0>;
28 cpu0: cpu@0 {
32 reg = <0x000>;
39 reg = <0x100>;
46 reg = <0x200>;
53 reg = <0x300>;
60 reg = <0x400>;
67 reg = <0x500>;
74 reg = <0x600>;
81 reg = <0x700>;
[all …]
H A Dmt6797.dtsi25 #size-cells = <0>;
27 cpu0: cpu@0 {
31 reg = <0x000>;
38 reg = <0x001>;
45 reg = <0x002>;
52 reg = <0x003>;
59 reg = <0x100>;
66 reg = <0x101>;
73 reg = <0x102>;
80 reg = <0x103>;
[all …]
/openbmc/u-boot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h22 #define AR71XX_APB_BASE 0x18000000
23 #define AR71XX_GE0_BASE 0x19000000
24 #define AR71XX_GE0_SIZE 0x10000
25 #define AR71XX_GE1_BASE 0x1a000000
26 #define AR71XX_GE1_SIZE 0x10000
27 #define AR71XX_EHCI_BASE 0x1b000000
28 #define AR71XX_EHCI_SIZE 0x1000
29 #define AR71XX_OHCI_BASE 0x1c000000
30 #define AR71XX_OHCI_SIZE 0x1000
31 #define AR71XX_SPI_BASE 0x1f000000
[all …]
/openbmc/linux/arch/mips/include/asm/mach-ath79/
H A Dar71xx_regs.h19 #define AR71XX_APB_BASE 0x18000000
20 #define AR71XX_GE0_BASE 0x19000000
21 #define AR71XX_GE0_SIZE 0x10000
22 #define AR71XX_GE1_BASE 0x1a000000
23 #define AR71XX_GE1_SIZE 0x10000
24 #define AR71XX_EHCI_BASE 0x1b000000
25 #define AR71XX_EHCI_SIZE 0x1000
26 #define AR71XX_OHCI_BASE 0x1c000000
27 #define AR71XX_OHCI_SIZE 0x1000
28 #define AR71XX_SPI_BASE 0x1f000000
[all …]
/openbmc/linux/arch/arm/mach-versatile/
H A Dintegrator-hardware.h14 #define IO_BASE 0xF0000000 // VA of IO
15 #define IO_SIZE 0x0B000000 // How much?
19 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
25 #define INTEGRATOR_BOOT_ROM_LO 0x00000000
26 #define INTEGRATOR_BOOT_ROM_HI 0x20000000
40 #define INTEGRATOR_SSRAM_BASE 0x00000000
41 #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
44 #define INTEGRATOR_FLASH_BASE 0x24000000
47 #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
53 #define INTEGRATOR_SDRAM_BASE 0x00040000
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx1.dtsi38 reg = <0x00223000 0x1000>;
42 #size-cells = <0>;
45 cpu@0 {
47 reg = <0>;
59 #clock-cells = <0>;
75 reg = <0x00200000 0x10000>;
80 reg = <0x00202000 0x1000>;
89 reg = <0x00203000 0x1000>;
98 reg = <0x00205000 0x1000>;
109 reg = <0x00206000 0x1000>;
[all …]
/openbmc/linux/fs/freevxfs/
H A Dvxfs.h20 #define VXFS_SUPER_MAGIC 0xa501FCF5
176 * File modes. File types above 0xf000 are vxfs internal only, they should
181 VXFS_ISUID = 0x00000800, /* setuid */
182 VXFS_ISGID = 0x00000400, /* setgid */
183 VXFS_ISVTX = 0x00000200, /* sticky bit */
184 VXFS_IREAD = 0x00000100, /* read */
185 VXFS_IWRITE = 0x00000080, /* write */
186 VXFS_IEXEC = 0x00000040, /* exec */
188 VXFS_IFIFO = 0x00001000, /* Named pipe */
189 VXFS_IFCHR = 0x00002000, /* Character device */
[all …]
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8960.dtsi20 #size-cells = <0>;
21 interrupts = <GIC_PPI 14 0x304>;
23 cpu@0 {
27 reg = <0>;
52 reg = <0x0 0x0>;
57 interrupts = <GIC_PPI 10 0x304>;
64 #clock-cells = <0>;
71 #clock-cells = <0>;
78 #clock-cells = <0>;
103 reg = <0x02000000 0x1000>,
[all …]

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