1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2576afd4fSJean-Christophe PLAGNIOL-VILLARD /*
3576afd4fSJean-Christophe PLAGNIOL-VILLARD * (C) Copyright 2002
4576afd4fSJean-Christophe PLAGNIOL-VILLARD * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
5576afd4fSJean-Christophe PLAGNIOL-VILLARD * Marius Groeger <mgroeger@sysgo.de>
6576afd4fSJean-Christophe PLAGNIOL-VILLARD *
7576afd4fSJean-Christophe PLAGNIOL-VILLARD * (C) Copyright 2002
8576afd4fSJean-Christophe PLAGNIOL-VILLARD * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
9576afd4fSJean-Christophe PLAGNIOL-VILLARD *
10576afd4fSJean-Christophe PLAGNIOL-VILLARD * (C) Copyright 2003
11576afd4fSJean-Christophe PLAGNIOL-VILLARD * Texas Instruments, <www.ti.com>
12576afd4fSJean-Christophe PLAGNIOL-VILLARD * Kshitij Gupta <Kshitij@ti.com>
13576afd4fSJean-Christophe PLAGNIOL-VILLARD *
14576afd4fSJean-Christophe PLAGNIOL-VILLARD * (C) Copyright 2004
15576afd4fSJean-Christophe PLAGNIOL-VILLARD * ARM Ltd.
16576afd4fSJean-Christophe PLAGNIOL-VILLARD * Philippe Robin, <philippe.robin@arm.com>
17576afd4fSJean-Christophe PLAGNIOL-VILLARD */
18576afd4fSJean-Christophe PLAGNIOL-VILLARD
19576afd4fSJean-Christophe PLAGNIOL-VILLARD #include <common.h>
209d922450SSimon Glass #include <dm.h>
21576afd4fSJean-Christophe PLAGNIOL-VILLARD #include <netdev.h>
227c045d0bSLinus Walleij #include <asm/io.h>
233f394e70SLinus Walleij #include <dm/platform_data/serial_pl01x.h>
24701ed16eSLinus Walleij #include "arm-ebi.h"
251dc26801SLinus Walleij #include "integrator-sc.h"
26c62db35dSSimon Glass #include <asm/mach-types.h>
27576afd4fSJean-Christophe PLAGNIOL-VILLARD
28576afd4fSJean-Christophe PLAGNIOL-VILLARD DECLARE_GLOBAL_DATA_PTR;
29576afd4fSJean-Christophe PLAGNIOL-VILLARD
303f394e70SLinus Walleij static const struct pl01x_serial_platdata serial_platdata = {
313f394e70SLinus Walleij .base = 0x16000000,
323f394e70SLinus Walleij #ifdef CONFIG_ARCH_CINTEGRATOR
333f394e70SLinus Walleij .type = TYPE_PL011,
343f394e70SLinus Walleij .clock = 14745600,
353f394e70SLinus Walleij #else
363f394e70SLinus Walleij .type = TYPE_PL010,
373f394e70SLinus Walleij .clock = 0, /* Not used for PL010 */
383f394e70SLinus Walleij #endif
393f394e70SLinus Walleij };
403f394e70SLinus Walleij
413f394e70SLinus Walleij U_BOOT_DEVICE(integrator_serials) = {
423f394e70SLinus Walleij .name = "serial_pl01x",
433f394e70SLinus Walleij .platdata = &serial_platdata,
443f394e70SLinus Walleij };
453f394e70SLinus Walleij
46576afd4fSJean-Christophe PLAGNIOL-VILLARD void peripheral_power_enable (void);
47576afd4fSJean-Christophe PLAGNIOL-VILLARD
48576afd4fSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_SHOW_BOOT_PROGRESS)
show_boot_progress(int progress)49576afd4fSJean-Christophe PLAGNIOL-VILLARD void show_boot_progress(int progress)
50576afd4fSJean-Christophe PLAGNIOL-VILLARD {
51576afd4fSJean-Christophe PLAGNIOL-VILLARD printf("Boot reached stage %d\n", progress);
52576afd4fSJean-Christophe PLAGNIOL-VILLARD }
53576afd4fSJean-Christophe PLAGNIOL-VILLARD #endif
54576afd4fSJean-Christophe PLAGNIOL-VILLARD
55576afd4fSJean-Christophe PLAGNIOL-VILLARD #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
56576afd4fSJean-Christophe PLAGNIOL-VILLARD
57576afd4fSJean-Christophe PLAGNIOL-VILLARD /*
58576afd4fSJean-Christophe PLAGNIOL-VILLARD * Miscellaneous platform dependent initialisations
59576afd4fSJean-Christophe PLAGNIOL-VILLARD */
60576afd4fSJean-Christophe PLAGNIOL-VILLARD
board_init(void)61576afd4fSJean-Christophe PLAGNIOL-VILLARD int board_init (void)
62576afd4fSJean-Christophe PLAGNIOL-VILLARD {
63701ed16eSLinus Walleij u32 val;
64701ed16eSLinus Walleij
65576afd4fSJean-Christophe PLAGNIOL-VILLARD /* arch number of Integrator Board */
66576afd4fSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_ARCH_CINTEGRATOR
67576afd4fSJean-Christophe PLAGNIOL-VILLARD gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
68576afd4fSJean-Christophe PLAGNIOL-VILLARD #else
69576afd4fSJean-Christophe PLAGNIOL-VILLARD gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
70576afd4fSJean-Christophe PLAGNIOL-VILLARD #endif
71576afd4fSJean-Christophe PLAGNIOL-VILLARD
72576afd4fSJean-Christophe PLAGNIOL-VILLARD /* adress of boot parameters */
73576afd4fSJean-Christophe PLAGNIOL-VILLARD gd->bd->bi_boot_params = 0x00000100;
74576afd4fSJean-Christophe PLAGNIOL-VILLARD
75576afd4fSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_CM_REMAP
76576afd4fSJean-Christophe PLAGNIOL-VILLARD extern void cm_remap(void);
77576afd4fSJean-Christophe PLAGNIOL-VILLARD cm_remap(); /* remaps writeable memory to 0x00000000 */
78576afd4fSJean-Christophe PLAGNIOL-VILLARD #endif
79576afd4fSJean-Christophe PLAGNIOL-VILLARD
801dc26801SLinus Walleij #ifdef CONFIG_ARCH_CINTEGRATOR
81701ed16eSLinus Walleij /*
821dc26801SLinus Walleij * Flash protection on the Integrator/CP is in a simple register
831dc26801SLinus Walleij */
841dc26801SLinus Walleij val = readl(CP_FLASHPROG);
851dc26801SLinus Walleij val |= (CP_FLASHPROG_FLVPPEN | CP_FLASHPROG_FLWREN);
861dc26801SLinus Walleij writel(val, CP_FLASHPROG);
871dc26801SLinus Walleij #else
881dc26801SLinus Walleij /*
891dc26801SLinus Walleij * The Integrator/AP has some special protection mechanisms
901dc26801SLinus Walleij * for the external memories, first the External Bus Interface (EBI)
911dc26801SLinus Walleij * then the system controller (SC).
921dc26801SLinus Walleij *
93701ed16eSLinus Walleij * The system comes up with the flash memory non-writable and
94701ed16eSLinus Walleij * configuration locked. If we want U-Boot to be used for flash
95701ed16eSLinus Walleij * access we cannot have the flash memory locked.
96701ed16eSLinus Walleij */
97701ed16eSLinus Walleij writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG);
98701ed16eSLinus Walleij val = readl(EBI_BASE + EBI_CSR1_REG);
99701ed16eSLinus Walleij val &= EBI_CSR_WREN_MASK;
100701ed16eSLinus Walleij val |= EBI_CSR_WREN_ENABLE;
101701ed16eSLinus Walleij writel(val, EBI_BASE + EBI_CSR1_REG);
102701ed16eSLinus Walleij writel(0, EBI_BASE + EBI_LOCK_REG);
103701ed16eSLinus Walleij
1041dc26801SLinus Walleij /*
1051dc26801SLinus Walleij * Set up the system controller to remove write protection from
1061dc26801SLinus Walleij * the flash memory and enable Vpp
1071dc26801SLinus Walleij */
1081dc26801SLinus Walleij writel(SC_CTRL_FLASHVPP | SC_CTRL_FLASHWP, SC_CTRLS);
1091dc26801SLinus Walleij #endif
1101dc26801SLinus Walleij
111576afd4fSJean-Christophe PLAGNIOL-VILLARD icache_enable ();
112576afd4fSJean-Christophe PLAGNIOL-VILLARD
113576afd4fSJean-Christophe PLAGNIOL-VILLARD return 0;
114576afd4fSJean-Christophe PLAGNIOL-VILLARD }
115576afd4fSJean-Christophe PLAGNIOL-VILLARD
misc_init_r(void)116576afd4fSJean-Christophe PLAGNIOL-VILLARD int misc_init_r (void)
117576afd4fSJean-Christophe PLAGNIOL-VILLARD {
118382bee57SSimon Glass env_set("verify", "n");
119576afd4fSJean-Christophe PLAGNIOL-VILLARD return (0);
120576afd4fSJean-Christophe PLAGNIOL-VILLARD }
121576afd4fSJean-Christophe PLAGNIOL-VILLARD
12246b5ccbfSLinus Walleij /*
12346b5ccbfSLinus Walleij * The Integrator remaps the Flash memory to 0x00000000 and executes U-Boot
12446b5ccbfSLinus Walleij * from there, which means we cannot test the RAM underneath the ROM at this
12546b5ccbfSLinus Walleij * point. It will be unmapped later on, when we are executing from the
12646b5ccbfSLinus Walleij * relocated in RAM U-Boot. We simply assume that this RAM is usable if the
12746b5ccbfSLinus Walleij * RAM on higher addresses works fine.
12846b5ccbfSLinus Walleij */
12946b5ccbfSLinus Walleij #define REMAPPED_FLASH_SZ 0x40000
13046b5ccbfSLinus Walleij
dram_init(void)131576afd4fSJean-Christophe PLAGNIOL-VILLARD int dram_init (void)
132576afd4fSJean-Christophe PLAGNIOL-VILLARD {
13326c82638SLinus Walleij gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
134576afd4fSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_CM_SPD_DETECT
135576afd4fSJean-Christophe PLAGNIOL-VILLARD {
136576afd4fSJean-Christophe PLAGNIOL-VILLARD extern void dram_query(void);
1377c045d0bSLinus Walleij u32 cm_reg_sdram;
1387c045d0bSLinus Walleij u32 sdram_shift;
139576afd4fSJean-Christophe PLAGNIOL-VILLARD
140576afd4fSJean-Christophe PLAGNIOL-VILLARD dram_query(); /* Assembler accesses to CM registers */
141576afd4fSJean-Christophe PLAGNIOL-VILLARD /* Queries the SPD values */
142576afd4fSJean-Christophe PLAGNIOL-VILLARD
143576afd4fSJean-Christophe PLAGNIOL-VILLARD /* Obtain the SDRAM size from the CM SDRAM register */
144576afd4fSJean-Christophe PLAGNIOL-VILLARD
1457c045d0bSLinus Walleij cm_reg_sdram = readl(CM_BASE + OS_SDRAM);
146576afd4fSJean-Christophe PLAGNIOL-VILLARD /* Register SDRAM size
147576afd4fSJean-Christophe PLAGNIOL-VILLARD *
148576afd4fSJean-Christophe PLAGNIOL-VILLARD * 0xXXXXXXbbb000bb 16 MB
149576afd4fSJean-Christophe PLAGNIOL-VILLARD * 0xXXXXXXbbb001bb 32 MB
150576afd4fSJean-Christophe PLAGNIOL-VILLARD * 0xXXXXXXbbb010bb 64 MB
151576afd4fSJean-Christophe PLAGNIOL-VILLARD * 0xXXXXXXbbb011bb 128 MB
152576afd4fSJean-Christophe PLAGNIOL-VILLARD * 0xXXXXXXbbb100bb 256 MB
153576afd4fSJean-Christophe PLAGNIOL-VILLARD *
154576afd4fSJean-Christophe PLAGNIOL-VILLARD */
155576afd4fSJean-Christophe PLAGNIOL-VILLARD sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
15646b5ccbfSLinus Walleij gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
15746b5ccbfSLinus Walleij REMAPPED_FLASH_SZ,
15826c82638SLinus Walleij 0x01000000 << sdram_shift);
159576afd4fSJean-Christophe PLAGNIOL-VILLARD }
16026c82638SLinus Walleij #else
16146b5ccbfSLinus Walleij gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
16246b5ccbfSLinus Walleij REMAPPED_FLASH_SZ,
16326c82638SLinus Walleij PHYS_SDRAM_1_SIZE);
164576afd4fSJean-Christophe PLAGNIOL-VILLARD #endif /* CM_SPD_DETECT */
16546b5ccbfSLinus Walleij /* We only have one bank of RAM, set it to whatever was detected */
16646b5ccbfSLinus Walleij gd->bd->bi_dram[0].size = gd->ram_size;
167576afd4fSJean-Christophe PLAGNIOL-VILLARD
168576afd4fSJean-Christophe PLAGNIOL-VILLARD return 0;
169576afd4fSJean-Christophe PLAGNIOL-VILLARD }
170576afd4fSJean-Christophe PLAGNIOL-VILLARD
1717194ab80SBen Warren #ifdef CONFIG_CMD_NET
board_eth_init(bd_t * bis)172576afd4fSJean-Christophe PLAGNIOL-VILLARD int board_eth_init(bd_t *bis)
173576afd4fSJean-Christophe PLAGNIOL-VILLARD {
1747194ab80SBen Warren int rc = 0;
1757194ab80SBen Warren #ifdef CONFIG_SMC91111
1767194ab80SBen Warren rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
1777194ab80SBen Warren #endif
1787194ab80SBen Warren rc += pci_eth_init(bis);
1797194ab80SBen Warren return rc;
180576afd4fSJean-Christophe PLAGNIOL-VILLARD }
181576afd4fSJean-Christophe PLAGNIOL-VILLARD #endif
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