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/openbmc/qemu/tests/qemu-iotests/
H A D04625 seq=`basename $0`
34 trap "_cleanup; exit \$status" 0 1 2 3 15
60 local pattern=0
61 local cur_sec=0
63 for ((i=0;i<=$((sectors - 1));i++)); do
71 backing_io 0 32 write | $QEMU_IO "$TEST_IMG" | _filter_qemu_io
84 aio_write -P 10 0x18000 0x2000
87 aio_write -P 11 0x12000 0x2000
88 aio_write -P 12 0x1c000 0x2000
98 aio_write -P 20 0x28000 0x2000
[all …]
/openbmc/qemu/tests/qtest/
H A Daspeed_smc-test.c38 g_assert(fd >= 0); in test_palmetto_bmc()
40 g_assert(ret == 0); in test_palmetto_bmc()
48 data->flash_base = 0x20000000; in test_palmetto_bmc()
49 data->spi_base = 0x1E620000; in test_palmetto_bmc()
50 data->jedec_id = 0x20ba19; in test_palmetto_bmc()
51 data->cs = 0; in test_palmetto_bmc()
52 data->node = "/machine/soc/fmc/ssi.0/child[0]"; in test_palmetto_bmc()
54 data->page_addr = 0x14000 * FLASH_PAGE_SIZE; in test_palmetto_bmc()
85 g_assert(fd >= 0); in test_ast2500_evb()
87 g_assert(ret == 0); in test_ast2500_evb()
[all …]
/openbmc/linux/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_cfg.c22 0,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
40 .base = { 0x01100, 0x01500, 0x01900 },
45 0,
49 .base = { 0x01d00, 0x02100, 0x02500 },
53 0,
57 .base = { 0x02900, 0x02d00 },
60 0,
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
[all …]
/openbmc/linux/arch/arm/mach-imx/
H A Dmx3x.h36 #define MX3x_L2CC_BASE_ADDR 0x30000000
42 #define MX3x_AIPS1_BASE_ADDR 0x43f00000
44 #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
45 #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
46 #define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
47 #define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
48 #define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
49 #define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
50 #define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
51 #define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
[all …]
H A Dmx2x.h16 #define MX2x_AIPI_BASE_ADDR 0x10000000
18 #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
19 #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
20 #define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000)
21 #define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000)
22 #define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000)
23 #define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000)
24 #define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000)
25 #define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000)
26 #define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/marvell/
H A Darmada-37xx.txt16 reg = <0x14000 0x60>;
31 reg = <0x11500 0x40>;
/openbmc/u-boot/arch/arm/mach-snapdragon/include/mach/
H A Dsysmap-apq8096.h10 #define TLMM_BASE_ADDR (0x1010000)
13 #define SDC1_HDRV_PULL_CTL_REG (TLMM_BASE_ADDR + 0x0012D000)
16 #define GPLL0_STATUS (0x0000)
17 #define APCS_GPLL_ENA_VOTE (0x52000)
18 #define APCS_CLOCK_BRANCH_ENA_VOTE (0x52004)
20 #define SDCC2_BCR (0x14000) /* block reset */
21 #define SDCC2_APPS_CBCR (0x14004) /* branch control */
22 #define SDCC2_AHB_CBCR (0x14008)
23 #define SDCC2_CMD_RCGR (0x14010)
24 #define SDCC2_CFG_RCGR (0x14014)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dmpc512x-dma.txt24 reg = <0x14000 0x1800>;
25 interrupts = <65 0x8>;
/openbmc/linux/sound/soc/intel/atom/sst/
H A Dsst_acpi.c38 #define SST_BYT_IRAM_PHY_START 0xff2c0000
39 #define SST_BYT_IRAM_PHY_END 0xff2d4000
40 #define SST_BYT_DRAM_PHY_START 0xff300000
41 #define SST_BYT_DRAM_PHY_END 0xff320000
42 #define SST_BYT_IMR_VIRT_START 0xc0000000 /* virtual addr in LPE */
43 #define SST_BYT_IMR_VIRT_END 0xc01fffff
44 #define SST_BYT_SHIM_PHY_ADDR 0xff340000
45 #define SST_BYT_MBOX_PHY_ADDR 0xff344000
46 #define SST_BYT_DMA0_PHY_ADDR 0xff298000
47 #define SST_BYT_DMA1_PHY_ADDR 0xff29c000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dapple,nco.yaml53 #clock-cells = <0>;
60 reg = <0x3b044000 0x14000>;
/openbmc/u-boot/arch/arm/mach-versal/
H A Dcpu.c17 .virt = 0x0UL,
18 .phys = 0x0UL,
19 .size = 0x80000000UL,
23 .virt = 0x80000000UL,
24 .phys = 0x80000000UL,
25 .size = 0x70000000UL,
30 .virt = 0xf0000000UL,
31 .phys = 0xf0000000UL,
32 .size = 0x0fe00000UL,
37 .virt = 0xffe00000UL,
[all …]
/openbmc/linux/arch/arm/mach-davinci/
H A Dda8xx.h33 #define DA8XX_CP_INTC_BASE 0xfffee000
37 #define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000)
39 #define DA8XX_JTAG_ID_REG 0x18
40 #define DA8XX_HOST1CFG_REG 0x44
41 #define DA8XX_CHIPSIG_REG 0x174
42 #define DA8XX_CFGCHIP0_REG 0x17c
43 #define DA8XX_CFGCHIP1_REG 0x180
44 #define DA8XX_CFGCHIP2_REG 0x184
45 #define DA8XX_CFGCHIP3_REG 0x188
46 #define DA8XX_CFGCHIP4_REG 0x18c
[all …]
/openbmc/linux/Documentation/devicetree/bindings/ufs/
H A Dti,j721e-ufs.yaml49 "^ufs@[0-9a-f]+$":
68 reg = <0x0 0x4e80000 0x0 0x100>;
74 ranges = <0x0 0x0 0x0 0x4e80000 0x0 0x14000>;
80 reg = <0x0 0x4000 0x0 0x10000>;
/openbmc/linux/Documentation/devicetree/bindings/interconnect/
H A Dinterconnect.txt30 reg = <0x580000 0x14000>;
83 cpu@0 {
/openbmc/u-boot/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h11 #define ROMCP_ARB_BASE_ADDR 0x00000000
12 #define ROMCP_ARB_END_ADDR 0x000FFFFF
15 #define GPU_2D_ARB_BASE_ADDR 0x02200000
16 #define GPU_2D_ARB_END_ADDR 0x02203FFF
17 #define OPENVG_ARB_BASE_ADDR 0x02204000
18 #define OPENVG_ARB_END_ADDR 0x02207FFF
20 #define CAAM_ARB_BASE_ADDR 0x00100000
21 #define CAAM_ARB_END_ADDR 0x00107FFF
22 #define GPU_ARB_BASE_ADDR 0x01800000
23 #define GPU_ARB_END_ADDR 0x01803FFF
[all …]
/openbmc/u-boot/include/configs/
H A Dls2080aqds.h20 #define CONFIG_SYS_I2C_IFDR_DIV 0x7e
23 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
31 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
32 #define SPD_EEPROM_ADDRESS1 0x51
33 #define SPD_EEPROM_ADDRESS2 0x52
34 #define SPD_EEPROM_ADDRESS3 0x53
35 #define SPD_EEPROM_ADDRESS4 0x54
36 #define SPD_EEPROM_ADDRESS5 0x55
37 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
39 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
[all …]
H A Dls1021atwr.h29 #define DDR_SDRAM_CFG 0x470c0008
30 #define DDR_CS0_BNDS 0x008000bf
31 #define DDR_CS0_CONFIG 0x80014302
32 #define DDR_TIMING_CFG_0 0x50550004
33 #define DDR_TIMING_CFG_1 0xbcb38c56
34 #define DDR_TIMING_CFG_2 0x0040d120
35 #define DDR_TIMING_CFG_3 0x010e1000
36 #define DDR_TIMING_CFG_4 0x00000001
37 #define DDR_TIMING_CFG_5 0x03401400
38 #define DDR_SDRAM_CFG_2 0x00401010
[all …]
/openbmc/linux/drivers/remoteproc/
H A Dmtk_common.h15 #define MT8183_SW_RSTN 0x0
16 #define MT8183_SW_RSTN_BIT BIT(0)
17 #define MT8183_SCP_TO_HOST 0x1C
18 #define MT8183_SCP_IPC_INT_BIT BIT(0)
20 #define MT8183_HOST_TO_SCP 0x28
21 #define MT8183_HOST_IPC_INT_BIT BIT(0)
22 #define MT8183_WDT_CFG 0x84
23 #define MT8183_SCP_CLK_SW_SEL 0x4000
24 #define MT8183_SCP_CLK_DIV_SEL 0x4024
25 #define MT8183_SCP_SRAM_PDN 0x402C
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-bman1-portals.dtsi40 bman-portal@0 {
42 reg = <0x0 0x4000>, <0x100000 0x1000>;
43 interrupts = <105 2 0 0>;
47 reg = <0x4000 0x4000>, <0x101000 0x1000>;
48 interrupts = <107 2 0 0>;
52 reg = <0x8000 0x4000>, <0x102000 0x1000>;
53 interrupts = <109 2 0 0>;
57 reg = <0xc000 0x4000>, <0x103000 0x1000>;
58 interrupts = <111 2 0 0>;
62 reg = <0x10000 0x4000>, <0x104000 0x1000>;
[all …]
H A Dqoriq-qman1-portals.dtsi40 qportal0: qman-portal@0 {
42 reg = <0x0 0x4000>, <0x100000 0x1000>;
43 interrupts = <104 2 0 0>;
44 cell-index = <0x0>;
48 reg = <0x4000 0x4000>, <0x101000 0x1000>;
49 interrupts = <106 2 0 0>;
54 reg = <0x8000 0x4000>, <0x102000 0x1000>;
55 interrupts = <108 2 0 0>;
60 reg = <0xc000 0x4000>, <0x103000 0x1000>;
61 interrupts = <110 2 0 0>;
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-omap4/
H A Domap.h26 #define OMAP44XX_L4_CORE_BASE 0x4A000000
27 #define OMAP44XX_L4_WKUP_BASE 0x4A300000
28 #define OMAP44XX_L4_PER_BASE 0x48000000
30 #define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000
31 #define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000
36 #define CONTROL_ID_CODE 0x4A002204
38 #define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F
39 #define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F
40 #define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F
41 #define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F
[all …]
/openbmc/linux/drivers/reset/
H A Dreset-qcom-aoss.c30 [AOSS_CC_MSS_RESTART] = {0x10000},
31 [AOSS_CC_CAMSS_RESTART] = {0x11000},
32 [AOSS_CC_VENUS_RESTART] = {0x12000},
33 [AOSS_CC_GPU_RESTART] = {0x13000},
34 [AOSS_CC_DISPSS_RESTART] = {0x14000},
35 [AOSS_CC_WCSS_RESTART] = {0x20000},
36 [AOSS_CC_LPASS_RESTART] = {0x30000},
59 return 0; in qcom_aoss_control_assert()
68 writel(0, data->base + map->reg); in qcom_aoss_control_deassert()
71 return 0; in qcom_aoss_control_deassert()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-omap5/
H A Dcpu.h23 u32 tidr; /* 0x00 r */
24 u8 res1[0xc];
25 u32 tiocp_cfg; /* 0x10 rw */
26 u8 res2[0x10];
27 u32 tisr_raw; /* 0x24 r */
28 u32 tisr; /* 0x28 rw */
29 u32 tier; /* 0x2c rw */
30 u32 ticr; /* 0x30 rw */
31 u32 twer; /* 0x34 rw */
32 u32 tclr; /* 0x38 rw */
[all …]
/openbmc/linux/drivers/net/ethernet/wangxun/ngbe/
H A Dngbe_type.h12 #define NGBE_DEV_ID_EM_WX1860AL_W 0x0100
13 #define NGBE_DEV_ID_EM_WX1860A2 0x0101
14 #define NGBE_DEV_ID_EM_WX1860A2S 0x0102
15 #define NGBE_DEV_ID_EM_WX1860A4 0x0103
16 #define NGBE_DEV_ID_EM_WX1860A4S 0x0104
17 #define NGBE_DEV_ID_EM_WX1860AL2 0x0105
18 #define NGBE_DEV_ID_EM_WX1860AL2S 0x0106
19 #define NGBE_DEV_ID_EM_WX1860AL4 0x0107
20 #define NGBE_DEV_ID_EM_WX1860AL4S 0x0108
21 #define NGBE_DEV_ID_EM_WX1860LC 0x0109
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/apple/
H A Dapple,pmgr.yaml20 pattern: "^power-management@[0-9a-f]+$"
42 "power-controller@[0-9a-f]+$":
64 reg = <0x2 0x3b700000 0x0 0x14000>;
68 reg = <0x1c0 8>;
69 #power-domain-cells = <0>;
70 #reset-cells = <0>;
77 reg = <0x220 8>;
78 #power-domain-cells = <0>;
79 #reset-cells = <0>;
86 reg = <0x270 8>;
[all …]

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