Lines Matching +full:0 +full:x14000
10 #define TLMM_BASE_ADDR (0x1010000)
13 #define SDC1_HDRV_PULL_CTL_REG (TLMM_BASE_ADDR + 0x0012D000)
16 #define GPLL0_STATUS (0x0000)
17 #define APCS_GPLL_ENA_VOTE (0x52000)
18 #define APCS_CLOCK_BRANCH_ENA_VOTE (0x52004)
20 #define SDCC2_BCR (0x14000) /* block reset */
21 #define SDCC2_APPS_CBCR (0x14004) /* branch control */
22 #define SDCC2_AHB_CBCR (0x14008)
23 #define SDCC2_CMD_RCGR (0x14010)
24 #define SDCC2_CFG_RCGR (0x14014)
25 #define SDCC2_M (0x14018)
26 #define SDCC2_N (0x1401C)
27 #define SDCC2_D (0x14020)
29 #define BLSP2_AHB_CBCR (0x25004)
30 #define BLSP2_UART2_APPS_CBCR (0x29004)
31 #define BLSP2_UART2_APPS_CMD_RCGR (0x2900C)
32 #define BLSP2_UART2_APPS_CFG_RCGR (0x29010)
33 #define BLSP2_UART2_APPS_M (0x29014)
34 #define BLSP2_UART2_APPS_N (0x29018)
35 #define BLSP2_UART2_APPS_D (0x2901C)