Lines Matching +full:0 +full:x14000
20 #define CONFIG_SYS_I2C_IFDR_DIV 0x7e
23 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
31 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
32 #define SPD_EEPROM_ADDRESS1 0x51
33 #define SPD_EEPROM_ADDRESS2 0x52
34 #define SPD_EEPROM_ADDRESS3 0x53
35 #define SPD_EEPROM_ADDRESS4 0x54
36 #define SPD_EEPROM_ADDRESS5 0x55
37 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
39 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
58 #define CONFIG_SYS_MMC_ENV_DEV 0
59 #define CONFIG_ENV_SIZE 0x20000
60 #define CONFIG_ENV_OFFSET 0x500000
63 #define CONFIG_ENV_SECT_SIZE 0x20000
66 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
91 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
92 FTIM0_NOR_TEADC(0x5) | \
93 FTIM0_NOR_TEAHC(0x5))
94 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
95 FTIM1_NOR_TRAD_NOR(0x1a) |\
96 FTIM1_NOR_TSEQRAD_NOR(0x13))
97 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
98 FTIM2_NOR_TCH(0x4) | \
99 FTIM2_NOR_TWPH(0x0E) | \
100 FTIM2_NOR_TWP(0x1c))
101 #define CONFIG_SYS_NOR_FTIM3 0x04000000
102 #define CONFIG_SYS_IFC_CCR 0x01000000
115 CONFIG_SYS_FLASH_BASE + 0x40000000}
122 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
140 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
141 FTIM0_NAND_TWP(0x18) | \
142 FTIM0_NAND_TWCHT(0x07) | \
143 FTIM0_NAND_TWH(0x0a))
144 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
145 FTIM1_NAND_TWBE(0x39) | \
146 FTIM1_NAND_TRR(0x0e) | \
147 FTIM1_NAND_TRP(0x18))
148 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
149 FTIM2_NAND_TREH(0x0a) | \
150 FTIM2_NAND_TWHRE(0x1e))
151 #define CONFIG_SYS_NAND_FTIM3 0x0
160 #define QIXIS_LBMAP_SWITCH 0x06
161 #define QIXIS_LBMAP_MASK 0x0f
162 #define QIXIS_LBMAP_SHIFT 0
163 #define QIXIS_LBMAP_DFLTBANK 0x00
164 #define QIXIS_LBMAP_ALTBANK 0x04
165 #define QIXIS_LBMAP_NAND 0x09
166 #define QIXIS_LBMAP_SD 0x00
167 #define QIXIS_LBMAP_QSPI 0x0f
168 #define QIXIS_RST_CTL_RESET 0x31
169 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
170 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
171 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
172 #define QIXIS_RCW_SRC_NAND 0x107
173 #define QIXIS_RCW_SRC_SD 0x40
174 #define QIXIS_RCW_SRC_QSPI 0x62
175 #define QIXIS_RST_FORCE_MEM 0x01
177 #define CONFIG_SYS_CSPR3_EXT (0x0)
190 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
191 FTIM0_GPCM_TEADC(0x0e) | \
192 FTIM0_GPCM_TEAHC(0x0e))
193 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
194 FTIM1_GPCM_TRAD(0x3f))
195 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
196 FTIM2_GPCM_TCH(0xf) | \
197 FTIM2_GPCM_TWP(0x3E))
198 #define CONFIG_SYS_CS3_FTIM3 0x0
231 #define CONFIG_ENV_SECT_SIZE 0x20000
232 #define CONFIG_ENV_SIZE 0x2000
233 #define CONFIG_SPL_PAD_TO 0x20000
237 #define CONFIG_ENV_OFFSET 0x300000
238 #define CONFIG_SYS_MMC_ENV_DEV 0
239 #define CONFIG_ENV_SIZE 0x20000
271 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
272 #define CONFIG_ENV_SECT_SIZE 0x20000
273 #define CONFIG_ENV_SIZE 0x2000
279 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
286 #define I2C_MUX_PCA_ADDR 0x77
287 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
290 #define I2C_MUX_CH_DEFAULT 0x8
307 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
308 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
310 #define FSL_QIXIS_BRDCFG9_QSPI 0x1
327 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
332 #define CONFIG_SYS_EEPROM_BUS_NUM 0
333 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
353 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
354 "loadaddr=0x80100000\0" \
355 "kernel_addr=0x100000\0" \
356 "ramdisk_addr=0x800000\0" \
357 "ramdisk_size=0x2000000\0" \
358 "fdt_high=0xa0000000\0" \
359 "initrd_high=0xffffffffffffffff\0" \
360 "kernel_start=0x581000000\0" \
361 "kernel_load=0xa0000000\0" \
362 "kernel_size=0x2800000\0" \
363 "mcmemsize=0x40000000\0" \
364 "mcinitcmd=esbc_validate 0x580700000;" \
365 "esbc_validate 0x580740000;" \
366 "fsl_mc start mc 0x580a00000" \
367 " 0x580e00000 \0"
371 "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
372 "mmc read 0x80100000 0x7000 0x800;" \
373 "fsl_mc start mc 0x80000000 0x80100000\0"
375 "fsl_mc start mc 0x580a00000" \
376 " 0x580e00000 \0"
378 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
379 "loadaddr=0x80100000\0" \
380 "loadaddr_sd=0x90100000\0" \
381 "kernel_addr=0x100000\0" \
382 "kernel_addr_sd=0x800\0" \
383 "ramdisk_addr=0x800000\0" \
384 "ramdisk_size=0x2000000\0" \
385 "fdt_high=0xa0000000\0" \
386 "initrd_high=0xffffffffffffffff\0" \
387 "kernel_start=0x581000000\0" \
388 "kernel_start_sd=0x8000\0" \
389 "kernel_load=0xa0000000\0" \
390 "kernel_size=0x2800000\0" \
391 "kernel_size_sd=0x14000\0" \
392 "mcinitcmd=fsl_mc start mc 0x580a00000" \
393 " 0x580e00000 \0" \
394 "mcmemsize=0x70000000 \0"
397 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
398 "loadaddr=0x90100000\0" \
399 "kernel_addr=0x800\0" \
400 "ramdisk_addr=0x800000\0" \
401 "ramdisk_size=0x2000000\0" \
402 "fdt_high=0xa0000000\0" \
403 "initrd_high=0xffffffffffffffff\0" \
404 "kernel_start=0x8000\0" \
405 "kernel_load=0xa0000000\0" \
406 "kernel_size=0x14000\0" \
407 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
408 "mmc read 0x80100000 0x7000 0x800;" \
409 "fsl_mc start mc 0x80000000 0x80100000\0" \
410 "mcmemsize=0x70000000 \0"
413 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
414 "loadaddr=0x80100000\0" \
415 "kernel_addr=0x100000\0" \
416 "ramdisk_addr=0x800000\0" \
417 "ramdisk_size=0x2000000\0" \
418 "fdt_high=0xa0000000\0" \
419 "initrd_high=0xffffffffffffffff\0" \
420 "kernel_start=0x581000000\0" \
421 "kernel_load=0xa0000000\0" \
422 "kernel_size=0x2800000\0" \
423 "mcmemsize=0x40000000\0" \
424 "mcinitcmd=fsl_mc start mc 0x580a00000" \
425 " 0x580e00000 \0"
435 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
436 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
437 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
438 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
440 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
441 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
442 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
443 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
444 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
445 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
446 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
447 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
448 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
449 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
450 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
451 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
452 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
453 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
454 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
455 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf