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/openbmc/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Dgaudi2_blocks_linux_driver.h16 #define mmDCORE0_TPC0_ROM_TABLE_BASE 0x0ull
17 #define DCORE0_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
18 #define DCORE0_TPC0_ROM_TABLE_SECTION 0x1000
19 #define mmDCORE0_TPC0_EML_SPMU_BASE 0x1000ull
20 #define DCORE0_TPC0_EML_SPMU_MAX_OFFSET 0x1000
21 #define DCORE0_TPC0_EML_SPMU_SECTION 0x1000
22 #define mmDCORE0_TPC0_EML_ETF_BASE 0x2000ull
23 #define DCORE0_TPC0_EML_ETF_MAX_OFFSET 0x1000
24 #define DCORE0_TPC0_EML_ETF_SECTION 0x1000
25 #define mmDCORE0_TPC0_EML_STM_BASE 0x3000ull
[all …]
/openbmc/u-boot/test/py/tests/test_fs/
H A Dtest_ext.py26 'host bind 0 %s' % fs_img,
27 '%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
28 '%swrite host 0:0 %x /dir1/%s.w1 $filesize'
35 '%sload host 0:0 %x /dir1/%s.w1' % (fs_type, ADDR, MIN_FILE),
38 assert(md5val[0] in ''.join(output))
48 'host bind 0 %s' % fs_img,
49 '%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
50 '%swrite host 0:0 %x dir1/%s.w2 $filesize'
57 '%sload host 0:0 %x dir1/%s.w2' % (fs_type, ADDR, MIN_FILE),
60 assert(md5val[0] in ''.join(output))
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpu_sun9i.h12 #define REGS_AHB0_BASE 0x01C00000
13 #define REGS_AHB1_BASE 0x00800000
14 #define REGS_AHB2_BASE 0x03000000
15 #define REGS_APB0_BASE 0x06000000
16 #define REGS_APB1_BASE 0x07000000
17 #define REGS_RCPUS_BASE 0x08000000
19 #define SUNXI_SRAM_D_BASE 0x08100000
22 #define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
23 #define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)
25 #define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000)
[all …]
/openbmc/linux/drivers/bus/
H A Domap_l3_smx.h14 #define L3_COMPONENT 0x000
15 #define L3_CORE 0x018
16 #define L3_AGENT_CONTROL 0x020
17 #define L3_AGENT_STATUS 0x028
18 #define L3_ERROR_LOG 0x058
23 #define L3_ERROR_LOG_ADDR 0x060
26 #define L3_SI_CONTROL 0x020
27 #define L3_SI_FLAG_STATUS_0 0x510
31 #define L3_STATUS_0_MPUIA_BRST (shift << 0)
95 #define L3_SI_FLAG_STATUS_1 0x530
[all …]
/openbmc/linux/arch/sparc/include/asm/
H A Dcontregs.h12 #define AC_M_PCR 0x0000 /* shv Processor Control Reg */
13 #define AC_M_CTPR 0x0100 /* shv Context Table Pointer Reg */
14 #define AC_M_CXR 0x0200 /* shv Context Register */
15 #define AC_M_SFSR 0x0300 /* shv Synchronous Fault Status Reg */
16 #define AC_M_SFAR 0x0400 /* shv Synchronous Fault Address Reg */
17 #define AC_M_AFSR 0x0500 /* hv Asynchronous Fault Status Reg */
18 #define AC_M_AFAR 0x0600 /* hv Asynchronous Fault Address Reg */
19 #define AC_M_RESET 0x0700 /* hv Reset Reg */
20 #define AC_M_RPR 0x1000 /* hv Root Pointer Reg */
21 #define AC_M_TSUTRCR 0x1000 /* s TLB Replacement Ctrl Reg */
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32mp153.dtsi35 reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
42 bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
48 reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
55 bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
H A Dstm32mp133.dtsi13 reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
20 bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
26 reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
33 bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
39 reg = <0x48003000 0x400>;
46 #size-cells = <0>;
49 adc1: adc@0 {
53 #size-cells = <0>;
54 reg = <0x0>;
56 interrupts = <0>;
[all …]
/openbmc/linux/sound/soc/sof/amd/
H A Dacp-dsp-offset.h15 #define ACP_DMA_CNTL_0 0x00
16 #define ACP_DMA_DSCR_STRT_IDX_0 0x20
17 #define ACP_DMA_DSCR_CNT_0 0x40
18 #define ACP_DMA_PRIO_0 0x60
19 #define ACP_DMA_CUR_DSCR_0 0x80
20 #define ACP_DMA_ERR_STS_0 0xC0
21 #define ACP_DMA_DESC_BASE_ADDR 0xE0
22 #define ACP_DMA_DESC_MAX_NUM_DSCR 0xE4
23 #define ACP_DMA_CH_STS 0xE8
24 #define ACP_DMA_CH_GROUP 0xEC
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A Dcontregs.h15 #define AC_IDPROM 0x00000000 /* 34 ID PROM, R/O, byte, 32 bytes */
16 #define AC_PAGEMAP 0x10000000 /* 3 Pagemap R/W, long */
17 #define AC_SEGMAP 0x20000000 /* 3 Segment map, byte */
18 #define AC_CONTEXT 0x30000000 /* 34c current mmu-context */
19 #define AC_SENABLE 0x40000000 /* 34c system dvma/cache/reset enable reg*/
20 #define AC_UDVMA_ENB 0x50000000 /* 34 Not used on Sun boards, byte */
21 #define AC_BUS_ERROR 0x60000000 /* 34 Not cleared on read, byte. */
22 #define AC_SYNC_ERR 0x60000000 /* c fault type */
23 #define AC_SYNC_VA 0x60000004 /* c fault virtual address */
24 #define AC_ASYNC_ERR 0x60000008 /* c asynchronous fault type */
[all …]
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_dfs.c58 printf("\n write reg 0x%08x = 0x%08x", addr, val); in dfs_reg_write()
76 } while (reg); /* Wait for '0' */ in wait_refresh_op_complete()
117 u32 cs = 0; in ddr3_dfs_high_2_low()
123 freq_par = ddr3_get_freq_parameter(freq, 0); in ddr3_dfs_high_2_low()
133 /* [0] - DfsDllNextState - Disable */ in ddr3_dfs_high_2_low()
135 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
142 /* [0] - RetryMask - Disable */ in ddr3_dfs_high_2_low()
144 /* 0x14B0 - Dunit MMask Register */ in ddr3_dfs_high_2_low()
150 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
158 reg = (0x9 & REG_SDRAM_OPERATION_CWA_RC_MASK) << in ddr3_dfs_high_2_low()
[all …]
/openbmc/u-boot/arch/x86/include/asm/arch-broadwell/
H A Diomap.h11 #define MCFG_BASE_ADDRESS 0xf0000000
12 #define MCFG_BASE_SIZE 0x4000000
14 #define HPET_BASE_ADDRESS 0xfed00000
16 #define MCH_BASE_ADDRESS 0xfed10000
17 #define MCH_BASE_SIZE 0x8000
19 #define DMI_BASE_ADDRESS 0xfed18000
20 #define DMI_BASE_SIZE 0x1000
22 #define EP_BASE_ADDRESS 0xfed19000
23 #define EP_BASE_SIZE 0x1000
25 #define EDRAM_BASE_ADDRESS 0xfed80000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dmarvell,mvebu-sdram-controller.yaml30 reg = <0x1400 0x500>;
/openbmc/u-boot/arch/arm/include/asm/arch-am33xx/
H A Dhardware_ti814x.h16 #define UART0_BASE 0x48020000
19 #define WDT_BASE 0x481C7000
22 #define CTRL_BASE 0x48140000
23 #define CTRL_DEVICE_BASE 0x48140600
26 #define PRCM_BASE 0x48180000
27 #define CM_PER 0x44E00000
28 #define CM_WKUP 0x44E00400
30 #define PRM_RSTCTRL (PRCM_BASE + 0x00A0)
34 #define PLL_SUBSYS_BASE 0x481C5000
37 #define VTP0_CTRL_ADDR 0x48140E0C
[all …]
H A Dhardware_am33xx.h16 #define UART0_BASE 0x44E09000
17 #define UART1_BASE 0x48022000
18 #define UART2_BASE 0x48024000
19 #define UART3_BASE 0x481A6000
20 #define UART4_BASE 0x481A8000
21 #define UART5_BASE 0x481AA000
24 #define GPIO2_BASE 0x481AC000
27 #define WDT_BASE 0x44E35000
30 #define CTRL_BASE 0x44E10000
31 #define CTRL_DEVICE_BASE 0x44E10600
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Domap34xx.h17 #define L4_34XX_BASE 0x48000000
18 #define L4_WK_34XX_BASE 0x48300000
19 #define L4_PER_34XX_BASE 0x49000000
20 #define L4_EMU_34XX_BASE 0x54000000
21 #define L3_34XX_BASE 0x68000000
23 #define L4_WK_AM33XX_BASE 0x44C00000
25 #define OMAP3430_32KSYNCT_BASE 0x48320000
26 #define OMAP3430_CM_BASE 0x48004800
27 #define OMAP3430_PRM_BASE 0x48306800
28 #define OMAP343X_SMS_BASE 0x6C000000
[all …]
H A Dcm81xx.h13 #define TI81XX_CM_ACTIVE_MOD 0x0400 /* 256B */
14 #define TI81XX_CM_DEFAULT_MOD 0x0500 /* 256B */
15 #define TI81XX_CM_ALWON_MOD 0x1400 /* 1KB */
16 #define TI81XX_CM_SGX_MOD 0x0900 /* 256B */
19 #define TI816X_CM_IVAHD0_MOD 0x0600 /* 256B */
20 #define TI816X_CM_IVAHD1_MOD 0x0700 /* 256B */
21 #define TI816X_CM_IVAHD2_MOD 0x0800 /* 256B */
24 #define TI81XX_CM_ALWON_L3_SLOW_CLKDM 0x0000
25 #define TI81XX_CM_ALWON_L3_MED_CLKDM 0x0004
26 #define TI81XX_CM_ETHERNET_CLKDM 0x0004
[all …]
H A Dcm2_54xx.h22 #define OMAP54XX_CM_CORE_BASE 0x4a008000
28 #define OMAP54XX_CM_CORE_OCP_SOCKET_INST 0x0000
29 #define OMAP54XX_CM_CORE_CKGEN_INST 0x0100
30 #define OMAP54XX_CM_CORE_COREAON_INST 0x0600
31 #define OMAP54XX_CM_CORE_CORE_INST 0x0700
32 #define OMAP54XX_CM_CORE_IVA_INST 0x1200
33 #define OMAP54XX_CM_CORE_CAM_INST 0x1300
34 #define OMAP54XX_CM_CORE_DSS_INST 0x1400
35 #define OMAP54XX_CM_CORE_GPU_INST 0x1500
36 #define OMAP54XX_CM_CORE_L3INIT_INST 0x1600
[all …]
H A Dprm54xx.h24 #define OMAP54XX_PRM_BASE 0x4ae06000
31 #define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000
32 #define OMAP54XX_PRM_CKGEN_INST 0x0100
33 #define OMAP54XX_PRM_MPU_INST 0x0300
34 #define OMAP54XX_PRM_DSP_INST 0x0400
35 #define OMAP54XX_PRM_ABE_INST 0x0500
36 #define OMAP54XX_PRM_COREAON_INST 0x0600
37 #define OMAP54XX_PRM_CORE_INST 0x0700
38 #define OMAP54XX_PRM_IVA_INST 0x1200
39 #define OMAP54XX_PRM_CAM_INST 0x1300
[all …]
H A Dcm2_44xx.h26 #define OMAP4430_CM2_BASE 0x4a008000
32 #define OMAP4430_CM2_OCP_SOCKET_INST 0x0000
33 #define OMAP4430_CM2_CKGEN_INST 0x0100
34 #define OMAP4430_CM2_ALWAYS_ON_INST 0x0600
35 #define OMAP4430_CM2_CORE_INST 0x0700
36 #define OMAP4430_CM2_IVAHD_INST 0x0f00
37 #define OMAP4430_CM2_CAM_INST 0x1000
38 #define OMAP4430_CM2_DSS_INST 0x1100
39 #define OMAP4430_CM2_GFX_INST 0x1200
40 #define OMAP4430_CM2_L3INIT_INST 0x1300
[all …]
H A Dprm7xx.h26 #define DRA7XX_PRM_BASE 0x4ae06000
33 #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000
34 #define DRA7XX_PRM_CKGEN_INST 0x0100
35 #define DRA7XX_PRM_MPU_INST 0x0300
36 #define DRA7XX_PRM_DSP1_INST 0x0400
37 #define DRA7XX_PRM_IPU_INST 0x0500
38 #define DRA7XX_PRM_COREAON_INST 0x0628
39 #define DRA7XX_PRM_CORE_INST 0x0700
40 #define DRA7XX_PRM_IVA_INST 0x0f00
41 #define DRA7XX_PRM_CAM_INST 0x1000
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/clk/
H A Dpll-ld11.c14 #define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
15 #define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */
16 #define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* DSP */
17 #define SC_VSPLLCTRL (SC_BASE_ADDR | 0x1440) /* Video codec, VPE etc. */
18 #define SC_DPLLCTRL (SC_BASE_ADDR | 0x1460) /* DDR memory */
21 #define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
22 #define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
29 uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); in uniphier_ld11_pll_init()
43 writel(0, SC_CA53_GEARSET); /* Gear0: CPLL/2 */ in uniphier_ld11_pll_init()
H A Dpll-ld20.c14 #define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
15 #define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */
16 #define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */
17 #define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* Video codec */
18 #define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* VPE etc. */
19 #define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* GPU/Mali */
20 #define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* DDR memory 0 */
21 #define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* DDR memory 1 */
22 #define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 2 */
25 #define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7996/
H A Deeprom.h12 MT_EE_CHIP_ID = 0x000,
13 MT_EE_VERSION = 0x002,
14 MT_EE_MAC_ADDR = 0x004,
15 MT_EE_MAC_ADDR2 = 0x00a,
16 MT_EE_WIFI_CONF = 0x190,
17 MT_EE_MAC_ADDR3 = 0x2c0,
18 MT_EE_RATE_DELTA_2G = 0x1400,
19 MT_EE_RATE_DELTA_5G = 0x147d,
20 MT_EE_RATE_DELTA_6G = 0x154a,
21 MT_EE_TX0_POWER_2G = 0x1300,
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi12 #clock-cells = <0>;
20 #clock-cells = <0>;
29 #clock-cells = <0>;
32 reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
38 #clock-cells = <0>;
42 reg = <0x0d50>;
47 #clock-cells = <0>;
51 reg = <0x0b00>;
55 #clock-cells = <0>;
63 #clock-cells = <0>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
H A Dpar_io.txt18 #size-cells = <0>;
41 reg = <0x1400 0x18>;
49 reg = <0x1460 0x18>;

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