Lines Matching +full:0 +full:x1400
58 printf("\n write reg 0x%08x = 0x%08x", addr, val); in dfs_reg_write()
76 } while (reg); /* Wait for '0' */ in wait_refresh_op_complete()
117 u32 cs = 0; in ddr3_dfs_high_2_low()
123 freq_par = ddr3_get_freq_parameter(freq, 0); in ddr3_dfs_high_2_low()
133 /* [0] - DfsDllNextState - Disable */ in ddr3_dfs_high_2_low()
135 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
142 /* [0] - RetryMask - Disable */ in ddr3_dfs_high_2_low()
144 /* 0x14B0 - Dunit MMask Register */ in ddr3_dfs_high_2_low()
150 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
158 reg = (0x9 & REG_SDRAM_OPERATION_CWA_RC_MASK) << in ddr3_dfs_high_2_low()
164 reg |= ((0 & REG_SDRAM_OPERATION_CWA_DATA_MASK) << in ddr3_dfs_high_2_low()
171 reg |= (0 << REG_SDRAM_OPERATION_CWA_DELAY_SEL_OFFS); in ddr3_dfs_high_2_low()
175 ~(0xF << REG_SDRAM_OPERATION_CS_OFFS)); in ddr3_dfs_high_2_low()
177 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_high_2_low()
190 /* 0x16D0 - DDR3 Registered DRAM Control */ in ddr3_dfs_high_2_low()
195 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
208 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
213 } while (reg == 0x0); /* 0x1528 [3] - DfsAtSR - Wait for '1' */ in ddr3_dfs_high_2_low()
221 /* 0xE8264[7:0] 0xff CPU Clock Dividers Reset mask */ in ddr3_dfs_high_2_low()
222 dfs_reg_write(CPU_PLL_CLOCK_DIVIDER_CNTRL0, (reg + 0xFF)); in ddr3_dfs_high_2_low()
227 /* 0xE8260 [15:8] 0x2 CPU Clock Dividers Reload Smooth enable */ in ddr3_dfs_high_2_low()
234 /* 0xE8260 [31:24] 0x2 Relax Enable */ in ddr3_dfs_high_2_low()
241 * 0xE8268 [13:8] N Set Training clock: in ddr3_dfs_high_2_low()
251 /* 0xE8264 [8]=0x1 CPU Clock Dividers Reload Ratio trigger set */ in ddr3_dfs_high_2_low()
260 /* 0xE8264 [8]=0x0 CPU Clock Dividers Reload Ratio trigger clear */ in ddr3_dfs_high_2_low()
269 * force reserved bits[7:0]. in ddr3_dfs_high_2_low()
271 reg = 0x0000FDFF; in ddr3_dfs_high_2_low()
272 /* 0x18700 - CPU Div CLK control 0 */ in ddr3_dfs_high_2_low()
279 reg = 0x0000FF00; in ddr3_dfs_high_2_low()
280 /* 0x18704 - CPU Div CLK control 0 */ in ddr3_dfs_high_2_low()
288 /* 0x1870C - CPU Div CLK control 3 register */ in ddr3_dfs_high_2_low()
298 reg = 0x000FFF02; in ddr3_dfs_high_2_low()
311 * bits [7:0] == not in use in ddr3_dfs_high_2_low()
313 reg = 0x0102FDFF; in ddr3_dfs_high_2_low()
314 /* 0x18700 - CPU Div CLK control 0 register */ in ddr3_dfs_high_2_low()
320 * Poll Div CLK status 0 register - indication that the clocks in ddr3_dfs_high_2_low()
321 * are active - 0x18718 [8] in ddr3_dfs_high_2_low()
326 } while (reg == 0); in ddr3_dfs_high_2_low()
332 reg = 0x000000FF; in ddr3_dfs_high_2_low()
333 /* 0x18700 - CPU Div CLK control 0 register */ in ddr3_dfs_high_2_low()
344 /* 0x18488 - DRAM Init control status register */ in ddr3_dfs_high_2_low()
348 /* [15] - Phy2UnitClkRatio = 0 - Set 1:1 Ratio between Dunit and Phy */ in ddr3_dfs_high_2_low()
351 dfs_reg_write(REG_DDR_IO_ADDR, reg); /* 0x1524 - DDR IO Register */ in ddr3_dfs_high_2_low()
357 /* 0x1404 - DDR Controller Control Low Register */ in ddr3_dfs_high_2_low()
365 reg |= (0x4 << REG_DFS_CL_NEXT_STATE_OFFS); in ddr3_dfs_high_2_low()
367 reg |= (0x1 << REG_DFS_CWL_NEXT_STATE_OFFS); in ddr3_dfs_high_2_low()
368 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
374 /* 0x1674 [10:0] - Phy lock status Register */ in ddr3_dfs_high_2_low()
379 /* [30:29] = 0 - Data Pup R/W path reset */ in ddr3_dfs_high_2_low()
380 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_high_2_low()
389 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_high_2_low()
398 reg = (0xA & REG_SDRAM_OPERATION_CWA_RC_MASK) << in ddr3_dfs_high_2_low()
405 reg |= ((0x0 & REG_SDRAM_OPERATION_CWA_DATA_MASK) << in ddr3_dfs_high_2_low()
409 reg |= (0x1 << REG_SDRAM_OPERATION_CWA_DELAY_SEL_OFFS); in ddr3_dfs_high_2_low()
413 ~(0xF << REG_SDRAM_OPERATION_CS_OFFS)); in ddr3_dfs_high_2_low()
415 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_high_2_low()
428 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
431 * Poll - DFS Register - 0x1528 [3] - DfsAtSR - All DRAM devices in ddr3_dfs_high_2_low()
436 } while (reg); /* Wait for '0' */ in ddr3_dfs_high_2_low()
439 /* [3-0] = 0x2 - Refresh Command, [11-8] - enabled Cs */ in ddr3_dfs_high_2_low()
441 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
446 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_high_2_low()
455 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
462 /* [0] - RetryMask - Enable */ in ddr3_dfs_high_2_low()
464 /* 0x14B0 - Dunit MMask Register */ in ddr3_dfs_high_2_low()
467 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
473 tmp = 0x4; /* CL=6 - 0x4 */ in ddr3_dfs_high_2_low()
474 reg |= ((tmp & 0x1) << REG_DDR3_MR0_CL_OFFS); in ddr3_dfs_high_2_low()
475 reg |= ((tmp & 0xE) << REG_DDR3_MR0_CL_HIGH_OFFS); in ddr3_dfs_high_2_low()
483 /* CWL=6 - 0x1 */ in ddr3_dfs_high_2_low()
484 reg |= ((0x1) << REG_DDR3_MR2_CWL_OFFS); in ddr3_dfs_high_2_low()
498 u32 cs = 0; in ddr3_dfs_high_2_low()
504 freq_par = ddr3_get_freq_parameter(freq, 0); in ddr3_dfs_high_2_low()
506 reg = 0x0000FF00; in ddr3_dfs_high_2_low()
507 /* 0x18700 - CPU Div CLK control 0 */ in ddr3_dfs_high_2_low()
510 /* 0x1600 - ODPG_CNTRL_Control */ in ddr3_dfs_high_2_low()
516 /* 0x1670 - PHY lock mask register */ in ddr3_dfs_high_2_low()
518 reg &= REG_PHY_LOCK_MASK_MASK; /* [11:0] = 0 */ in ddr3_dfs_high_2_low()
521 reg = reg_read(REG_DFS_ADDR); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
524 reg &= ~0x10; /* [4] - Enable reconfig MR registers after DFS_ERG */ in ddr3_dfs_high_2_low()
525 reg |= 0x1; /* [0] - DRAM DLL disabled after DFS */ in ddr3_dfs_high_2_low()
527 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
529 reg = reg_read(REG_METAL_MASK_ADDR) & ~(1 << 0); /* [0] - disable */ in ddr3_dfs_high_2_low()
530 /* 0x14B0 - Dunit MMask Register */ in ddr3_dfs_high_2_low()
535 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
539 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
542 * Poll DFS Register - 0x1528 [3] - DfsAtSR - in ddr3_dfs_high_2_low()
548 } while (reg == 0x0); /* Wait for '1' */ in ddr3_dfs_high_2_low()
554 /* [11:0] = 0 */ in ddr3_dfs_high_2_low()
556 /* 0x1670 - PHY lock mask register */ in ddr3_dfs_high_2_low()
565 * force reserved bits[7:0]. in ddr3_dfs_high_2_low()
567 reg = 0x0000FDFF; in ddr3_dfs_high_2_low()
568 /* 0x18700 - CPU Div CLK control 0 */ in ddr3_dfs_high_2_low()
574 reg = 0x0000FF00; in ddr3_dfs_high_2_low()
575 /* 0x18700 - CPU Div CLK control 0 */ in ddr3_dfs_high_2_low()
582 /* 0x1870C - CPU Div CLK control 3 register */ in ddr3_dfs_high_2_low()
592 reg = 0x000FFF02; in ddr3_dfs_high_2_low()
605 * bits [7:0] == not in use in ddr3_dfs_high_2_low()
607 reg = 0x0102FDFF; in ddr3_dfs_high_2_low()
608 /* 0x18700 - CPU Div CLK control 0 register */ in ddr3_dfs_high_2_low()
614 * Poll Div CLK status 0 register - indication that the clocks in ddr3_dfs_high_2_low()
615 * are active - 0x18718 [8] in ddr3_dfs_high_2_low()
620 } while (reg == 0); in ddr3_dfs_high_2_low()
626 reg = 0x000000FF; in ddr3_dfs_high_2_low()
627 /* 0x18700 - CPU Div CLK control 0 register */ in ddr3_dfs_high_2_low()
633 reg = 0x20050000; in ddr3_dfs_high_2_low()
634 /* 0x18488 - DRAM Init control status register */ in ddr3_dfs_high_2_low()
638 /* [15] = 0 - Set 1:1 Ratio between Dunit and Phy */ in ddr3_dfs_high_2_low()
639 dfs_reg_write(REG_DDR_IO_ADDR, reg); /* 0x1524 - DDR IO Regist */ in ddr3_dfs_high_2_low()
643 /* 0x15EC - DRAM PHY Config register */ in ddr3_dfs_high_2_low()
648 /* 0x15EC - DRAM PHY Config register */ in ddr3_dfs_high_2_low()
653 /* 0x1404 */ in ddr3_dfs_high_2_low()
654 reg = (reg_read(REG_DUNIT_CTRL_LOW_ADDR) & 0xFFFFFFE7); in ddr3_dfs_high_2_low()
657 /* Poll Phy lock status register - APLL lock indication - 0x1674 */ in ddr3_dfs_high_2_low()
661 } while (reg != REG_PHY_LOCK_STATUS_LOCK_MASK); /* Wait for '0xFFF' */ in ddr3_dfs_high_2_low()
664 /* [30:29] = 0 - Data Pup R/W path reset */ in ddr3_dfs_high_2_low()
665 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_high_2_low()
670 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_high_2_low()
675 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
682 reg &= ~0x74; /* CL [3:0]; [6:4],[2] */ in ddr3_dfs_high_2_low()
687 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_high_2_low()
694 reg &= ~0x38; /* CWL [5:3] */ in ddr3_dfs_high_2_low()
700 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_high_2_low()
724 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
728 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
731 * Poll DFS Register - 0x1528 [3] - DfsAtSR - in ddr3_dfs_high_2_low()
739 reg = (reg_read(REG_METAL_MASK_ADDR) | (1 << 0)); in ddr3_dfs_high_2_low()
740 /* [0] - Enable Dunit to crossbar retry */ in ddr3_dfs_high_2_low()
741 /* 0x14B0 - Dunit MMask Register */ in ddr3_dfs_high_2_low()
744 /* 0x1600 - PHY lock mask register */ in ddr3_dfs_high_2_low()
746 reg &= ~(1 << REG_ODPG_CNTRL_OFFS); /* [21] = 0 */ in ddr3_dfs_high_2_low()
749 /* 0x1670 - PHY lock mask register */ in ddr3_dfs_high_2_low()
751 reg |= ~REG_PHY_LOCK_MASK_MASK; /* [11:0] = FFF */ in ddr3_dfs_high_2_low()
773 u32 cs = 0; in ddr3_dfs_low_2_high()
789 /* [0] - DfsDllNextState - Enable */ in ddr3_dfs_low_2_high()
791 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
798 /* [0] - RetryMask - Disable */ in ddr3_dfs_low_2_high()
800 /* 0x14B0 - Dunit MMask Register */ in ddr3_dfs_low_2_high()
806 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
811 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
816 } while (reg == 0x0); /* 0x1528 [3] - DfsAtSR - Wait for '1' */ in ddr3_dfs_low_2_high()
824 /* 0xE8264[7:0] 0xff CPU Clock Dividers Reset mask */ in ddr3_dfs_low_2_high()
825 dfs_reg_write(CPU_PLL_CLOCK_DIVIDER_CNTRL0, (reg + 0xFF)); in ddr3_dfs_low_2_high()
830 /* 0xE8260 [15:8] 0x2 CPU Clock Dividers Reload Smooth enable */ in ddr3_dfs_low_2_high()
837 /* 0xE8260 [31:24] 0x2 Relax Enable */ in ddr3_dfs_low_2_high()
844 * 0xE8268 [13:8] N Set Training clock: in ddr3_dfs_low_2_high()
853 /* 0xE8264 [8]=0x1 CPU Clock Dividers Reload Ratio trigger set */ in ddr3_dfs_low_2_high()
862 /* 0xE8264 [8]=0x0 CPU Clock Dividers Reload Ratio trigger clear */ in ddr3_dfs_low_2_high()
871 * and force reserved bits[7:0]. in ddr3_dfs_low_2_high()
873 reg = 0x0000FFFF; in ddr3_dfs_low_2_high()
875 /* 0x18700 - CPU Div CLK control 0 */ in ddr3_dfs_low_2_high()
881 reg = 0x0000FF00; in ddr3_dfs_low_2_high()
882 /* 0x18704 - CPU Div CLK control 0 */ in ddr3_dfs_low_2_high()
889 /* 0x1870C - CPU Div CLK control 3 register */ in ddr3_dfs_low_2_high()
897 reg = 0x000FFF02; in ddr3_dfs_low_2_high()
903 reg = 0x0102FDFF; in ddr3_dfs_low_2_high()
911 * bits [7:0] == not in use in ddr3_dfs_low_2_high()
913 /* 0x18700 - CPU Div CLK control 0 register */ in ddr3_dfs_low_2_high()
919 * Poll Div CLK status 0 register - indication that the clocks in ddr3_dfs_low_2_high()
920 * are active - 0x18718 [8] in ddr3_dfs_low_2_high()
925 } while (reg == 0); in ddr3_dfs_low_2_high()
927 reg = 0x000000FF; in ddr3_dfs_low_2_high()
932 /* 0x18700 - CPU Div CLK control 0 register */ in ddr3_dfs_low_2_high()
942 /* 0x18488 - DRAM Init control status register */ in ddr3_dfs_low_2_high()
959 * [15] - Phy2UnitClkRatio = 0 - Set 1:1 Ratio between in ddr3_dfs_low_2_high()
965 dfs_reg_write(REG_DDR_IO_ADDR, reg); /* 0x1524 - DDR IO Register */ in ddr3_dfs_low_2_high()
973 /* 0x1404 - DDR Controller Control Low Register */ in ddr3_dfs_low_2_high()
982 if (dram_info->target_frequency == 0x8) in ddr3_dfs_low_2_high()
994 reg |= (((0) & REG_DFS_CWL_NEXT_STATE_MASK) << in ddr3_dfs_low_2_high()
1001 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1004 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_low_2_high()
1018 /* 0x15EC - DRAM PHY Config Register */ in ddr3_dfs_low_2_high()
1024 /* 0x15EC - DRAM PHY Config register */ in ddr3_dfs_low_2_high()
1031 /* 0x1674 [10:0] - Phy lock status Register */ in ddr3_dfs_low_2_high()
1037 /* [28] - DataPupRdRST = 0 */ in ddr3_dfs_low_2_high()
1043 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_low_2_high()
1047 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_low_2_high()
1053 /* [30:29] = 0 - Data Pup R/W path reset */ in ddr3_dfs_low_2_high()
1054 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_low_2_high()
1063 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_low_2_high()
1072 reg = (0xA & REG_SDRAM_OPERATION_CWA_RC_MASK) << in ddr3_dfs_low_2_high()
1079 reg |= ((0x0 & REG_SDRAM_OPERATION_CWA_DATA_MASK) << in ddr3_dfs_low_2_high()
1086 reg |= ((0x1 & REG_SDRAM_OPERATION_CWA_DATA_MASK) << in ddr3_dfs_low_2_high()
1093 reg |= ((0x2 & REG_SDRAM_OPERATION_CWA_DATA_MASK) << in ddr3_dfs_low_2_high()
1100 reg |= ((0x3 & REG_SDRAM_OPERATION_CWA_DATA_MASK) << in ddr3_dfs_low_2_high()
1105 reg |= (0x1 << REG_SDRAM_OPERATION_CWA_DELAY_SEL_OFFS); in ddr3_dfs_low_2_high()
1108 ~(0xF << REG_SDRAM_OPERATION_CS_OFFS)); in ddr3_dfs_low_2_high()
1110 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_low_2_high()
1123 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1126 * Poll - DFS Register - 0x1528 [3] - DfsAtSR - All DRAM in ddr3_dfs_low_2_high()
1131 } while (reg); /* Wait for '0' */ in ddr3_dfs_low_2_high()
1134 /* [3-0] = 0x2 - Refresh Command, [11-8] - enabled Cs */ in ddr3_dfs_low_2_high()
1136 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_low_2_high()
1141 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_low_2_high()
1150 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1157 /* [0] - RetryMask - Enable */ in ddr3_dfs_low_2_high()
1159 /* 0x14B0 - Dunit MMask Register */ in ddr3_dfs_low_2_high()
1162 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_low_2_high()
1172 reg |= ((tmp & 0x1) << REG_DDR3_MR0_CL_OFFS); in ddr3_dfs_low_2_high()
1173 reg |= ((tmp & 0xE) << REG_DDR3_MR0_CL_HIGH_OFFS); in ddr3_dfs_low_2_high()
1182 reg |= ((0) << REG_DDR3_MR2_CWL_OFFS); in ddr3_dfs_low_2_high()
1200 u32 cs = 0; in ddr3_dfs_low_2_high()
1208 reg = 0x0000FF00; in ddr3_dfs_low_2_high()
1211 /* 0x1600 - PHY lock mask register */ in ddr3_dfs_low_2_high()
1216 /* 0x1670 - PHY lock mask register */ in ddr3_dfs_low_2_high()
1218 reg &= REG_PHY_LOCK_MASK_MASK; /* [11:0] = 0 */ in ddr3_dfs_low_2_high()
1222 reg = reg_read(REG_DFS_ADDR); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1224 reg &= ~0x11; in ddr3_dfs_low_2_high()
1225 /* [0] - Enable - DRAM DLL after DFS */ in ddr3_dfs_low_2_high()
1226 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1229 /* [0] - disable */ in ddr3_dfs_low_2_high()
1230 reg = reg_read(REG_METAL_MASK_ADDR) & ~(1 << 0); in ddr3_dfs_low_2_high()
1231 /* 0x14B0 - Dunit MMask Register */ in ddr3_dfs_low_2_high()
1237 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1242 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1248 /* 0x1528 [3] - DfsAtSR */ in ddr3_dfs_low_2_high()
1251 } while (reg == 0x0); /* Wait for '1' */ in ddr3_dfs_low_2_high()
1262 /* [15] = 0 - Set 1:1 Ratio between Dunit and Phy */ in ddr3_dfs_low_2_high()
1266 dfs_reg_write(REG_DDR_IO_ADDR, reg); /* 0x1524 - DDR IO Register */ in ddr3_dfs_low_2_high()
1268 /* Switch HCLK Mux from (100Mhz) [16]=0, keep DFS request bit */ in ddr3_dfs_low_2_high()
1269 reg = 0x20040000; in ddr3_dfs_low_2_high()
1275 /* 0x18488 - DRAM Init control status register */ in ddr3_dfs_low_2_high()
1284 * force reserved bits[7:0]. in ddr3_dfs_low_2_high()
1286 reg = 0x0000FFFF; in ddr3_dfs_low_2_high()
1287 /* 0x18700 - CPU Div CLK control 0 */ in ddr3_dfs_low_2_high()
1293 reg = 0x0000FF00; in ddr3_dfs_low_2_high()
1294 /* 0x18704 - CPU Div CLK control 0 */ in ddr3_dfs_low_2_high()
1301 /* 0x1870C - CPU Div CLK control 3 register */ in ddr3_dfs_low_2_high()
1310 reg = 0x000FFF02; in ddr3_dfs_low_2_high()
1317 reg = 0x0102FDFF; in ddr3_dfs_low_2_high()
1325 * bits [7:0] == not in use in ddr3_dfs_low_2_high()
1327 /* 0x18700 - CPU Div CLK control 0 register */ in ddr3_dfs_low_2_high()
1333 * Poll Div CLK status 0 register - indication that the clocks are in ddr3_dfs_low_2_high()
1334 * active - 0x18718 [8] in ddr3_dfs_low_2_high()
1339 } while (reg == 0); in ddr3_dfs_low_2_high()
1341 reg = 0x000000FF; in ddr3_dfs_low_2_high()
1346 /* 0x18700 - CPU Div CLK control 0 register */ in ddr3_dfs_low_2_high()
1353 /* [28] = 0 - Pup Reset Divider B */ in ddr3_dfs_low_2_high()
1357 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_low_2_high()
1361 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_low_2_high()
1368 /* 0x15EC - DRAM PHY Config Register */ in ddr3_dfs_low_2_high()
1373 /* APLL lock indication - Poll Phy lock status Register - 0x1674 [9] */ in ddr3_dfs_low_2_high()
1377 } while (reg == 0); in ddr3_dfs_low_2_high()
1382 /* 0x15EC - DRAM PHY Config register */ in ddr3_dfs_low_2_high()
1388 * APLL lock indication - Poll Phy lock status Register - 0x1674 [11:0] in ddr3_dfs_low_2_high()
1397 /* [30:29] = 0 - Data Pup R/W path reset */ in ddr3_dfs_low_2_high()
1398 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_low_2_high()
1404 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_low_2_high()
1409 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1413 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1416 * Poll DFS Register - 0x1528 [3] - DfsAtSR - All DRAM devices on in ddr3_dfs_low_2_high()
1421 } while (reg); /* Wait for '0' */ in ddr3_dfs_low_2_high()
1423 /* 0x1404 */ in ddr3_dfs_low_2_high()
1424 reg = (reg_read(REG_DUNIT_CTRL_LOW_ADDR) & 0xFFFFFFE7) | 0x2; in ddr3_dfs_low_2_high()
1435 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_low_2_high()
1446 * [3-0] = 0x4 - MR1 Command, [11-8] - in ddr3_dfs_low_2_high()
1449 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_low_2_high()
1463 * [3-0] = 0x4 - MR1 Command, [11-8] - in ddr3_dfs_low_2_high()
1466 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_low_2_high()
1473 reg &= ~0x74; /* CL [3:0]; [6:4],[2] */ in ddr3_dfs_low_2_high()
1476 tmp = ddr3_cl_to_valid_cl(6) & 0xF; in ddr3_dfs_low_2_high()
1478 tmp = ddr3_cl_to_valid_cl(dram_info->cl) & 0xF; in ddr3_dfs_low_2_high()
1480 reg |= ((tmp & 0x1) << 2); in ddr3_dfs_low_2_high()
1486 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_low_2_high()
1493 reg &= ~0x38; /* CWL [5:3] */ in ddr3_dfs_low_2_high()
1494 /* CWL = 0 ,for 400 MHg is 5 */ in ddr3_dfs_low_2_high()
1500 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_low_2_high()
1525 dfs_reg_write(REG_SDRAM_ODT_CTRL_HIGH_ADDR, 0); in ddr3_dfs_low_2_high()
1529 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1532 /* 0x1600 - PHY lock mask register */ in ddr3_dfs_low_2_high()
1534 reg &= ~(1 << REG_ODPG_CNTRL_OFFS); /* [21] = 0 */ in ddr3_dfs_low_2_high()
1538 /* 0x1670 - PHY lock mask register */ in ddr3_dfs_low_2_high()
1540 reg |= ~REG_PHY_LOCK_MASK_MASK; /* [11:0] = FFF */ in ddr3_dfs_low_2_high()
1543 reg = reg_read(REG_METAL_MASK_ADDR) | (1 << 0); /* [0] - disable */ in ddr3_dfs_low_2_high()
1544 /* 0x14B0 - Dunit MMask Register */ in ddr3_dfs_low_2_high()